aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-ixp23xx/memory.h2
-rw-r--r--include/asm-arm/arch-l7200/serial_l7200.h2
-rw-r--r--include/asm-arm/arch-l7200/uncompress.h2
-rw-r--r--include/asm-arm/arch-lh7a40x/clocks.h20
-rw-r--r--include/asm-arm/arch-lh7a40x/constants.h8
-rw-r--r--include/asm-arm/arch-lh7a40x/dma.h79
-rw-r--r--include/asm-arm/arch-lh7a40x/entry-macro.S70
-rw-r--r--include/asm-arm/arch-lh7a40x/hardware.h4
-rw-r--r--include/asm-arm/arch-lh7a40x/irqs.h7
-rw-r--r--include/asm-arm/arch-lh7a40x/registers.h64
-rw-r--r--include/asm-arm/arch-lh7a40x/ssp.h71
-rw-r--r--include/asm-arm/arch-lh7a40x/uncompress.h2
-rw-r--r--include/asm-arm/arch-pnx4008/clock.h61
-rw-r--r--include/asm-arm/arch-pnx4008/debug-macro.S27
-rw-r--r--include/asm-arm/arch-pnx4008/dma.h162
-rw-r--r--include/asm-arm/arch-pnx4008/entry-macro.S121
-rw-r--r--include/asm-arm/arch-pnx4008/gpio.h139
-rw-r--r--include/asm-arm/arch-pnx4008/hardware.h32
-rw-r--r--include/asm-arm/arch-pnx4008/io.h21
-rw-r--r--include/asm-arm/arch-pnx4008/irq.h42
-rw-r--r--include/asm-arm/arch-pnx4008/irqs.h215
-rw-r--r--include/asm-arm/arch-pnx4008/memory.h24
-rw-r--r--include/asm-arm/arch-pnx4008/param.h21
-rw-r--r--include/asm-arm/arch-pnx4008/platform.h69
-rw-r--r--include/asm-arm/arch-pnx4008/pm.h62
-rw-r--r--include/asm-arm/arch-pnx4008/system.h38
-rw-r--r--include/asm-arm/arch-pnx4008/timex.h73
-rw-r--r--include/asm-arm/arch-pnx4008/uncompress.h46
-rw-r--r--include/asm-arm/arch-pnx4008/vmalloc.h20
-rw-r--r--include/asm-arm/arch-pxa/ohci.h2
-rw-r--r--include/asm-arm/arch-s3c2410/map.h11
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h6
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h5
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h5
-rw-r--r--include/asm-arm/mach/time.h1
-rw-r--r--include/asm-arm/system.h6
36 files changed, 1507 insertions, 33 deletions
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h
index 6e19f46d54d1..c85fc06a043c 100644
--- a/include/asm-arm/arch-ixp23xx/memory.h
+++ b/include/asm-arm/arch-ixp23xx/memory.h
@@ -49,7 +49,7 @@ static inline int __ixp23xx_arch_is_coherent(void)
49{ 49{
50 extern unsigned int processor_id; 50 extern unsigned int processor_id;
51 51
52 if (((processor_id & 15) >= 2) || machine_is_roadrunner()) 52 if (((processor_id & 15) >= 4) || machine_is_roadrunner())
53 return 1; 53 return 1;
54 54
55 return 0; 55 return 0;
diff --git a/include/asm-arm/arch-l7200/serial_l7200.h b/include/asm-arm/arch-l7200/serial_l7200.h
index 238c595d97ea..b1008a9d23e5 100644
--- a/include/asm-arm/arch-l7200/serial_l7200.h
+++ b/include/asm-arm/arch-l7200/serial_l7200.h
@@ -28,7 +28,7 @@
28#define UARTDR 0x00 /* Tx/Rx data */ 28#define UARTDR 0x00 /* Tx/Rx data */
29#define RXSTAT 0x04 /* Rx status */ 29#define RXSTAT 0x04 /* Rx status */
30#define H_UBRLCR 0x08 /* mode register high */ 30#define H_UBRLCR 0x08 /* mode register high */
31#define M_UBRLCR 0x0C /* mode reg mid (MSB of buad)*/ 31#define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/
32#define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/ 32#define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/
33#define UARTCON 0x14 /* control register */ 33#define UARTCON 0x14 /* control register */
34#define UARTFLG 0x18 /* flag register */ 34#define UARTFLG 0x18 /* flag register */
diff --git a/include/asm-arm/arch-l7200/uncompress.h b/include/asm-arm/arch-l7200/uncompress.h
index 9fcd40aee3e3..04be2a088639 100644
--- a/include/asm-arm/arch-l7200/uncompress.h
+++ b/include/asm-arm/arch-l7200/uncompress.h
@@ -6,7 +6,7 @@
6 * Changelog: 6 * Changelog:
7 * 05-01-2000 SJH Created 7 * 05-01-2000 SJH Created
8 * 05-13-2000 SJH Filled in function bodies 8 * 05-13-2000 SJH Filled in function bodies
9 * 07-26-2000 SJH Removed hard coded buad rate 9 * 07-26-2000 SJH Removed hard coded baud rate
10 */ 10 */
11 11
12#include <asm/hardware.h> 12#include <asm/hardware.h>
diff --git a/include/asm-arm/arch-lh7a40x/clocks.h b/include/asm-arm/arch-lh7a40x/clocks.h
new file mode 100644
index 000000000000..bee02fd8dab1
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/clocks.h
@@ -0,0 +1,20 @@
1/* include/asm-arm/arch-lh7a40x/clocks.h
2 *
3 * Copyright (C) 2004 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/config.h>
12
13#ifndef __ASM_ARCH_CLOCKS_H
14#define __ASM_ARCH_CLOCKS_H
15
16unsigned int fclkfreq_get (void);
17unsigned int hclkfreq_get (void);
18unsigned int pclkfreq_get (void);
19
20#endif /* _ASM_ARCH_CLOCKS_H */
diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h
index 267d1145c3f9..51de96e87faf 100644
--- a/include/asm-arm/arch-lh7a40x/constants.h
+++ b/include/asm-arm/arch-lh7a40x/constants.h
@@ -28,8 +28,7 @@
28 28
29#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) 29#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
30 30
31# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */ 31# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */
32/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */
33# define IOBARRIER_VIRT 0xf0000000 32# define IOBARRIER_VIRT 0xf0000000
34# define IOBARRIER_SIZE PAGE_SIZE 33# define IOBARRIER_SIZE PAGE_SIZE
35 34
@@ -52,6 +51,9 @@
52# define CPLD08_PHYS CPLDX_PHYS (0x08) 51# define CPLD08_PHYS CPLDX_PHYS (0x08)
53# define CPLD08_VIRT CPLDX_VIRT (0x08) 52# define CPLD08_VIRT CPLDX_VIRT (0x08)
54# define CPLD08_SIZE PAGE_SIZE 53# define CPLD08_SIZE PAGE_SIZE
54# define CPLD0A_PHYS CPLDX_PHYS (0x0a)
55# define CPLD0A_VIRT CPLDX_VIRT (0x0a)
56# define CPLD0A_SIZE PAGE_SIZE
55# define CPLD0C_PHYS CPLDX_PHYS (0x0c) 57# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
56# define CPLD0C_VIRT CPLDX_VIRT (0x0c) 58# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
57# define CPLD0C_SIZE PAGE_SIZE 59# define CPLD0C_SIZE PAGE_SIZE
@@ -83,5 +85,7 @@
83#define XTAL_IN 14745600 /* 14.7456 MHz crystal */ 85#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
84#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ 86#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
85#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ 87#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
88#define HCLK (99993600)
89//#define HCLK (119808000)
86 90
87#endif /* __ASM_ARCH_CONSTANTS_H */ 91#endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h
index 15492e3253f6..a8cbd14bbf9d 100644
--- a/include/asm-arm/arch-lh7a40x/dma.h
+++ b/include/asm-arm/arch-lh7a40x/dma.h
@@ -1,9 +1,86 @@
1/* include/asm-arm/arch-lh7a40x/dma.h 1/* include/asm-arm/arch-lh7a40x/dma.h
2 * 2 *
3 * Copyright (C) 2003 Coastal Environmental Systems 3 * Copyright (C) 2005 Marc Singer
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation. 7 * version 2 as published by the Free Software Foundation.
8 * 8 *
9 */ 9 */
10
11typedef enum {
12 DMA_M2M0 = 0,
13 DMA_M2M1 = 1,
14 DMA_M2P0 = 2, /* Tx */
15 DMA_M2P1 = 3, /* Rx */
16 DMA_M2P2 = 4, /* Tx */
17 DMA_M2P3 = 5, /* Rx */
18 DMA_M2P4 = 6, /* Tx - AC97 */
19 DMA_M2P5 = 7, /* Rx - AC97 */
20 DMA_M2P6 = 8, /* Tx */
21 DMA_M2P7 = 9, /* Rx */
22} dma_device_t;
23
24#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */
25
26#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
27#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
28
29#define DMAC_GIR_MMI1 (1<<11)
30#define DMAC_GIR_MMI0 (1<<10)
31#define DMAC_GIR_MPI8 (1<<9)
32#define DMAC_GIR_MPI9 (1<<8)
33#define DMAC_GIR_MPI6 (1<<7)
34#define DMAC_GIR_MPI7 (1<<6)
35#define DMAC_GIR_MPI4 (1<<5)
36#define DMAC_GIR_MPI5 (1<<4)
37#define DMAC_GIR_MPI2 (1<<3)
38#define DMAC_GIR_MPI3 (1<<2)
39#define DMAC_GIR_MPI0 (1<<1)
40#define DMAC_GIR_MPI1 (1<<0)
41
42#define DMAC_M2P0 0x0000
43#define DMAC_M2P1 0x0040
44#define DMAC_M2P2 0x0080
45#define DMAC_M2P3 0x00c0
46#define DMAC_M2P4 0x0240
47#define DMAC_M2P5 0x0200
48#define DMAC_M2P6 0x02c0
49#define DMAC_M2P7 0x0280
50#define DMAC_M2P8 0x0340
51#define DMAC_M2P9 0x0300
52#define DMAC_M2M0 0x0100
53#define DMAC_M2M1 0x0140
54
55#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
56#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
57#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
58#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
59#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
60#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
61#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
62#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28)
63#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30)
64#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34)
65#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38)
66
67#define DMAC_PCONTROL_ENABLE (1<<4)
68
69#define DMAC_PORT_USB 0
70#define DMAC_PORT_SDMMC 1
71#define DMAC_PORT_AC97_1 2
72#define DMAC_PORT_AC97_2 3
73#define DMAC_PORT_AC97_3 4
74#define DMAC_PORT_UART1 6
75#define DMAC_PORT_UART2 7
76#define DMAC_PORT_UART3 8
77
78#define DMAC_PSTATUS_CURRSTATE_SHIFT 4
79#define DMAC_PSTATUS_CURRSTATE_MASK 0x3
80
81#define DMAC_PSTATUS_NEXTBUF (1<<6)
82#define DMAC_PSTATUS_STALLRINT (1<<0)
83
84#define DMAC_INT_CHE (1<<3)
85#define DMAC_INT_NFB (1<<1)
86#define DMAC_INT_STALL (1<<0)
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S
index a2f67c06d9c9..9fc7f4988124 100644
--- a/include/asm-arm/arch-lh7a40x/entry-macro.S
+++ b/include/asm-arm/arch-lh7a40x/entry-macro.S
@@ -10,11 +10,73 @@
10#include <asm/hardware.h> 10#include <asm/hardware.h>
11#include <asm/arch/irqs.h> 11#include <asm/arch/irqs.h>
12 12
13# if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) 13/* In order to allow there to be support for both of the processor
14# error "LH7A400 and LH7A404 are mutually exclusive" 14 classes at the same time, we make a hack here that isn't very
15# endif 15 pretty. At startup, the link pointed to with the
16 branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
17 detected as a lh7a404.
16 18
17# if defined (CONFIG_ARCH_LH7A400) 19 *** FIXME: we should clean this up so that there is only one
20 implementation for each CPU's design.
21
22*/
23
24#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
25
26 .macro disable_fiq
27 .endm
28
29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30
31branch_irq_lh7a400: b 1000f
32
33@ Implementation of the LH7A404 get_irqnr_and_base.
34
35 mov \irqnr, #0 @ VIC1 irq base
36 mov \base, #io_p2v(0x80000000) @ APB registers
37 add \base, \base, #0x8000
38 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
39 tst \tmp, #VA_VECTORED @ Direct vectored
40 bne 1002f
41 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
42 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
43 bne 1001f
44 add \base, \base, #(0xa000 - 0x8000)
45 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
46 tst \tmp, #VA_VECTORED @ Direct vectored
47 bne 1002f
48 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
49 mov \irqnr, #32 @ VIC2 irq base
50
511001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
52 bcs 1008f @ Bit set; irq found
53 add \irqnr, \irqnr, #1
54 bne 1001b @ Until no bits
55 b 1009f @ Nothing? Hmm.
561002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
571008: movs \irqstat, #1 @ Force !Z
58 str \tmp, [\base, #0x0030] @ Clear vector
59 b 1009f
60
61@ Implementation of the LH7A400 get_irqnr_and_base.
62
631000: mov \irqnr, #0
64 mov \base, #io_p2v(0x80000000) @ APB registers
65 ldr \irqstat, [\base, #0x500] @ PIC INTSR
66
671001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
68 bcs 1008f @ Bit set; irq found
69 add \irqnr, \irqnr, #1
70 bne 1001b @ Until no bits
71 b 1009f @ Nothing? Hmm.
721008: movs \irqstat, #1 @ Force !Z
73
741009:
75 .endm
76
77
78
79#elif defined (CONFIG_ARCH_LH7A400)
18 .macro disable_fiq 80 .macro disable_fiq
19 .endm 81 .endm
20 82
diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h
index aeb07c162e25..e9ff74fd7939 100644
--- a/include/asm-arm/arch-lh7a40x/hardware.h
+++ b/include/asm-arm/arch-lh7a40x/hardware.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_HARDWARE_H 13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H 14#define __ASM_ARCH_HARDWARE_H
15 15
16#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */
17
16#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) 18#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
17#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff)) 19#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
18 20
@@ -53,6 +55,8 @@ typedef struct { volatile u8 offset[4096]; } __regbase8;
53 55
54#endif 56#endif
55 57
58#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s)
59
56#include "registers.h" 60#include "registers.h"
57 61
58#endif /* _ASM_ARCH_HARDWARE_H */ 62#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h
index 189908b2b79a..afe8c7cbad6a 100644
--- a/include/asm-arm/arch-lh7a40x/irqs.h
+++ b/include/asm-arm/arch-lh7a40x/irqs.h
@@ -153,9 +153,10 @@
153#if !defined (IRQ_GPIO0INTR) 153#if !defined (IRQ_GPIO0INTR)
154# define IRQ_GPIO0INTR IRQ_GPIO0FIQ 154# define IRQ_GPIO0INTR IRQ_GPIO0FIQ
155#endif 155#endif
156#define IRQ_TICK IRQ_TINTR 156#define IRQ_TICK IRQ_TINTR
157#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ 157#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */
158#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ 158#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */
159#define IRQ_USB IRQ_USBINTR /* USB device */
159 160
160#ifdef CONFIG_MACH_KEV7A400 161#ifdef CONFIG_MACH_KEV7A400
161# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ 162# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */
@@ -190,6 +191,10 @@
190# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ 191# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */
191#endif 192#endif
192 193
194#if defined (CONFIG_MACH_LPD7A400)
195# define IRQ_TOUCH IRQ_LPD7A400_TS
196#endif
197
193#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) 198#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD)
194 199
195#endif 200#endif
diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h
index 3b0d4fcd36f7..b4f09b3e2d03 100644
--- a/include/asm-arm/arch-lh7a40x/registers.h
+++ b/include/asm-arm/arch-lh7a40x/registers.h
@@ -17,7 +17,7 @@
17 17
18 /* Physical register base addresses */ 18 /* Physical register base addresses */
19 19
20#define AC97_PHYS (0x80000000) /* AC97 Controller */ 20#define AC97C_PHYS (0x80000000) /* AC97 Controller */
21#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */ 21#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
22#define USB_PHYS (0x80000200) /* USB Client */ 22#define USB_PHYS (0x80000200) /* USB Client */
23#define SCI_PHYS (0x80000300) /* Secure Card Interface */ 23#define SCI_PHYS (0x80000300) /* Secure Card Interface */
@@ -34,6 +34,8 @@
34#define RTC_PHYS (0x80000d00) /* Real-time Clock */ 34#define RTC_PHYS (0x80000d00) /* Real-time Clock */
35#define GPIO_PHYS (0x80000e00) /* General Purpose IO */ 35#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
36#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */ 36#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
37#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */
38#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */
37#define WDT_PHYS (0x80001400) /* Watchdog Timer */ 39#define WDT_PHYS (0x80001400) /* Watchdog Timer */
38#define SMC_PHYS (0x80002000) /* Static Memory Controller */ 40#define SMC_PHYS (0x80002000) /* Static Memory Controller */
39#define SDRC_PHYS (0x80002400) /* SDRAM Controller */ 41#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
@@ -42,6 +44,7 @@
42 44
43 /* Physical registers of the LH7A404 */ 45 /* Physical registers of the LH7A404 */
44 46
47#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */
45#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */ 48#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
46#define USBH_PHYS (0x80009000) /* USB OHCI host controller */ 49#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
47#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */ 50#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
@@ -52,10 +55,32 @@
52 55
53 /* Clock/State Controller register */ 56 /* Clock/State Controller register */
54 57
58#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
55#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */ 59#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
60#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
61#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
56 62
57#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */ 63#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
58 64#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
65#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
66#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
67#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
68#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
69#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
70#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
71#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
72#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
73#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
74#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
75#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
76
77#define CSC_PWRSR_CHIPMAN_SHIFT (24)
78#define CSC_PWRSR_CHIPMAN_MASK (0xff)
79#define CSC_PWRSR_CHIPID_SHIFT (16)
80#define CSC_PWRSR_CHIPID_MASK (0xff)
81
82#define CSC_USBDRESET_APBRESETREG (1<<1)
83#define CSC_USBDRESET_IORESETREG (1<<0)
59 84
60 /* Interrupt Controller registers */ 85 /* Interrupt Controller registers */
61 86
@@ -108,6 +133,13 @@
108#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */ 133#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
109#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */ 134#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
110#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */ 135#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
136#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
137#define GPIO_PADD __REG(GPIO_PHYS + 0x10)
138#define GPIO_PAD __REG(GPIO_PHYS + 0x00)
139#define GPIO_PCD __REG(GPIO_PHYS + 0x08)
140#define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
141#define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
142#define GPIO_PED __REG(GPIO_PHYS + 0x20)
111 143
112 144
113 /* Static Memory Controller registers */ 145 /* Static Memory Controller registers */
@@ -137,20 +169,21 @@
137#endif 169#endif
138 170
139#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) 171#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
140# define CPLD_CONTROL __REG8(CPLD02_PHYS)
141# define CPLD_SPI_DATA __REG8(CPLD06_PHYS)
142# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS)
143# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS)
144# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */
145# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS)
146# define CPLD_FLASH __REG8(CPLD10_PHYS)
147# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS)
148# define CPLD_REVISION __REG8(CPLD14_PHYS)
149# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS)
150# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS)
151# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS)
152#endif
153 172
173# define CPLD_CONTROL __REG16(CPLD02_PHYS)
174# define CPLD_SPI_DATA __REG16(CPLD06_PHYS)
175# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS)
176# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS)
177# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */
178# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS)
179# define CPLD_FLASH __REG16(CPLD10_PHYS)
180# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS)
181# define CPLD_REVISION __REG16(CPLD14_PHYS)
182# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS)
183# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS)
184# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS)
185
186#endif
154 187
155 /* Timer registers */ 188 /* Timer registers */
156 189
@@ -189,4 +222,3 @@
189 222
190 223
191#endif /* _ASM_ARCH_REGISTERS_H */ 224#endif /* _ASM_ARCH_REGISTERS_H */
192
diff --git a/include/asm-arm/arch-lh7a40x/ssp.h b/include/asm-arm/arch-lh7a40x/ssp.h
new file mode 100644
index 000000000000..132b1c4d5ce6
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/ssp.h
@@ -0,0 +1,71 @@
1/* ssp.h
2 $Id$
3
4 written by Marc Singer
5 6 Dec 2004
6
7 Copyright (C) 2004 Marc Singer
8
9 -----------
10 DESCRIPTION
11 -----------
12
13 This SSP header is available throughout the kernel, for this
14 machine/architecture, because drivers that use it may be dispersed.
15
16 This file was cloned from the 7952x implementation. It would be
17 better to share them, but we're taking an easier approach for the
18 time being.
19
20*/
21
22#if !defined (__SSP_H__)
23# define __SSP_H__
24
25/* ----- Includes */
26
27/* ----- Types */
28
29struct ssp_driver {
30 int (*init) (void);
31 void (*exit) (void);
32 void (*acquire) (void);
33 void (*release) (void);
34 int (*configure) (int device, int mode, int speed,
35 int frame_size_write, int frame_size_read);
36 void (*chip_select) (int enable);
37 void (*set_callbacks) (void* handle,
38 irqreturn_t (*callback_tx)(void*),
39 irqreturn_t (*callback_rx)(void*));
40 void (*enable) (void);
41 void (*disable) (void);
42// int (*save_state) (void*);
43// void (*restore_state) (void*);
44 int (*read) (void);
45 int (*write) (u16 data);
46 int (*write_read) (u16 data);
47 void (*flush) (void);
48 void (*write_async) (void* pv, size_t cb);
49 size_t (*write_pos) (void);
50};
51
52 /* These modes are only available on the LH79524 */
53#define SSP_MODE_SPI (1)
54#define SSP_MODE_SSI (2)
55#define SSP_MODE_MICROWIRE (3)
56#define SSP_MODE_I2S (4)
57
58 /* CPLD SPI devices */
59#define DEVICE_EEPROM 0 /* Configuration eeprom */
60#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */
61#define DEVICE_CODEC 2 /* Audio codec */
62#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */
63
64/* ----- Globals */
65
66/* ----- Prototypes */
67
68//extern struct ssp_driver lh79520_i2s_driver;
69extern struct ssp_driver lh7a400_cpld_ssp_driver;
70
71#endif /* __SSP_H__ */
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
index f8053346f608..3d1ce0426a33 100644
--- a/include/asm-arm/arch-lh7a40x/uncompress.h
+++ b/include/asm-arm/arch-lh7a40x/uncompress.h
@@ -16,7 +16,7 @@
16#ifndef UART_R_STATUS 16#ifndef UART_R_STATUS
17# define UART_R_STATUS (0x10) 17# define UART_R_STATUS (0x10)
18#endif 18#endif
19#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ 19#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
20 20
21 /* Access UART with physical addresses before MMU is setup */ 21 /* Access UART with physical addresses before MMU is setup */
22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) 22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
diff --git a/include/asm-arm/arch-pnx4008/clock.h b/include/asm-arm/arch-pnx4008/clock.h
new file mode 100644
index 000000000000..91ae0030fdf2
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/clock.h
@@ -0,0 +1,61 @@
1/*
2 * include/asm-arm/arch-pnx4008/clock.h
3 *
4 * Clock control driver for PNX4008 - header file
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __PNX4008_CLOCK_H__
14#define __PNX4008_CLOCK_H__
15
16struct module;
17struct clk;
18
19#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
20#define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40)
21#define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44)
22#define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48)
23#define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c)
24#define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50)
25#define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58)
26#define USBCTRL_REG (PWRMAN_VA_BASE + 0x64)
27#define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68)
28#define MSCTRL_REG (PWRMAN_VA_BASE + 0x80)
29#define BTCLKCTRL (PWRMAN_VA_BASE + 0x84)
30#define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90)
31#define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac)
32#define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0)
33#define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4)
34#define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8)
35#define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4)
36#define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8)
37#define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0)
38#define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4)
39#define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8)
40#define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec)
41#define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc)
42
43#define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
44#define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60)
45#define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64)
46#define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68)
47#define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C)
48
49#define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
50
51#define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE)
52
53#define CLK_RATE_13MHZ 13000
54#define CLK_RATE_1MHZ 1000
55#define CLK_RATE_208MHZ 208000
56#define CLK_RATE_48MHZ 48000
57#define CLK_RATE_32KHZ 32
58
59#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
60
61#endif
diff --git a/include/asm-arm/arch-pnx4008/debug-macro.S b/include/asm-arm/arch-pnx4008/debug-macro.S
new file mode 100644
index 000000000000..eb3839de389a
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/debug-macro.S
@@ -0,0 +1,27 @@
1/* linux/include/asm-arm/arch-pnx4008/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 mov \rx, #0x00090000
18 addeq \rx, \rx, #0x40000000
19 addne \rx, \rx, #0xf4000000
20 .endm
21
22 .macro senduart,rd,rx
23 strb \rd, [\rx, #0x0]
24 .endm
25
26#define UART_SHIFT 2
27#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-pnx4008/dma.h b/include/asm-arm/arch-pnx4008/dma.h
new file mode 100644
index 000000000000..3aee1204795b
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/dma.h
@@ -0,0 +1,162 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/dma.h
3 *
4 * PNX4008 DMA header file
5 *
6 * Author: Vitaly Wool
7 * Copyright: MontaVista Software Inc. (c) 2005
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_DMA_H
15#define __ASM_ARCH_DMA_H
16
17#include "platform.h"
18
19#define MAX_DMA_ADDRESS 0xffffffff
20
21#define MAX_DMA_CHANNELS 8
22
23#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
24#define DMAC_INT_STAT (DMAC_BASE + 0x0000)
25#define DMAC_INT_TC_STAT (DMAC_BASE + 0x0004)
26#define DMAC_INT_TC_CLEAR (DMAC_BASE + 0x0008)
27#define DMAC_INT_ERR_STAT (DMAC_BASE + 0x000c)
28#define DMAC_INT_ERR_CLEAR (DMAC_BASE + 0x0010)
29#define DMAC_SOFT_SREQ (DMAC_BASE + 0x0024)
30#define DMAC_CONFIG (DMAC_BASE + 0x0030)
31#define DMAC_Cx_SRC_ADDR(c) (DMAC_BASE + 0x0100 + (c) * 0x20)
32#define DMAC_Cx_DEST_ADDR(c) (DMAC_BASE + 0x0104 + (c) * 0x20)
33#define DMAC_Cx_LLI(c) (DMAC_BASE + 0x0108 + (c) * 0x20)
34#define DMAC_Cx_CONTROL(c) (DMAC_BASE + 0x010c + (c) * 0x20)
35#define DMAC_Cx_CONFIG(c) (DMAC_BASE + 0x0110 + (c) * 0x20)
36
37enum {
38 WIDTH_BYTE = 0,
39 WIDTH_HWORD,
40 WIDTH_WORD
41};
42
43enum {
44 FC_MEM2MEM_DMA,
45 FC_MEM2PER_DMA,
46 FC_PER2MEM_DMA,
47 FC_PER2PER_DMA,
48 FC_PER2PER_DPER,
49 FC_MEM2PER_PER,
50 FC_PER2MEM_PER,
51 FC_PER2PER_SPER
52};
53
54enum {
55 DMA_INT_UNKNOWN = 0,
56 DMA_ERR_INT = 1,
57 DMA_TC_INT = 2,
58};
59
60enum {
61 DMA_BUFFER_ALLOCATED = 1,
62 DMA_HAS_LL = 2,
63};
64
65enum {
66 PER_CAM_DMA_1 = 0,
67 PER_NDF_FLASH = 1,
68 PER_MBX_SLAVE_FIFO = 2,
69 PER_SPI2_REC_XMIT = 3,
70 PER_MS_SD_RX_XMIT = 4,
71 PER_HS_UART_1_XMIT = 5,
72 PER_HS_UART_1_RX = 6,
73 PER_HS_UART_2_XMIT = 7,
74 PER_HS_UART_2_RX = 8,
75 PER_HS_UART_7_XMIT = 9,
76 PER_HS_UART_7_RX = 10,
77 PER_SPI1_REC_XMIT = 11,
78 PER_MLC_NDF_SREC = 12,
79 PER_CAM_DMA_2 = 13,
80 PER_PRNG_INFIFO = 14,
81 PER_PRNG_OUTFIFO = 15,
82};
83
84struct pnx4008_dma_ch_ctrl {
85 int tc_mask;
86 int cacheable;
87 int bufferable;
88 int priv_mode;
89 int di;
90 int si;
91 int dest_ahb1;
92 int src_ahb1;
93 int dwidth;
94 int swidth;
95 int dbsize;
96 int sbsize;
97 int tr_size;
98};
99
100struct pnx4008_dma_ch_config {
101 int halt;
102 int active;
103 int lock;
104 int itc;
105 int ie;
106 int flow_cntrl;
107 int dest_per;
108 int src_per;
109};
110
111struct pnx4008_dma_ll {
112 unsigned long src_addr;
113 unsigned long dest_addr;
114 u32 next_dma;
115 unsigned long ch_ctrl;
116 struct pnx4008_dma_ll *next;
117 int flags;
118 void *alloc_data;
119 int (*free) (void *);
120};
121
122struct pnx4008_dma_config {
123 int is_ll;
124 unsigned long src_addr;
125 unsigned long dest_addr;
126 unsigned long ch_ctrl;
127 unsigned long ch_cfg;
128 struct pnx4008_dma_ll *ll;
129 u32 ll_dma;
130 int flags;
131 void *alloc_data;
132 int (*free) (void *);
133};
134
135extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
136extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
137extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
138
139extern int pnx4008_request_channel(char *, int,
140 void (*)(int, int, void *, struct pt_regs *),
141 void *);
142extern void pnx4008_free_channel(int);
143extern int pnx4008_config_dma(int, int, int);
144extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
145 unsigned long *);
146extern int pnx4008_dma_parse_control(unsigned long,
147 struct pnx4008_dma_ch_ctrl *);
148extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
149 unsigned long *);
150extern int pnx4008_dma_parse_config(unsigned long,
151 struct pnx4008_dma_ch_config *);
152extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
153extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
154extern int pnx4008_dma_ch_enable(int);
155extern int pnx4008_dma_ch_disable(int);
156extern int pnx4008_dma_ch_enabled(int);
157extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
158 struct pnx4008_dma_ch_ctrl *);
159extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
160 struct pnx4008_dma_ch_ctrl *);
161
162#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-pnx4008/entry-macro.S b/include/asm-arm/arch-pnx4008/entry-macro.S
new file mode 100644
index 000000000000..c1c198e3680b
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/entry-macro.S
@@ -0,0 +1,121 @@
1/*
2 * include/asm-arm/arch-pnx4008/entry-macro.S
3 *
4 * Low-level IRQ helper macros for PNX4008-based platforms
5 *
6 * 2005-2006 (c) MontaVista Software, Inc.
7 * Author: Vitaly Wool <vwool@ru.mvista.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include "platform.h"
14
15#define IO_BASE 0xF0000000
16#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
17
18#define INTRC_MASK 0x00
19#define INTRC_RAW_STAT 0x04
20#define INTRC_STAT 0x08
21#define INTRC_POLAR 0x0C
22#define INTRC_ACT_TYPE 0x10
23#define INTRC_TYPE 0x14
24
25#define SIC1_BASE_INT 32
26#define SIC2_BASE_INT 64
27
28 .macro disable_fiq
29 .endm
30
31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
32/* decode the MIC interrupt numbers */
33 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
34 ldr \irqstat, [\base, #INTRC_STAT]
35
36 cmp \irqstat,#1<<16
37 movhs \irqnr,#16
38 movlo \irqnr,#0
39 movhs \irqstat,\irqstat,lsr#16
40 cmp \irqstat,#1<<8
41 addhs \irqnr,\irqnr,#8
42 movhs \irqstat,\irqstat,lsr#8
43 cmp \irqstat,#1<<4
44 addhs \irqnr,\irqnr,#4
45 movhs \irqstat,\irqstat,lsr#4
46 cmp \irqstat,#1<<2
47 addhs \irqnr,\irqnr,#2
48 movhs \irqstat,\irqstat,lsr#2
49 cmp \irqstat,#1<<1
50 addhs \irqnr,\irqnr,#1
51
52/* was there an interrupt ? if not then drop out with EQ status */
53 teq \irqstat,#0
54 beq 1003f
55
56/* and now check for extended IRQ reasons */
57 cmp \irqnr,#1
58 bls 1003f
59 cmp \irqnr,#30
60 blo 1002f
61
62/* IRQ 31,30 : High priority cascade IRQ handle */
63/* read the correct SIC */
64/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
65/* set the base IRQ number */
66 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
67 moveq \irqnr,#SIC1_BASE_INT
68 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
69 movne \irqnr,#SIC2_BASE_INT
70 ldr \irqstat, [\base, #INTRC_STAT]
71 ldr \tmp, [\base, #INTRC_TYPE]
72/* and with inverted mask : low priority interrupts */
73 and \irqstat,\irqstat,\tmp
74 b 1004f
75
761003:
77/* IRQ 1,0 : Low priority cascade IRQ handle */
78/* read the correct SIC */
79/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
80/* read the correct SIC */
81/* set the base IRQ number */
82 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
83 movne \irqnr,#SIC1_BASE_INT
84 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
85 moveq \irqnr,#SIC2_BASE_INT
86 ldr \irqstat, [\base, #INTRC_STAT]
87 ldr \tmp, [\base, #INTRC_TYPE]
88/* and with inverted mask : low priority interrupts */
89 bic \irqstat,\irqstat,\tmp
90
911004:
92
93 cmp \irqstat,#1<<16
94 addhs \irqnr,\irqnr,#16
95 movhs \irqstat,\irqstat,lsr#16
96 cmp \irqstat,#1<<8
97 addhs \irqnr,\irqnr,#8
98 movhs \irqstat,\irqstat,lsr#8
99 cmp \irqstat,#1<<4
100 addhs \irqnr,\irqnr,#4
101 movhs \irqstat,\irqstat,lsr#4
102 cmp \irqstat,#1<<2
103 addhs \irqnr,\irqnr,#2
104 movhs \irqstat,\irqstat,lsr#2
105 cmp \irqstat,#1<<1
106 addhs \irqnr,\irqnr,#1
107
108
109/* is irqstat not zero */
110
1111002:
112/* we assert that irqstat is not equal to zero and return ne status if true*/
113 teq \irqstat,#0
1141003:
115 .endm
116
117
118 .macro irq_prio_table
119 .endm
120
121
diff --git a/include/asm-arm/arch-pnx4008/gpio.h b/include/asm-arm/arch-pnx4008/gpio.h
new file mode 100644
index 000000000000..1fa5a77c3010
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/gpio.h
@@ -0,0 +1,139 @@
1/*
2 * include/asm-arm/arch-pnx4008/gpio.h
3 *
4 * PNX4008 GPIO driver - header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
9 * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17#ifndef _PNX4008_GPIO_H_
18#define _PNX4008_GPIO_H_
19
20
21/* Block numbers */
22#define GPIO_IN (0)
23#define GPIO_OUT (0x100)
24#define GPIO_BID (0x200)
25#define GPIO_RAM (0x300)
26#define GPIO_MUX (0x400)
27
28#define GPIO_TYPE_MASK(K) ((K) & 0x700)
29
30/* INPUT GPIOs */
31/* GPI */
32#define GPI_00 (GPIO_IN | 0)
33#define GPI_01 (GPIO_IN | 1)
34#define GPI_02 (GPIO_IN | 2)
35#define GPI_03 (GPIO_IN | 3)
36#define GPI_04 (GPIO_IN | 4)
37#define GPI_05 (GPIO_IN | 5)
38#define GPI_06 (GPIO_IN | 6)
39#define GPI_07 (GPIO_IN | 7)
40#define GPI_08 (GPIO_IN | 8)
41#define GPI_09 (GPIO_IN | 9)
42#define U1_RX (GPIO_IN | 15)
43#define U2_HTCS (GPIO_IN | 16)
44#define U2_RX (GPIO_IN | 17)
45#define U3_RX (GPIO_IN | 18)
46#define U4_RX (GPIO_IN | 19)
47#define U5_RX (GPIO_IN | 20)
48#define U6_IRRX (GPIO_IN | 21)
49#define U7_HCTS (GPIO_IN | 22)
50#define U7_RX (GPIO_IN | 23)
51/* MISC IN */
52#define SPI1_DATIN (GPIO_IN | 25)
53#define DISP_SYNC (GPIO_IN | 26)
54#define SPI2_DATIN (GPIO_IN | 27)
55#define GPI_11 (GPIO_IN | 28)
56
57#define GPIO_IN_MASK 0x1eff83ff
58
59/* OUTPUT GPIOs */
60/* GPO */
61#define GPO_00 (GPIO_OUT | 0)
62#define GPO_01 (GPIO_OUT | 1)
63#define GPO_02 (GPIO_OUT | 2)
64#define GPO_03 (GPIO_OUT | 3)
65#define GPO_04 (GPIO_OUT | 4)
66#define GPO_05 (GPIO_OUT | 5)
67#define GPO_06 (GPIO_OUT | 6)
68#define GPO_07 (GPIO_OUT | 7)
69#define GPO_08 (GPIO_OUT | 8)
70#define GPO_09 (GPIO_OUT | 9)
71#define GPO_10 (GPIO_OUT | 10)
72#define GPO_11 (GPIO_OUT | 11)
73#define GPO_12 (GPIO_OUT | 12)
74#define GPO_13 (GPIO_OUT | 13)
75#define GPO_14 (GPIO_OUT | 14)
76#define GPO_15 (GPIO_OUT | 15)
77#define GPO_16 (GPIO_OUT | 16)
78#define GPO_17 (GPIO_OUT | 17)
79#define GPO_18 (GPIO_OUT | 18)
80#define GPO_19 (GPIO_OUT | 19)
81#define GPO_20 (GPIO_OUT | 20)
82#define GPO_21 (GPIO_OUT | 21)
83#define GPO_22 (GPIO_OUT | 22)
84#define GPO_23 (GPIO_OUT | 23)
85
86#define GPIO_OUT_MASK 0xffffff
87
88/* BIDIRECTIONAL GPIOs */
89/* RAM pins */
90#define RAM_D19 (GPIO_RAM | 0)
91#define RAM_D20 (GPIO_RAM | 1)
92#define RAM_D21 (GPIO_RAM | 2)
93#define RAM_D22 (GPIO_RAM | 3)
94#define RAM_D23 (GPIO_RAM | 4)
95#define RAM_D24 (GPIO_RAM | 5)
96#define RAM_D25 (GPIO_RAM | 6)
97#define RAM_D26 (GPIO_RAM | 7)
98#define RAM_D27 (GPIO_RAM | 8)
99#define RAM_D28 (GPIO_RAM | 9)
100#define RAM_D29 (GPIO_RAM | 10)
101#define RAM_D30 (GPIO_RAM | 11)
102#define RAM_D31 (GPIO_RAM | 12)
103
104#define GPIO_RAM_MASK 0x1fff
105
106/* I/O pins */
107#define GPIO_00 (GPIO_BID | 25)
108#define GPIO_01 (GPIO_BID | 26)
109#define GPIO_02 (GPIO_BID | 27)
110#define GPIO_03 (GPIO_BID | 28)
111#define GPIO_04 (GPIO_BID | 29)
112#define GPIO_05 (GPIO_BID | 30)
113
114#define GPIO_BID_MASK 0x7e000000
115
116/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
117#define GPIO_SDRAM_SEL (GPIO_MUX | 3)
118
119#define GPIO_MUX_MASK 0x8
120
121/* Extraction/assembly macros */
122#define GPIO_BIT_MASK(K) ((K) & 0x1F)
123#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
124#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
125#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
126#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
127#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
128#define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
129
130extern int pnx4008_gpio_register_pin(unsigned short pin);
131extern int pnx4008_gpio_unregister_pin(unsigned short pin);
132extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
133extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
134extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
135extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
136extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
137extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
138
139#endif /* _PNX4008_GPIO_H_ */
diff --git a/include/asm-arm/arch-pnx4008/hardware.h b/include/asm-arm/arch-pnx4008/hardware.h
new file mode 100644
index 000000000000..a4410397a921
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/hardware.h
@@ -0,0 +1,32 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/hardware.h
3 *
4 * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_HARDWARE_H
21#define __ASM_ARCH_HARDWARE_H
22
23#include <asm/sizes.h>
24#include <asm/arch/platform.h>
25
26/* Start of virtual addresses for IO devices */
27#define IO_BASE 0xF0000000
28
29/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
30#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
31
32#endif
diff --git a/include/asm-arm/arch-pnx4008/io.h b/include/asm-arm/arch-pnx4008/io.h
new file mode 100644
index 000000000000..29ee43955c52
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/io.h
@@ -0,0 +1,21 @@
1
2/*
3 * include/asm-arm/arch-pnx4008/io.h
4 *
5 * Author: Dmitry Chigirev <chigirev@ru.mvista.com>
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifndef __ASM_ARM_ARCH_IO_H
14#define __ASM_ARM_ARCH_IO_H
15
16#define IO_SPACE_LIMIT 0xffffffff
17
18#define __io(a) ((void __iomem *)(a))
19#define __mem_pci(a) (a)
20
21#endif
diff --git a/include/asm-arm/arch-pnx4008/irq.h b/include/asm-arm/arch-pnx4008/irq.h
new file mode 100644
index 000000000000..fabff5dc337f
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/irq.h
@@ -0,0 +1,42 @@
1/*
2 * include/asm-arm/arch-pnx4008/irq.h
3 *
4 * PNX4008 IRQ controller driver - header file
5 * this one is used in entry-arnv.S as well so it cannot contain C code
6 *
7 * Copyright (c) 2005 Philips Semiconductors
8 * Copyright (c) 2005 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __PNX4008_IRQ_H__
16#define __PNX4008_IRQ_H__
17
18#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
19#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
20#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
21
22/* Manual: Chapter 20, page 195 */
23
24#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
25
26#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
27#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
28#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
29#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
30#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
31#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
32
33#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
34
35#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
36#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
37#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
38#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
39
40extern void __init pnx4008_init_irq(void);
41
42#endif /* __PNX4008_IRQ_H__ */
diff --git a/include/asm-arm/arch-pnx4008/irqs.h b/include/asm-arm/arch-pnx4008/irqs.h
new file mode 100644
index 000000000000..13ec7ed0f501
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/irqs.h
@@ -0,0 +1,215 @@
1/*
2 * include/asm-arm/arch-pnx4008/irqs.h
3 *
4 * PNX4008 IRQ controller driver - header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __PNX4008_IRQS_h__
14#define __PNX4008_IRQS_h__
15
16#define NR_IRQS 96
17
18/*Manual: table 259, page 199*/
19
20/*SUB2 Interrupt Routing (SIC2)*/
21
22#define SIC2_BASE_INT 64
23
24#define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */
25#define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */
26#define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */
27#define GPI_06_INT 92
28#define GPI_05_INT 91
29#define GPI_04_INT 90
30#define GPI_03_INT 89
31#define GPI_02_INT 88
32#define GPI_01_INT 87
33#define GPI_00_INT 86
34#define BT_CLKREQ_INT 85
35#define SPI1_DATIN_INT 84
36#define U5_RX_INT 83
37#define SDIO_INT_N 82
38#define CAM_HS_INT 81
39#define CAM_VS_INT 80
40#define GPI_07_INT 79
41#define DISP_SYNC_INT 78
42#define DSP_INT8 77
43#define U7_HCTS_INT 76
44#define GPI_10_INT 75
45#define GPI_09_INT 74
46#define GPI_08_INT 73
47#define DSP_INT7 72
48#define U2_HCTS_INT 71
49#define SPI2_DATIN_INT 70
50#define GPIO_05_INT 69
51#define GPIO_04_INT 68
52#define GPIO_03_INT 67
53#define GPIO_02_INT 66
54#define GPIO_01_INT 65
55#define GPIO_00_INT 64
56
57/*Manual: table 258, page 198*/
58
59/*SUB1 Interrupt Routing (SIC1)*/
60
61#define SIC1_BASE_INT 32
62
63#define USB_I2C_INT 63
64#define USB_DEV_HP_INT 62
65#define USB_DEV_LP_INT 61
66#define USB_DEV_DMA_INT 60
67#define USB_HOST_INT 59
68#define USB_OTG_ATX_INT_N 58
69#define USB_OTG_TIMER_INT 57
70#define SW_INT 56
71#define SPI1_INT 55
72#define KEY_IRQ 54
73#define DSP_M_INT 53
74#define RTC_INT 52
75#define I2C_1_INT 51
76#define I2C_2_INT 50
77#define PLL1_LOCK_INT 49
78#define PLL2_LOCK_INT 48
79#define PLL3_LOCK_INT 47
80#define PLL4_LOCK_INT 46
81#define PLL5_LOCK_INT 45
82#define SPI2_INT 44
83#define DSP_INT1 43
84#define DSP_INT2 42
85#define DSP_TDM_INT2 41
86#define TS_AUX_INT 40
87#define TS_IRQ 39
88#define TS_P_INT 38
89#define UOUT1_TO_PAD_INT 37
90#define GPI_11_INT 36
91#define DSP_INT4 35
92#define JTAG_COMM_RX_INT 34
93#define JTAG_COMM_TX_INT 33
94#define DSP_INT3 32
95
96/*Manual: table 257, page 197*/
97
98/*MAIN Interrupt Routing*/
99
100#define MAIN_BASE_INT 0
101
102#define SUB2_FIQ_N 31 /*active low */
103#define SUB1_FIQ_N 30 /*active low */
104#define JPEG_INT 29
105#define DMA_INT 28
106#define MSTIMER_INT 27
107#define IIR1_INT 26
108#define IIR2_INT 25
109#define IIR7_INT 24
110#define DSP_TDM_INT0 23
111#define DSP_TDM_INT1 22
112#define DSP_P_INT 21
113#define DSP_INT0 20
114#define DUM_INT 19
115#define UOUT0_TO_PAD_INT 18
116#define MP4_ENC_INT 17
117#define MP4_DEC_INT 16
118#define SD0_INT 15
119#define MBX_INT 14
120#define SD1_INT 13
121#define MS_INT_N 12
122#define FLASH_INT 11 /*NAND*/
123#define IIR6_INT 10
124#define IIR5_INT 9
125#define IIR4_INT 8
126#define IIR3_INT 7
127#define WATCH_INT 6
128#define HSTIMER_INT 5
129#define ARCH_TIMER_IRQ HSTIMER_INT
130#define CAM_INT 4
131#define PRNG_INT 3
132#define CRYPTO_INT 2
133#define SUB2_IRQ_N 1 /*active low */
134#define SUB1_IRQ_N 0 /*active low */
135
136#define PNX4008_IRQ_TYPES \
137{ /*IRQ #'s: */ \
138IRQT_LOW, IRQT_LOW, IRQT_LOW, IRQT_HIGH, /* 0, 1, 2, 3 */ \
139IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 4, 5, 6, 7 */ \
140IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 8, 9,10,11 */ \
141IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */ \
142IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */ \
143IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */ \
144IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */ \
145IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 28,29,30,31 */ \
146IRQT_HIGH, IRQT_LOW, IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */ \
147IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */ \
148IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */ \
149IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */ \
150IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 48,49,50,51 */ \
151IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */ \
152IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_HIGH, /* 56,57,58,59 */ \
153IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */ \
154IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */ \
155IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */ \
156IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */ \
157IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */ \
158IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */ \
159IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */ \
160IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */ \
161IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */ \
162}
163
164/* Start Enable Pin Interrupts - table 58 page 66 */
165
166#define SE_PIN_BASE_INT 32
167
168#define SE_U7_RX_INT 63
169#define SE_U7_HCTS_INT 62
170#define SE_BT_CLKREQ_INT 61
171#define SE_U6_IRRX_INT 60
172/*59 unused*/
173#define SE_U5_RX_INT 58
174#define SE_GPI_11_INT 57
175#define SE_U3_RX_INT 56
176#define SE_U2_HCTS_INT 55
177#define SE_U2_RX_INT 54
178#define SE_U1_RX_INT 53
179#define SE_DISP_SYNC_INT 52
180/*51 unused*/
181#define SE_SDIO_INT_N 50
182#define SE_MSDIO_START_INT 49
183#define SE_GPI_06_INT 48
184#define SE_GPI_05_INT 47
185#define SE_GPI_04_INT 46
186#define SE_GPI_03_INT 45
187#define SE_GPI_02_INT 44
188#define SE_GPI_01_INT 43
189#define SE_GPI_00_INT 42
190#define SE_SYSCLKEN_PIN_INT 41
191#define SE_SPI1_DATAIN_INT 40
192#define SE_GPI_07_INT 39
193#define SE_SPI2_DATAIN_INT 38
194#define SE_GPI_10_INT 37
195#define SE_GPI_09_INT 36
196#define SE_GPI_08_INT 35
197/*34-32 unused*/
198
199/* Start Enable Internal Interrupts - table 57 page 65 */
200
201#define SE_INT_BASE_INT 0
202
203#define SE_TS_IRQ 31
204#define SE_TS_P_INT 30
205#define SE_TS_AUX_INT 29
206/*27-28 unused*/
207#define SE_USB_AHB_NEED_CLK_INT 26
208#define SE_MSTIMER_INT 25
209#define SE_RTC_INT 24
210#define SE_USB_NEED_CLK_INT 23
211#define SE_USB_INT 22
212#define SE_USB_I2C_INT 21
213#define SE_USB_OTG_TIMER_INT 20
214
215#endif /* __PNX4008_IRQS_h__ */
diff --git a/include/asm-arm/arch-pnx4008/memory.h b/include/asm-arm/arch-pnx4008/memory.h
new file mode 100644
index 000000000000..0d8268a95261
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/memory.h
@@ -0,0 +1,24 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/memory.h
3 *
4 * Copyright (c) 2005 Philips Semiconductors
5 * Copyright (c) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16/*
17 * Physical DRAM offset.
18 */
19#define PHYS_OFFSET (0x80000000)
20
21#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
22#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET)
23
24#endif
diff --git a/include/asm-arm/arch-pnx4008/param.h b/include/asm-arm/arch-pnx4008/param.h
new file mode 100644
index 000000000000..95d5f547b416
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/param.h
@@ -0,0 +1,21 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/param.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#define HZ 100
diff --git a/include/asm-arm/arch-pnx4008/platform.h b/include/asm-arm/arch-pnx4008/platform.h
new file mode 100644
index 000000000000..485a3651b4d7
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/platform.h
@@ -0,0 +1,69 @@
1/*
2 * include/asm-arm/arch-pnx4008/platfrom.h
3 *
4 * PNX4008 Base addresses - header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code received from Philips:
9 * Copyright (C) 2003 Philips Semiconductors
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17
18#ifndef __ASM_ARCH_PLATFORM_H__
19#define __ASM_ARCH_PLATFORM_H__
20
21#define PNX4008_IRAM_BASE 0x08000000
22#define PNX4008_IRAM_SIZE 0x00010000
23#define PNX4008_YUV_SLAVE_BASE 0x10000000
24#define PNX4008_DUM_SLAVE_BASE 0x18000000
25#define PNX4008_NDF_FLASH_BASE 0x20020000
26#define PNX4008_SPI1_BASE 0x20088000
27#define PNX4008_SPI2_BASE 0x20090000
28#define PNX4008_SD_CONFIG_BASE 0x20098000
29#define PNX4008_FLASH_DATA 0x200B0000
30#define PNX4008_MLC_FLASH_BASE 0x200B8000
31#define PNX4008_JPEG_CONFIG_BASE 0x300A0000
32#define PNX4008_DMA_CONFIG_BASE 0x31000000
33#define PNX4008_USB_CONFIG_BASE 0x31020000
34#define PNX4008_SDRAM_CFG_BASE 0x31080000
35#define PNX4008_AHB2FAB_BASE 0x40000000
36#define PNX4008_PWRMAN_BASE 0x40004000
37#define PNX4008_INTCTRLMIC_BASE 0x40008000
38#define PNX4008_INTCTRLSIC1_BASE 0x4000C000
39#define PNX4008_INTCTRLSIC2_BASE 0x40010000
40#define PNX4008_HSUART1_BASE 0x40014000
41#define PNX4008_HSUART2_BASE 0x40018000
42#define PNX4008_HSUART7_BASE 0x4001C000
43#define PNX4008_RTC_BASE 0x40024000
44#define PNX4008_PIO_BASE 0x40028000
45#define PNX4008_MSTIMER_BASE 0x40034000
46#define PNX4008_HSTIMER_BASE 0x40038000
47#define PNX4008_WDOG_BASE 0x4003C000
48#define PNX4008_DEBUG_BASE 0x40040000
49#define PNX4008_TOUCH1_BASE 0x40048000
50#define PNX4008_KEYSCAN_BASE 0x40050000
51#define PNX4008_UARTCTRL_BASE 0x40054000
52#define PNX4008_PWM_BASE 0x4005C000
53#define PNX4008_UART3_BASE 0x40080000
54#define PNX4008_UART4_BASE 0x40088000
55#define PNX4008_UART5_BASE 0x40090000
56#define PNX4008_UART6_BASE 0x40098000
57#define PNX4008_I2C1_BASE 0x400A0000
58#define PNX4008_I2C2_BASE 0x400A8000
59#define PNX4008_MAGICGATE_BASE 0x400B0000
60#define PNX4008_DUMCONF_BASE 0x400B8000
61#define PNX4008_DUM_MAINCFG_BASE 0x400BC000
62#define PNX4008_DSP_BASE 0x400C0000
63#define PNX4008_PROFCOUNTER_BASE 0x400C8000
64#define PNX4008_CRYPTO_BASE 0x400D0000
65#define PNX4008_CAMIFCONF_BASE 0x400D8000
66#define PNX4008_YUV2RGB_BASE 0x400E0000
67#define PNX4008_AUDIOCONFIG_BASE 0x400E8000
68
69#endif
diff --git a/include/asm-arm/arch-pnx4008/pm.h b/include/asm-arm/arch-pnx4008/pm.h
new file mode 100644
index 000000000000..c660486670fb
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/pm.h
@@ -0,0 +1,62 @@
1/*
2 * include/asm-arm/arch-pnx4008/pm.h
3 *
4 * PNX4008 Power Management Routiness - header file
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __ASM_ARCH_PNX4008_PM_H
15#define __ASM_ARCH_PNX4008_PM_H
16
17#ifndef __ASSEMBLER__
18#include "irq.h"
19#include "irqs.h"
20#include "clock.h"
21
22extern void pnx4008_pm_idle(void);
23extern void pnx4008_pm_suspend(void);
24extern unsigned int pnx4008_cpu_suspend_sz;
25extern void pnx4008_cpu_suspend(void);
26extern unsigned int pnx4008_cpu_standby_sz;
27extern void pnx4008_cpu_standby(void);
28
29extern int pnx4008_startup_pll(struct clk *);
30extern int pnx4008_shutdown_pll(struct clk *);
31
32static inline void start_int_umask(u8 irq)
33{
34 __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
35 START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
36}
37
38static inline void start_int_mask(u8 irq)
39{
40 __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
41 ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
42}
43
44static inline void start_int_ack(u8 irq)
45{
46 __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
47}
48
49static inline void start_int_set_falling_edge(u8 irq)
50{
51 __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
52 ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
53}
54
55static inline void start_int_set_rising_edge(u8 irq)
56{
57 __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
58 START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
59}
60
61#endif /* ASSEMBLER */
62#endif /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/include/asm-arm/arch-pnx4008/system.h b/include/asm-arm/arch-pnx4008/system.h
new file mode 100644
index 000000000000..6e3da70ab107
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/system.h
@@ -0,0 +1,38 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/system.h
3 *
4 * Copyright (C) 2003 Philips Semiconductors
5 * Copyright (C) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24#include <asm/hardware.h>
25#include <asm/io.h>
26#include <asm/arch/platform.h>
27
28static void arch_idle(void)
29{
30 cpu_do_idle();
31}
32
33static inline void arch_reset(char mode)
34{
35 cpu_reset(0);
36}
37
38#endif
diff --git a/include/asm-arm/arch-pnx4008/timex.h b/include/asm-arm/arch-pnx4008/timex.h
new file mode 100644
index 000000000000..ee470a39089a
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/timex.h
@@ -0,0 +1,73 @@
1/*
2 * include/asm-arm/arch-pnx4008/timex.h
3 *
4 * PNX4008 timers header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __PNX4008_TIMEX_H
15#define __PNX4008_TIMEX_H
16
17#include <asm/hardware.h>
18#include <asm/io.h>
19
20#define CLOCK_TICK_RATE 1000000
21
22#define TICKS2USECS(x) (x)
23
24/* MilliSecond Timer - Chapter 21 Page 202 */
25
26#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
27#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
28#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
29#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
30#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
31#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
32
33/* High Speed Timer - Chpater 22, Page 205 */
34
35#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
36#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
37#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
38#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
39#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
40#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
41#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
42#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
43#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
44#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
45#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
46#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
47
48/* IMPORTANT: both timers are UPCOUNTING */
49
50/* xSTIM_MCTRL bit definitions */
51#define MR0_INT 1
52#define RESET_COUNT0 (1<<1)
53#define STOP_COUNT0 (1<<2)
54#define MR1_INT (1<<3)
55#define RESET_COUNT1 (1<<4)
56#define STOP_COUNT1 (1<<5)
57#define MR2_INT (1<<6)
58#define RESET_COUNT2 (1<<7)
59#define STOP_COUNT2 (1<<8)
60
61/* xSTIM_CTRL bit definitions */
62#define COUNT_ENAB 1
63#define RESET_COUNT (1<<1)
64#define DEBUG_EN (1<<2)
65
66/* xSTIM_INT bit definitions */
67#define MATCH0_INT 1
68#define MATCH1_INT (1<<1)
69#define MATCH2_INT (1<<2)
70#define RTC_TICK0 (1<<4)
71#define RTC_TICK1 (1<<5)
72
73#endif
diff --git a/include/asm-arm/arch-pnx4008/uncompress.h b/include/asm-arm/arch-pnx4008/uncompress.h
new file mode 100644
index 000000000000..8fa4d24b72b4
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/uncompress.h
@@ -0,0 +1,46 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/uncompress.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2006 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#define UART5_BASE 0x40090000
23
24#define UART5_DR (*(volatile unsigned char *) (UART5_BASE))
25#define UART5_FR (*(volatile unsigned char *) (UART5_BASE + 18))
26
27static __inline__ void putc(char c)
28{
29 while (UART5_FR & (1 << 5))
30 barrier();
31
32 UART5_DR = c;
33}
34
35/*
36 * This does not append a newline
37 */
38static inline void flush(void)
39{
40}
41
42/*
43 * nothing to do
44 */
45#define arch_decomp_setup()
46#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pnx4008/vmalloc.h b/include/asm-arm/arch-pnx4008/vmalloc.h
new file mode 100644
index 000000000000..140d925f6f37
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/vmalloc.h
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-pnx4008/vmalloc.h
3 *
4 * Author: Vitaly Wool <source@mvista.com>
5 *
6 * 2006 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12/*
13 * Just any arbitrary offset to the start of the vmalloc VM area: the
14 * current 8MB value just means that there will be a 8MB "hole" after the
15 * physical memory until the kernel virtual memory starts. That means that
16 * any out-of-bounds memory accesses will hopefully be caught.
17 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
18 * area for the same reason. ;)
19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-pxa/ohci.h b/include/asm-arm/arch-pxa/ohci.h
index 7da89569061e..e848a47128cd 100644
--- a/include/asm-arm/arch-pxa/ohci.h
+++ b/include/asm-arm/arch-pxa/ohci.h
@@ -11,6 +11,8 @@ struct pxaohci_platform_data {
11#define PMM_NPS_MODE 1 11#define PMM_NPS_MODE 1
12#define PMM_GLOBAL_MODE 2 12#define PMM_GLOBAL_MODE 2
13#define PMM_PERPORT_MODE 3 13#define PMM_PERPORT_MODE 3
14
15 int power_budget;
14}; 16};
15 17
16extern void pxa_set_ohci_info(struct pxaohci_platform_data *info); 18extern void pxa_set_ohci_info(struct pxaohci_platform_data *info);
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index c380d264a847..5e4c8c37bc66 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -126,9 +126,18 @@
126#define S3C24XX_SZ_IIS SZ_1M 126#define S3C24XX_SZ_IIS SZ_1M
127 127
128/* GPIO ports */ 128/* GPIO ports */
129#define S3C24XX_VA_GPIO S3C2410_ADDR(0x00E00000) 129
130/* the calculation for the VA of this must ensure that
131 * it is the same distance apart from the UART in the
132 * phsyical address space, as the initial mapping for the IO
133 * is done as a 1:1 maping. This puts it (currently) at
134 * 0xF6800000, which is not in the way of any current mapping
135 * by the base system.
136*/
137
130#define S3C2400_PA_GPIO (0x15600000) 138#define S3C2400_PA_GPIO (0x15600000)
131#define S3C2410_PA_GPIO (0x56000000) 139#define S3C2410_PA_GPIO (0x56000000)
140#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
132#define S3C24XX_SZ_GPIO SZ_1M 141#define S3C24XX_SZ_GPIO SZ_1M
133 142
134/* RTC */ 143/* RTC */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 34360706e016..6c92faffe985 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -114,7 +114,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
114 114
115#endif /* __ASSEMBLY__ */ 115#endif /* __ASSEMBLY__ */
116 116
117#ifdef CONFIG_CPU_S3C2440 117#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
118 118
119/* extra registers */ 119/* extra registers */
120#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) 120#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
@@ -136,7 +136,9 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
136#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) 136#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
137#define S3C2440_CAMDIVN_DVSEN (1<<12) 137#define S3C2440_CAMDIVN_DVSEN (1<<12)
138 138
139#endif /* CONFIG_CPU_S3C2440 */ 139#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
140
141#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
140 142
141 143
142#endif /* __ASM_ARM_REGS_CLOCK */ 144#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index d2574084697f..5f10334f06bf 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -450,12 +450,14 @@
450#define S3C2410_GPD0_OUTP (0x01 << 0) 450#define S3C2410_GPD0_OUTP (0x01 << 0)
451#define S3C2410_GPD0_VD8 (0x02 << 0) 451#define S3C2410_GPD0_VD8 (0x02 << 0)
452#define S3C2400_GPD0_VFRAME (0x02 << 0) 452#define S3C2400_GPD0_VFRAME (0x02 << 0)
453#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
453 454
454#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) 455#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
455#define S3C2410_GPD1_INP (0x00 << 2) 456#define S3C2410_GPD1_INP (0x00 << 2)
456#define S3C2410_GPD1_OUTP (0x01 << 2) 457#define S3C2410_GPD1_OUTP (0x01 << 2)
457#define S3C2410_GPD1_VD9 (0x02 << 2) 458#define S3C2410_GPD1_VD9 (0x02 << 2)
458#define S3C2400_GPD1_VM (0x02 << 2) 459#define S3C2400_GPD1_VM (0x02 << 2)
460#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
459 461
460#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) 462#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
461#define S3C2410_GPD2_INP (0x00 << 4) 463#define S3C2410_GPD2_INP (0x00 << 4)
@@ -858,6 +860,7 @@
858#define S3C2410_GPG12_OUTP (0x01 << 24) 860#define S3C2410_GPG12_OUTP (0x01 << 24)
859#define S3C2410_GPG12_EINT20 (0x02 << 24) 861#define S3C2410_GPG12_EINT20 (0x02 << 24)
860#define S3C2410_GPG12_XMON (0x03 << 24) 862#define S3C2410_GPG12_XMON (0x03 << 24)
863#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
861 864
862#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) 865#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
863#define S3C2410_GPG13_INP (0x00 << 26) 866#define S3C2410_GPG13_INP (0x00 << 26)
@@ -943,6 +946,7 @@
943#define S3C2410_GPH9_INP (0x00 << 18) 946#define S3C2410_GPH9_INP (0x00 << 18)
944#define S3C2410_GPH9_OUTP (0x01 << 18) 947#define S3C2410_GPH9_OUTP (0x01 << 18)
945#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) 948#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
949#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
946 950
947#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) 951#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
948#define S3C2410_GPH10_INP (0x00 << 20) 952#define S3C2410_GPH10_INP (0x00 << 20)
@@ -1051,6 +1055,7 @@
1051#define S3C2410_GSTATUS1_IDMASK (0xffff0000) 1055#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
1052#define S3C2410_GSTATUS1_2410 (0x32410000) 1056#define S3C2410_GSTATUS1_2410 (0x32410000)
1053#define S3C2410_GSTATUS1_2440 (0x32440000) 1057#define S3C2410_GSTATUS1_2440 (0x32440000)
1058#define S3C2410_GSTATUS1_2442 (0x32440aaa)
1054 1059
1055#define S3C2410_GSTATUS2_WTRESET (1<<2) 1060#define S3C2410_GSTATUS2_WTRESET (1<<2)
1056#define S3C2410_GSTATUS2_OFFRESET (1<<1) 1061#define S3C2410_GSTATUS2_OFFRESET (1<<1)
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index 0ecb8103fa70..8e152a05e533 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -81,7 +81,8 @@ static void putc(int ch)
81 while (1) { 81 while (1) {
82 level = uart_rd(S3C2410_UFSTAT); 82 level = uart_rd(S3C2410_UFSTAT);
83 83
84 if (cpuid == S3C2410_GSTATUS1_2440) { 84 if (cpuid == S3C2410_GSTATUS1_2440 ||
85 cpuid == S3C2410_GSTATUS1_2442) {
85 level &= S3C2440_UFSTAT_TXMASK; 86 level &= S3C2440_UFSTAT_TXMASK;
86 level >>= S3C2440_UFSTAT_TXSHIFT; 87 level >>= S3C2440_UFSTAT_TXSHIFT;
87 } else { 88 } else {
@@ -129,7 +130,7 @@ static void arch_decomp_wdog_start(void)
129{ 130{
130 __raw_writel(WDOG_COUNT, S3C2410_WTDAT); 131 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
131 __raw_writel(WDOG_COUNT, S3C2410_WTCNT); 132 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
132 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); 133 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
133} 134}
134 135
135#else 136#else
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 96c6db7dd0e1..9f28073559e8 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -50,6 +50,7 @@ struct sys_timer {
50#define DYN_TICK_ENABLED (1 << 1) 50#define DYN_TICK_ENABLED (1 << 1)
51 51
52struct dyn_tick_timer { 52struct dyn_tick_timer {
53 spinlock_t lock;
53 unsigned int state; /* Current state */ 54 unsigned int state; /* Current state */
54 int (*enable)(void); /* Enables dynamic tick */ 55 int (*enable)(void); /* Enables dynamic tick */
55 int (*disable)(void); /* Disables dynamic tick */ 56 int (*disable)(void); /* Disables dynamic tick */
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index f5eafd7ed8fa..9c744ae6c6e3 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -126,6 +126,12 @@ static inline int cpu_is_xsc3(void)
126} 126}
127#endif 127#endif
128 128
129#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
130#define cpu_is_xscale() 0
131#else
132#define cpu_is_xscale() 1
133#endif
134
129#define set_cr(x) \ 135#define set_cr(x) \
130 __asm__ __volatile__( \ 136 __asm__ __volatile__( \
131 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ 137 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 04:50:45 -0500