152 files changed, 3309 insertions, 310 deletions
diff --git a/include/asm-arm/apm.h b/include/asm-arm/apm.h
index 3a50eb759c28..d09113b37e4a 100644
--- a/include/asm-arm/apm.h
+++ b/include/asm-arm/apm.h
@@ -13,7 +13,6 @@
 #ifndef ARM_ASM_SA1100_APM_H
 #define ARM_ASM_SA1100_APM_H
-#include <linux/config.h>
 #include <linux/apm_bios.h>
 /*
diff --git a/include/asm-arm/arch-aaec2000/io.h b/include/asm-arm/arch-aaec2000/io.h
index 8d67907fd4f0..d710204ac747 100644
--- a/include/asm-arm/arch-aaec2000/io.h
+++ b/include/asm-arm/arch-aaec2000/io.h
@@ -16,6 +16,5 @@
 */
 #define __io(a)                 ((void __iomem *)(a))
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 #endif
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index d8209f8911d6..24b51cccde8f 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -11,7 +11,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-#include <linux/config.h>
 #define PHYS_OFFSET     UL(0xf0000000)
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h b/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
new file mode 100644
index 000000000000..bff5ea45f604
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
@@ -0,0 +1,81 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Serial Peripheral Interface (SPI) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_SPI_H
+#define AT91RM9200_SPI_H
+#define AT91_SPI_CR                     0x00            /* Control Register */
+#define         AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
+#define         AT91_SPI_SPIDIS         (1 <<  1)               /* SPI Disable */
+#define         AT91_SPI_SWRST          (1 <<  7)               /* SPI Software Reset */
+#define         AT91_SPI_LASTXFER       (1 << 24)               /* Last Transfer [SAM9261 only] */
+#define AT91_SPI_MR                     0x04            /* Mode Register */
+#define         AT91_SPI_MSTR           (1    <<  0)            /* Master/Slave Mode */
+#define         AT91_SPI_PS             (1    <<  1)            /* Peripheral Select */
+#define                 AT91_SPI_PS_FIXED       (0 << 1)
+#define                 AT91_SPI_PS_VARIABLE    (1 << 1)
+#define         AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
+#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection */
+#define         AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
+#define         AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
+#define         AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
+#define         AT91_SPI_DLYBCS         (0xff << 24)            /* Delay Between Chip Selects */
+#define AT91_SPI_RDR            0x08                    /* Receive Data Register */
+#define         AT91_SPI_RD             (0xffff <<  0)          /* Receive Data */
+#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
+#define AT91_SPI_TDR            0x0c                    /* Transmit Data Register */
+#define         AT91_SPI_TD             (0xffff <<  0)          /* Transmit Data */
+#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
+#define         AT91_SPI_LASTXFER       (1      << 24)          /* Last Transfer [SAM9261 only] */
+#define AT91_SPI_SR             0x10                    /* Status Register */
+#define         AT91_SPI_RDRF           (1 <<  0)               /* Receive Data Register Full */
+#define         AT91_SPI_TDRE           (1 <<  1)               /* Transmit Data Register Full */
+#define         AT91_SPI_MODF           (1 <<  2)               /* Mode Fault Error */
+#define         AT91_SPI_OVRES          (1 <<  3)               /* Overrun Error Status */
+#define         AT91_SPI_ENDRX          (1 <<  4)               /* End of RX buffer */
+#define         AT91_SPI_ENDTX          (1 <<  5)               /* End of TX buffer */
+#define         AT91_SPI_RXBUFF         (1 <<  6)               /* RX Buffer Full */
+#define         AT91_SPI_TXBUFE         (1 <<  7)               /* TX Buffer Empty */
+#define         AT91_SPI_NSSR           (1 <<  8)               /* NSS Rising [SAM9261 only] */
+#define         AT91_SPI_TXEMPTY        (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
+#define         AT91_SPI_SPIENS         (1 << 16)               /* SPI Enable Status */
+#define AT91_SPI_IER            0x14                    /* Interrupt Enable Register */
+#define AT91_SPI_IDR            0x18                    /* Interrupt Disable Register */
+#define AT91_SPI_IMR            0x1c                    /* Interrupt Mask Register */
+#define AT91_SPI_CSR(n)         (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
+#define         AT91_SPI_CPOL           (1    <<  0)            /* Clock Polarity */
+#define         AT91_SPI_NCPHA          (1    <<  1)            /* Clock Phase */
+#define         AT91_SPI_CSAAT          (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
+#define         AT91_SPI_BITS           (0xf  <<  4)            /* Bits Per Transfer */
+#define                 AT91_SPI_BITS_8         (0 << 4)
+#define                 AT91_SPI_BITS_9         (1 << 4)
+#define                 AT91_SPI_BITS_10        (2 << 4)
+#define                 AT91_SPI_BITS_11        (3 << 4)
+#define                 AT91_SPI_BITS_12        (4 << 4)
+#define                 AT91_SPI_BITS_13        (5 << 4)
+#define                 AT91_SPI_BITS_14        (6 << 4)
+#define                 AT91_SPI_BITS_15        (7 << 4)
+#define                 AT91_SPI_BITS_16        (8 << 4)
+#define         AT91_SPI_SCBR           (0xff <<  8)            /* Serial Clock Baud Rate */
+#define         AT91_SPI_DLYBS          (0xff << 16)            /* Delay before SPCK */
+#define         AT91_SPI_DLYBCT         (0xff << 24)            /* Delay between Consecutive Transfers */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
new file mode 100644
index 000000000000..ac880227147f
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Serial Synchronous Controller (SSC) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_SSC_H
+#define AT91RM9200_SSC_H
+#define AT91_SSC_CR             0x00    /* Control Register */
+#define         AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
+#define         AT91_SSC_RXDIS          (1 <<  1)       /* Receive Disable */
+#define         AT91_SSC_TXEN           (1 <<  8)       /* Transmit Enable */
+#define         AT91_SSC_TXDIS          (1 <<  9)       /* Transmit Disable */
+#define         AT91_SSC_SWRST          (1 << 15)       /* Software Reset */
+#define AT91_SSC_CMR            0x04    /* Clock Mode Register */
+#define         AT91_SSC_CMR_DIV        (0xfff << 0)    /* Clock Divider */
+#define AT91_SSC_RCMR           0x10    /* Receive Clock Mode Register */
+#define         AT91_SSC_CKS            (3    <<  0)    /* Clock Selection */
+#define                 AT91_SSC_CKS_DIV                (0 << 0)
+#define                 AT91_SSC_CKS_CLOCK              (1 << 0)
+#define                 AT91_SSC_CKS_PIN                (2 << 0)
+#define         AT91_SSC_CKO            (7    <<  2)    /* Clock Output Mode Selection */
+#define                 AT91_SSC_CKO_NONE               (0 << 2)
+#define                 AT91_SSC_CKO_CONTINUOUS         (1 << 2)
+#define         AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
+#define                 AT91_SSC_CKI_FALLING            (0 << 5)
+#define                 AT91_SSC_CK_RISING              (1 << 5)
+#define         AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
+#define                 AT91_SSC_START_CONTINUOUS       (0 << 8)
+#define                 AT91_SSC_START_TX_RX            (1 << 8)
+#define                 AT91_SSC_START_LOW_RF           (2 << 8)
+#define                 AT91_SSC_START_HIGH_RF          (3 << 8)
+#define                 AT91_SSC_START_FALLING_RF       (4 << 8)
+#define                 AT91_SSC_START_RISING_RF        (5 << 8)
+#define                 AT91_SSC_START_LEVEL_RF         (6 << 8)
+#define                 AT91_SSC_START_EDGE_RF          (7 << 8)
+#define         AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
+#define         AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
+#define AT91_SSC_RFMR           0x14    /* Receive Frame Mode Register */
+#define         AT91_SSC_DATALEN        (0x1f <<  0)    /* Data Length */
+#define         AT91_SSC_LOOP           (1    <<  5)    /* Loop Mode */
+#define         AT91_SSC_MSBF           (1    <<  7)    /* Most Significant Bit First */
+#define         AT91_SSC_DATNB          (0xf  <<  8)    /* Data Number per Frame */
+#define         AT91_SSC_FSLEN          (0xf  << 16)    /* Frame Sync Length */
+#define         AT91_SSC_FSOS           (7    << 20)    /* Frame Sync Output Selection */
+#define                 AT91_SSC_FSOS_NONE              (0 << 20)
+#define                 AT91_SSC_FSOS_NEGATIVE          (1 << 20)
+#define                 AT91_SSC_FSOS_POSITIVE          (2 << 20)
+#define                 AT91_SSC_FSOS_LOW               (3 << 20)
+#define                 AT91_SSC_FSOS_HIGH              (4 << 20)
+#define                 AT91_SSC_FSOS_TOGGLE            (5 << 20)
+#define         AT91_SSC_FSEDGE         (1    << 24)    /* Frame Sync Edge Detection */
+#define                 AT91_SSC_FSEDGE_POSITIVE        (0 << 24)
+#define                 AT91_SSC_FSEDGE_NEGATIVE        (1 << 24)
+#define AT91_SSC_TCMR           0x18    /* Transmit Clock Mode Register */
+#define AT91_SSC_TFMR           0x1c    /* Transmit Fram Mode Register */
+#define         AT91_SSC_DATDEF         (1 <<  5)       /* Data Default Value */
+#define         AT91_SSC_FSDEN          (1 << 23)       /* Frame Sync Data Enable */
+#define AT91_SSC_RHR            0x20    /* Receive Holding Register */
+#define AT91_SSC_THR            0x24    /* Transmit Holding Register */
+#define AT91_SSC_RSHR           0x30    /* Receive Sync Holding Register */
+#define AT91_SSC_TSHR           0x34    /* Transmit Sync Holding Register */
+#define AT91_SSC_SR             0x40    /* Status Register */
+#define         AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
+#define         AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
+#define         AT91_SSC_ENDTX          (1 <<  2)       /* End of Transmission */
+#define         AT91_SSC_TXBUFE         (1 <<  3)       /* Transmit Buffer Empty */
+#define         AT91_SSC_RXRDY          (1 <<  4)       /* Receive Ready */
+#define         AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
+#define         AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
+#define         AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
+#define         AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
+#define         AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
+#define         AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
+#define         AT91_SSC_RXENA          (1 << 17)       /* Receive Enable */
+#define AT91_SSC_IER            0x44    /* Interrupt Enable Register */
+#define AT91_SSC_IDR            0x48    /* Interrupt Disable Register */
+#define AT91_SSC_IMR            0x4c    /* Interrupt Mask Register */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
index 2910d359f919..0f4c12d5f0cd 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -68,8 +68,17 @@
 #define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
 #define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
 #define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
 #define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
 #define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
+#define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
+#define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
+#define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
+#define         AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
+#define         AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
+#define         AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
+#define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
+#define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
 /*
@@ -241,7 +250,7 @@
 #define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
 #define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
 #define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
-#define         At91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
+#define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
 #define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
 #define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
new file mode 100644
index 000000000000..f4da752bb0c8
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
@@ -0,0 +1,146 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Timer/Counter Unit (TC) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_TC_H
+#define AT91RM9200_TC_H
+#define AT91_TC_BCR             0xc0            /* TC Block Control Register */
+#define         AT91_TC_SYNC            (1 << 0)        /* Synchro Command */
+#define AT91_TC_BMR             0xc4            /* TC Block Mode Register */
+#define         AT91_TC_TC0XC0S         (3 << 0)        /* External Clock Signal 0 Selection */
+#define                 AT91_TC_TC0XC0S_TCLK0           (0 << 0)
+#define                 AT91_TC_TC0XC0S_NONE            (1 << 0)
+#define                 AT91_TC_TC0XC0S_TIOA1           (2 << 0)
+#define                 AT91_TC_TC0XC0S_TIOA2           (3 << 0)
+#define         AT91_TC_TC1XC1S         (3 << 2)        /* External Clock Signal 1 Selection */
+#define                 AT91_TC_TC1XC1S_TCLK1           (0 << 2)
+#define                 AT91_TC_TC1XC1S_NONE            (1 << 2)
+#define                 AT91_TC_TC1XC1S_TIOA0           (2 << 2)
+#define                 AT91_TC_TC1XC1S_TIOA2           (3 << 2)
+#define         AT91_TC_TC2XC2S         (3 << 4)        /* External Clock Signal 2 Selection */
+#define                 AT91_TC_TC2XC2S_TCLK2           (0 << 4)
+#define                 AT91_TC_TC2XC2S_NONE            (1 << 4)
+#define                 AT91_TC_TC2XC2S_TIOA0           (2 << 4)
+#define                 AT91_TC_TC2XC2S_TIOA1           (3 << 4)
+#define AT91_TC_CCR             0x00            /* Channel Control Register */
+#define         AT91_TC_CLKEN           (1 << 0)        /* Counter Clock Enable Command */
+#define         AT91_TC_CLKDIS          (1 << 1)        /* Counter CLock Disable Command */
+#define         AT91_TC_SWTRG           (1 << 2)        /* Software Trigger Command */
+#define AT91_TC_CMR             0x04            /* Channel Mode Register */
+#define         AT91_TC_TCCLKS          (7 << 0)        /* Capture/Waveform Mode: Clock Selection */
+#define                 AT91_TC_TIMER_CLOCK1            (0 << 0)
+#define                 AT91_TC_TIMER_CLOCK2            (1 << 0)
+#define                 AT91_TC_TIMER_CLOCK3            (2 << 0)
+#define                 AT91_TC_TIMER_CLOCK4            (3 << 0)
+#define                 AT91_TC_TIMER_CLOCK5            (4 << 0)
+#define                 AT91_TC_XC0                     (5 << 0)
+#define                 AT91_TC_XC1                     (6 << 0)
+#define                 AT91_TC_XC2                     (7 << 0)
+#define         AT91_TC_CLKI            (1 << 3)        /* Capture/Waveform Mode: Clock Invert */
+#define         AT91_TC_BURST           (3 << 4)        /* Capture/Waveform Mode: Burst Signal Selection */
+#define         AT91_TC_LDBSTOP         (1 << 6)        /* Capture Mode: Counter Clock Stopped with TB Loading */
+#define         AT91_TC_LDBDIS          (1 << 7)        /* Capture Mode: Counter Clock Disable with RB Loading */
+#define         AT91_TC_ETRGEDG         (3 << 8)        /* Capture Mode: External Trigger Edge Selection */
+#define         AT91_TC_ABETRG          (1 << 10)       /* Capture Mode: TIOA or TIOB External Trigger Selection */
+#define         AT91_TC_CPCTRG          (1 << 14)       /* Capture Mode: RC Compare Trigger Enable */
+#define         AT91_TC_WAVE            (1 << 15)       /* Capture/Waveform mode */
+#define         AT91_TC_LDRA            (3 << 16)       /* Capture Mode: RA Loading Selection */
+#define         AT91_TC_LDRB            (3 << 18)       /* Capture Mode: RB Loading Selection */
+#define         AT91_TC_CPCSTOP         (1 <<  6)       /* Waveform Mode: Counter Clock Stopped with RC Compare */
+#define         AT91_TC_CPCDIS          (1 <<  7)       /* Waveform Mode: Counter Clock Disable with RC Compare */
+#define         AT91_TC_EEVTEDG         (3 <<  8)       /* Waveform Mode: External Event Edge Selection */
+#define                 AT91_TC_EEVTEDG_NONE            (0 << 8)
+#define                 AT91_TC_EEVTEDG_RISING          (1 << 8)
+#define                 AT91_TC_EEVTEDG_FALLING         (2 << 8)
+#define                 AT91_TC_EEVTEDG_BOTH            (3 << 8)
+#define         AT91_TC_EEVT            (3 << 10)       /* Waveform Mode: External Event Selection */
+#define                 AT91_TC_EEVT_TIOB               (0 << 10)
+#define                 AT91_TC_EEVT_XC0                (1 << 10)
+#define                 AT91_TC_EEVT_XC1                (2 << 10)
+#define                 AT91_TC_EEVT_XC2                (3 << 10)
+#define         AT91_TC_ENETRG          (1 << 12)       /* Waveform Mode: External Event Trigger Enable */
+#define         AT91_TC_WAVESEL         (3 << 13)       /* Waveform Mode: Waveform Selection */
+#define                 AT91_TC_WAVESEL_UP              (0 << 13)
+#define                 AT91_TC_WAVESEL_UP_AUTO         (2 << 13)
+#define                 AT91_TC_WAVESEL_UPDOWN          (1 << 13)
+#define                 AT91_TC_WAVESEL_UPDOWN_AUTO     (3 << 13)
+#define         AT91_TC_ACPA            (3 << 16)       /* Waveform Mode: RA Compare Effect on TIOA */
+#define                 AT91_TC_ACPA_NONE               (0 << 16)
+#define                 AT91_TC_ACPA_SET                (1 << 16)
+#define                 AT91_TC_ACPA_CLEAR              (2 << 16)
+#define                 AT91_TC_ACPA_TOGGLE             (3 << 16)
+#define         AT91_TC_ACPC            (3 << 18)       /* Waveform Mode: RC Compre Effect on TIOA */
+#define                 AT91_TC_ACPC_NONE               (0 << 18)
+#define                 AT91_TC_ACPC_SET                (1 << 18)
+#define                 AT91_TC_ACPC_CLEAR              (2 << 18)
+#define                 AT91_TC_ACPC_TOGGLE             (3 << 18)
+#define         AT91_TC_AEEVT           (3 << 20)       /* Waveform Mode: External Event Effect on TIOA */
+#define                 AT91_TC_AEEVT_NONE              (0 << 20)
+#define                 AT91_TC_AEEVT_SET               (1 << 20)
+#define                 AT91_TC_AEEVT_CLEAR             (2 << 20)
+#define                 AT91_TC_AEEVT_TOGGLE            (3 << 20)
+#define         AT91_TC_ASWTRG          (3 << 22)       /* Waveform Mode: Software Trigger Effect on TIOA */
+#define                 AT91_TC_ASWTRG_NONE             (0 << 22)
+#define                 AT91_TC_ASWTRG_SET              (1 << 22)
+#define                 AT91_TC_ASWTRG_CLEAR            (2 << 22)
+#define                 AT91_TC_ASWTRG_TOGGLE           (3 << 22)
+#define         AT91_TC_BCPB            (3 << 24)       /* Waveform Mode: RB Compare Effect on TIOB */
+#define                 AT91_TC_BCPB_NONE               (0 << 24)
+#define                 AT91_TC_BCPB_SET                (1 << 24)
+#define                 AT91_TC_BCPB_CLEAR              (2 << 24)
+#define                 AT91_TC_BCPB_TOGGLE             (3 << 24)
+#define         AT91_TC_BCPC            (3 << 26)       /* Waveform Mode: RC Compare Effect on TIOB */
+#define                 AT91_TC_BCPC_NONE               (0 << 26)
+#define                 AT91_TC_BCPC_SET                (1 << 26)
+#define                 AT91_TC_BCPC_CLEAR              (2 << 26)
+#define                 AT91_TC_BCPC_TOGGLE             (3 << 26)
+#define         AT91_TC_BEEVT           (3 << 28)       /* Waveform Mode: External Event Effect on TIOB */
+#define                 AT91_TC_BEEVT_NONE              (0 << 28)
+#define                 AT91_TC_BEEVT_SET               (1 << 28)
+#define                 AT91_TC_BEEVT_CLEAR             (2 << 28)
+#define                 AT91_TC_BEEVT_TOGGLE            (3 << 28)
+#define         AT91_TC_BSWTRG          (3 << 30)       /* Waveform Mode: Software Trigger Effect on TIOB */
+#define                 AT91_TC_BSWTRG_NONE             (0 << 30)
+#define                 AT91_TC_BSWTRG_SET              (1 << 30)
+#define                 AT91_TC_BSWTRG_CLEAR            (2 << 30)
+#define                 AT91_TC_BSWTRG_TOGGLE           (3 << 30)
+#define AT91_TC_CV              0x10            /* Counter Value */
+#define AT91_TC_RA              0x14            /* Register A */
+#define AT91_TC_RB              0x18            /* Register B */
+#define AT91_TC_RC              0x1c            /* Register C */
+#define AT91_TC_SR              0x20            /* Status Register */
+#define         AT91_TC_COVFS           (1 <<  0)       /* Counter Overflow Status */
+#define         AT91_TC_LOVRS           (1 <<  1)       /* Load Overrun Status */
+#define         AT91_TC_CPAS            (1 <<  2)       /* RA Compare Status */
+#define         AT91_TC_CPBS            (1 <<  3)       /* RB Compare Status */
+#define         AT91_TC_CPCS            (1 <<  4)       /* RC Compare Status */
+#define         AT91_TC_LDRAS           (1 <<  5)       /* RA Loading Status */
+#define         AT91_TC_LDRBS           (1 <<  6)       /* RB Loading Status */
+#define         AT91_TC_ETRGS           (1 <<  7)       /* External Trigger Status */
+#define         AT91_TC_CLKSTA          (1 << 16)       /* Clock Enabling Status */
+#define         AT91_TC_MTIOA           (1 << 17)       /* TIOA Mirror */
+#define         AT91_TC_MTIOB           (1 << 18)       /* TIOB Mirror */
+#define AT91_TC_IER             0x24            /* Interrupt Enable Register */
+#define AT91_TC_IDR             0x28            /* Interrupt Disable Register */
+#define AT91_TC_IMR             0x2c            /* Interrupt Mask Register */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
new file mode 100644
index 000000000000..951e3f61cef4
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
@@ -0,0 +1,77 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * USB Device Port (UDP) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_UDP_H
+#define AT91RM9200_UDP_H
+#define AT91_UDP_FRM_NUM        0x00            /* Frame Number Register */
+#define         AT91_UDP_NUM            (0x7ff <<  0)           /* Frame Number */
+#define         AT91_UDP_FRM_ERR        (1     << 16)           /* Frame Error */
+#define         AT91_UDP_FRM_OK         (1     << 17)           /* Frame OK */
+#define AT91_UDP_GLB_STAT       0x04            /* Global State Register */
+#define         AT91_UDP_FADDEN         (1 <<  0)               /* Function Address Enable */
+#define         AT91_UDP_CONFG          (1 <<  1)               /* Configured */
+#define         AT91_UDP_ESR            (1 <<  2)               /* Enable Send Resume */
+#define         AT91_UDP_RSMINPR        (1 <<  3)               /* Resume has been sent */
+#define         AT91_UDP_RMWUPE         (1 <<  4)               /* Remote Wake Up Enable */
+#define AT91_UDP_FADDR          0x08            /* Function Address Register */
+#define         AT91_UDP_FADD           (0x7f << 0)             /* Function Address Value */
+#define         AT91_UDP_FEN            (1    << 8)             /* Function Enable */
+#define AT91_UDP_IER            0x10            /* Interrupt Enable Register */
+#define AT91_UDP_IDR            0x14            /* Interrupt Disable Register */
+#define AT91_UDP_IMR            0x18            /* Interrupt Mask Register */
+#define AT91_UDP_ISR            0x1c            /* Interrupt Status Register */
+#define         AT91_UDP_EP(n)          (1 << (n))              /* Endpoint Interrupt Status */
+#define         AT91_UDP_RXSUSP         (1 <<  8)               /* USB Suspend Interrupt Status */
+#define         AT91_UDP_RXRSM          (1 <<  9)               /* USB Resume Interrupt Status */
+#define         AT91_UDP_EXTRSM         (1 << 10)               /* External Resume Interrupt Status */
+#define         AT91_UDP_SOFINT         (1 << 11)               /* Start of Frame Interrupt Status */
+#define         AT91_UDP_ENDBUSRES      (1 << 12)               /* End of Bus Reset Interrpt Status */
+#define         AT91_UDP_WAKEUP         (1 << 13)               /* USB Wakeup Interrupt Status */
+#define AT91_UDP_ICR            0x20            /* Interrupt Clear Register */
+#define AT91_UDP_RST_EP         0x28            /* Reset Endpoint Register */
+#define AT91_UDP_CSR(n)         (0x30 + ((n) * 4))      /* Endpoint Control/Status Registers 0-7 */
+#define         AT91_UDP_TXCOMP         (1 <<  0)               /* Generates IN packet with data previously written in DPR */
+#define         AT91_UDP_RX_DATA_BK0    (1 <<  1)               /* Receive Data Bank 0 */
+#define         AT91_UDP_RXSETUP        (1 <<  2)               /* Send STALL to the host */
+#define         AT91_UDP_STALLSENT      (1 <<  3)               /* Stall Sent / Isochronous error (Isochronous endpoints) */
+#define         AT91_UDP_TXPKTRDY       (1 <<  4)               /* Transmit Packet Ready */
+#define         AT91_UDP_FORCESTALL     (1 <<  5)               /* Force Stall */
+#define         AT91_UDP_RX_DATA_BK1    (1 <<  6)               /* Receive Data Bank 1 */
+#define         AT91_UDP_DIR            (1 <<  7)               /* Transfer Direction */
+#define         AT91_UDP_EPTYPE         (7 <<  8)               /* Endpoint Type */
+#define                 AT91_UDP_EPTYPE_CTRL            (0 <<  8)
+#define                 AT91_UDP_EPTYPE_ISO_OUT         (1 <<  8)
+#define                 AT91_UDP_EPTYPE_BULK_OUT        (2 <<  8)
+#define                 AT91_UDP_EPTYPE_INT_OUT         (3 <<  8)
+#define                 AT91_UDP_EPTYPE_ISO_IN          (5 <<  8)
+#define                 AT91_UDP_EPTYPE_BULK_IN         (6 <<  8)
+#define                 AT91_UDP_EPTYPE_INT_IN          (7 <<  8)
+#define         AT91_UDP_DTGLE          (1 << 11)               /* Data Toggle */
+#define         AT91_UDP_EPEDS          (1 << 15)               /* Endpoint Enable/Disable */
+#define         AT91_UDP_RXBYTECNT      (0x7ff << 16)           /* Number of bytes in FIFO */
+#define AT91_UDP_FDR(n)         (0x50 + ((n) * 4))      /* Endpoint FIFO Data Registers 0-7 */
+#define AT91_UDP_TXVC           0x74            /* Transceiver Control Register */
+#define         AT91_UDP_TXVC_TXVDIS    (1 << 8)                /* Transceiver Disable */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
index 4fdef13d01d4..1fdd70b23809 100644
--- a/include/asm-arm/arch-at91rm9200/board.h
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -31,14 +31,9 @@
 #ifndef __ASM_ARCH_BOARD_H
 #define __ASM_ARCH_BOARD_H
- /* Clocks */
-extern unsigned long at91_master_clock;
- /* Serial Port */
-extern int at91_serial_map[AT91_NR_UART];
-extern int at91_console_port;
 #include <linux/mtd/partitions.h>
+#include <linux/device.h>
+#include <linux/spi/spi.h>
 /* USB Device */
 struct at91_udc_data {
@@ -91,10 +86,25 @@ struct at91_nand_data {
 extern void __init at91_add_device_nand(struct at91_nand_data *data);
 /* I2C*/
-void __init at91_add_device_i2c(void);
+extern void __init at91_add_device_i2c(void);
+ /* SPI */
+extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
- /* RTC */
+ /* Serial */
-void __init at91_add_device_rtc(void);
+struct at91_uart_config {
+        unsigned short  console_tty;    /* tty number of serial console */
+        unsigned short  nr_tty;         /* number of serial tty's */
+        short           tty_map[];      /* map UART to tty number */
+};
+extern struct platform_device *at91_default_console_device;
+extern void __init at91_init_serial(struct at91_uart_config *config);
+struct at91_uart_data {
+        short           use_dma_tx;     /* use transmit DMA? */
+        short           use_dma_rx;     /* use receive DMA? */
+};
+extern void __init at91_add_device_serial(void);
 /* LEDs */
 extern u8 at91_leds_cpu;
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
index 6176ab2dc417..dbde1baaf251 100644
--- a/include/asm-arm/arch-at91rm9200/gpio.h
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_AT91RM9200_GPIO_H
 #define __ASM_ARCH_AT91RM9200_GPIO_H
+#include <asm/irq.h>
 #define PIN_BASE                NR_AIC_IRQS
 #define PQFP_GPIO_BANKS         3       /* PQFP package has 3 banks */
@@ -188,6 +190,9 @@ extern int at91_set_multi_drive(unsigned pin, int is_on);
 /* callable at any time */
 extern int at91_set_gpio_value(unsigned pin, int value);
 extern int at91_get_gpio_value(unsigned pin);
+extern void at91_gpio_suspend(void);
+extern void at91_gpio_resume(void);
 #endif
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 59e6f44d3a0d..235d39d91107 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -50,9 +50,12 @@
 #define AT91_VA_BASE_TCB0       AT91_IO_P2V(AT91_BASE_TCB0)
 /* Internal SRAM */
-#define AT91_BASE_SRAM          0x00200000      /* Internal SRAM base address */
+#define AT91_SRAM_BASE          0x00200000      /* Internal SRAM base address */
 #define AT91_SRAM_SIZE          0x00004000      /* Internal SRAM SIZE (16Kb) */
+ /* Internal SRAM is mapped below the IO devices */
+#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE)
 /* Serial ports */
 #define AT91_NR_UART            5               /* 4 USART3's and one DBGU port */
@@ -81,14 +84,14 @@ static inline unsigned int at91_sys_read(unsigned int reg_offset)
 {
        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-        return readl(addr + reg_offset);
+        return __raw_readl(addr + reg_offset);
 }
 static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
 {
        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-        writel(value, addr + reg_offset);
+        __raw_writel(value, addr + reg_offset);
 }
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/io.h b/include/asm-arm/arch-at91rm9200/io.h
index 23e670d85c9d..88fd1bebcef3 100644
--- a/include/asm-arm/arch-at91rm9200/io.h
+++ b/include/asm-arm/arch-at91rm9200/io.h
@@ -21,7 +21,6 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
-#include <asm/arch/at91rm9200.h>
 #include <asm/io.h>
 #define IO_SPACE_LIMIT          0xFFFFFFFF
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index 27b0497f1b36..2dc93b174a8f 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -37,8 +37,6 @@
 * symbols in gpio.h for ones handled indirectly as GPIOs.
 * We make provision for 4 banks of GPIO.
 */
-#include <asm/arch/gpio.h>
 #define NR_IRQS         (NR_AIC_IRQS + (4 * 32))
diff --git a/include/asm-arm/arch-at91rm9200/memory.h b/include/asm-arm/arch-at91rm9200/memory.h
index 462f1f0ad67c..3c327c404373 100644
--- a/include/asm-arm/arch-at91rm9200/memory.h
+++ b/include/asm-arm/arch-at91rm9200/memory.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define PHYS_OFFSET     (AT91_SDRAM_BASE)
diff --git a/include/asm-arm/arch-at91rm9200/pio.h b/include/asm-arm/arch-at91rm9200/pio.h
deleted file mode 100644
index a89501b4a703..000000000000
--- a/include/asm-arm/arch-at91rm9200/pio.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * include/asm-arm/arch-at91rm9200/pio.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_PIO_H
-#define __ASM_ARCH_PIO_H
-#include <asm/arch/hardware.h>
-static inline void AT91_CfgPIO_USART0(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA17_TXD0 | AT91_PA18_RXD0 | AT91_PA20_CTS0);
-        /*
-         * Errata #39 - RTS0 is not internally connected to PA21.  We need to drive
-         *  the pin manually.  Default is off (RTS is active low).
-         */
-        at91_sys_write(AT91_PIOA + PIO_PER, AT91_PA21_RTS0);
-        at91_sys_write(AT91_PIOA + PIO_OER, AT91_PA21_RTS0);
-        at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
-}
-static inline void AT91_CfgPIO_USART1(void) {
-        at91_sys_write(AT91_PIOB + PIO_PDR, AT91_PB18_RI1 | AT91_PB19_DTR1
-                        | AT91_PB20_TXD1 | AT91_PB21_RXD1 | AT91_PB23_DCD1
-                        | AT91_PB24_CTS1 | AT91_PB25_DSR1 | AT91_PB26_RTS1);
-}
-static inline void AT91_CfgPIO_USART2(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA22_RXD2 | AT91_PA23_TXD2);
-}
-static inline void AT91_CfgPIO_USART3(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
-        at91_sys_write(AT91_PIOA + PIO_BSR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
-}
-static inline void AT91_CfgPIO_DBGU(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA31_DTXD | AT91_PA30_DRXD);
-}
-/*
- * Enable the Two-Wire interface.
- */
-static inline void AT91_CfgPIO_TWI(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA25_TWD | AT91_PA26_TWCK);
-        at91_sys_write(AT91_PIOA + PIO_ASR, AT91_PA25_TWD | AT91_PA26_TWCK);
-        at91_sys_write(AT91_PIOA + PIO_MDER, AT91_PA25_TWD | AT91_PA26_TWCK);           /* open drain */
-}
-/*
- * Enable the Serial Peripheral Interface.
- */
-static inline void AT91_CfgPIO_SPI(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA0_MISO | AT91_PA1_MOSI | AT91_PA2_SPCK);
-}
-static inline void AT91_CfgPIO_SPI_CS0(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA3_NPCS0);
-}
-static inline void AT91_CfgPIO_SPI_CS1(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA4_NPCS1);
-}
-static inline void AT91_CfgPIO_SPI_CS2(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_NPCS2);
-}
-static inline void AT91_CfgPIO_SPI_CS3(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA6_NPCS3);
-}
-/*
- * Select the DataFlash card.
- */
-static inline void AT91_CfgPIO_DataFlashCard(void) {
-        at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(7));
-        at91_sys_write(AT91_PIOB + PIO_OER, AT91_PIO_P(7));
-        at91_sys_write(AT91_PIOB + PIO_CODR, AT91_PIO_P(7));
-}
-/*
- * Enable NAND Flash (SmartMedia) interface.
- */
-static inline void AT91_CfgPIO_SmartMedia(void) {
-        /* enable PC0=SMCE, PC1=SMOE, PC3=SMWE, A21=CLE, A22=ALE */
-        at91_sys_write(AT91_PIOC + PIO_ASR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
-        at91_sys_write(AT91_PIOC + PIO_PDR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
-        /* Configure PC2 as input (signal READY of the SmartMedia) */
-        at91_sys_write(AT91_PIOC + PIO_PER, AT91_PC2_BFAVD);    /* enable direct output enable */
-        at91_sys_write(AT91_PIOC + PIO_ODR, AT91_PC2_BFAVD);    /* disable output */
-        /* Configure PB1 as input (signal Card Detect of the SmartMedia) */
-        at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(1));     /* enable direct output enable */
-        at91_sys_write(AT91_PIOB + PIO_ODR, AT91_PIO_P(1));     /* disable output */
-}
-static inline int AT91_PIO_SmartMedia_RDY(void) {
-        return (at91_sys_read(AT91_PIOC + PIO_PDSR) & AT91_PIO_P(2)) ? 1 : 0;
-}
-static inline int AT91_PIO_SmartMedia_CardDetect(void) {
-        return (at91_sys_read(AT91_PIOB + PIO_PDSR) & AT91_PIO_P(1)) ? 1 : 0;
-}
-#endif
diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h
index 29c42655f05c..8a2ff472e4cf 100644
--- a/include/asm-arm/arch-at91rm9200/system.h
+++ b/include/asm-arm/arch-at91rm9200/system.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 static inline void arch_idle(void)
 {
@@ -48,4 +48,12 @@ static inline void arch_reset(char mode)
        at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
 }
+#define ARCH_ID_AT91RM9200      0x09200080
+#define ARCH_ID_AT91SAM9261     0x019000a0
+static inline unsigned long arch_identify(void)
+{
+        return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH);
+}
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/timex.h b/include/asm-arm/arch-at91rm9200/timex.h
index 3f112dd12587..88687cefe6eb 100644
--- a/include/asm-arm/arch-at91rm9200/timex.h
+++ b/include/asm-arm/arch-at91rm9200/timex.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h
index 7b38497c24b5..ec7811ab0a52 100644
--- a/include/asm-arm/arch-at91rm9200/uncompress.h
+++ b/include/asm-arm/arch-at91rm9200/uncompress.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 /*
 * The following code assumes the serial port has already been
diff --git a/include/asm-arm/arch-at91rm9200/vmalloc.h b/include/asm-arm/arch-at91rm9200/vmalloc.h
index 34d9718feb90..4c367eb57f47 100644
--- a/include/asm-arm/arch-at91rm9200/vmalloc.h
+++ b/include/asm-arm/arch-at91rm9200/vmalloc.h
@@ -21,6 +21,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END             (AT91_IO_VIRT_BASE & PGDIR_MASK)
+#define VMALLOC_END             (AT91_SRAM_VIRT_BASE & PGDIR_MASK)
 #endif
diff --git a/include/asm-arm/arch-cl7500/acornfb.h b/include/asm-arm/arch-cl7500/acornfb.h
index 3867231a4470..aea6330c9745 100644
--- a/include/asm-arm/arch-cl7500/acornfb.h
+++ b/include/asm-arm/arch-cl7500/acornfb.h
@@ -1,4 +1,3 @@
-#include <linux/config.h>
 #define acornfb_valid_pixrate(var) (var->pixclock >= 39325 && var->pixclock <= 40119)
 static inline void
diff --git a/include/asm-arm/arch-clps711x/hardware.h b/include/asm-arm/arch-clps711x/hardware.h
index 1386871e1a5a..0fdbe72fff2a 100644
--- a/include/asm-arm/arch-clps711x/hardware.h
+++ b/include/asm-arm/arch-clps711x/hardware.h
@@ -22,7 +22,6 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
-#include <linux/config.h>
 #define CLPS7111_VIRT_BASE      0xff000000
 #define CLPS7111_BASE           CLPS7111_VIRT_BASE
diff --git a/include/asm-arm/arch-clps711x/io.h b/include/asm-arm/arch-clps711x/io.h
index 62613b0e2d96..53d790202c19 100644
--- a/include/asm-arm/arch-clps711x/io.h
+++ b/include/asm-arm/arch-clps711x/io.h
@@ -26,7 +26,6 @@
 #define __io(a)                 ((void __iomem *)(a))
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 /*
 * We don't support ins[lb]/outs[lb].  Make them fault.
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index 61d8717406ce..c6e8dcf674de 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -20,7 +20,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-#include <linux/config.h>
 /*
 * Physical DRAM offset.
diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h
index 07157b7e4b20..03d233ae87ce 100644
--- a/include/asm-arm/arch-clps711x/uncompress.h
+++ b/include/asm-arm/arch-clps711x/uncompress.h
@@ -17,7 +17,6 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <linux/config.h>
 #include <asm/arch/io.h>
 #include <asm/hardware.h>
 #include <asm/hardware/clps7111.h>
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h
index ec51fe92483b..daad8ee2d194 100644
--- a/include/asm-arm/arch-ebsa285/hardware.h
+++ b/include/asm-arm/arch-ebsa285/hardware.h
@@ -12,7 +12,6 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
-#include <linux/config.h>
 #include <asm/arch/memory.h>
 #ifdef CONFIG_ARCH_FOOTBRIDGE
diff --git a/include/asm-arm/arch-ebsa285/io.h b/include/asm-arm/arch-ebsa285/io.h
index 776f9d377057..f9c729141860 100644
--- a/include/asm-arm/arch-ebsa285/io.h
+++ b/include/asm-arm/arch-ebsa285/io.h
@@ -24,7 +24,6 @@
 #define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
 #if 1
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            ((a) + PCIMEM_BASE)
 #else
 static inline void __iomem *___mem_pci(void __iomem *p)
@@ -34,14 +33,7 @@ static inline void __iomem *___mem_pci(void __iomem *p)
        return p;
 }
-static inline void __iomem *___mem_isa(void __iomem *p)
-{
-        unsigned long a = (unsigned long)p;
-        BUG_ON(a >= 16*1048576);
-        return p + PCIMEM_BASE;
-}
 #define __mem_pci(a)            ___mem_pci(a)
-#define __mem_isa(a)            ___mem_isa(a)
 #endif
 #endif
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index 99181ffc7e27..cbd7ae64bcc9 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -19,7 +19,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-#include <linux/config.h>
 #if defined(CONFIG_FOOTBRIDGE_ADDIN)
 /*
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
index d1ca955ce434..02598200997d 100644
--- a/include/asm-arm/arch-ebsa285/vmalloc.h
+++ b/include/asm-arm/arch-ebsa285/vmalloc.h
@@ -6,7 +6,6 @@
 * published by the Free Software Foundation.
 */
-#include <linux/config.h>
 #ifdef CONFIG_ARCH_FOOTBRIDGE
 #define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-arm/arch-ep93xx/ep93xx-regs.h
index 71cea0b5841b..8c322975f96e 100644
--- a/include/asm-arm/arch-ep93xx/ep93xx-regs.h
+++ b/include/asm-arm/arch-ep93xx/ep93xx-regs.h
@@ -115,6 +115,8 @@
 #define EP93XX_SYSCON_CLOCK_USH_EN      0x10000000
 #define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
+#define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
 #define EP93XX_SYSCON_DEVICE_CONFIG     EP93XX_SYSCON_REG(0x80)
 #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE       0x00800000
 #define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
diff --git a/include/asm-arm/arch-ep93xx/platform.h b/include/asm-arm/arch-ep93xx/platform.h
index df9cbb6ef660..d7a34ce20293 100644
--- a/include/asm-arm/arch-ep93xx/platform.h
+++ b/include/asm-arm/arch-ep93xx/platform.h
@@ -8,6 +8,7 @@ void ep93xx_map_io(void);
 void ep93xx_init_irq(void);
 void ep93xx_init_time(unsigned long);
 void ep93xx_init_devices(void);
+void ep93xx_clock_init(void);
 extern struct sys_timer ep93xx_timer;
diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h
index f2063c1d610d..599f03e5a9ef 100644
--- a/include/asm-arm/arch-imx/imx-dma.h
+++ b/include/asm-arm/arch-imx/imx-dma.h
@@ -46,7 +46,7 @@
 struct imx_dma_channel {
        const char *name;
        void (*irq_handler) (int, void *, struct pt_regs *);
-        void (*err_handler) (int, void *, struct pt_regs *);
+        void (*err_handler) (int, void *, struct pt_regs *, int errcode);
        void *data;
        dmamode_t  dma_mode;
        struct scatterlist *sg;
@@ -58,6 +58,10 @@ struct imx_dma_channel {
 extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
+#define IMX_DMA_ERR_BURST     1
+#define IMX_DMA_ERR_REQUEST   2
+#define IMX_DMA_ERR_TRANSFER  4
+#define IMX_DMA_ERR_BUFFER    8
 /* The type to distinguish channel numbers parameter from ordinal int type */
 typedef int imx_dmach_t;
@@ -74,7 +78,7 @@ imx_dma_setup_sg(imx_dmach_t dma_ch,
 int
 imx_dma_setup_handlers(imx_dmach_t dma_ch,
                void (*irq_handler) (int, void *, struct pt_regs *),
-                void (*err_handler) (int, void *, struct pt_regs *), void *data);
+                void (*err_handler) (int, void *, struct pt_regs *, int), void *data);
 void imx_dma_enable(imx_dmach_t dma_ch);
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h
index 31f2deab51b0..c8f2175948bd 100644
--- a/include/asm-arm/arch-integrator/io.h
+++ b/include/asm-arm/arch-integrator/io.h
@@ -32,6 +32,5 @@
 #define __io(a)                 ((void __iomem *)(PCI_IO_VADDR + (a)))
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            ((a) + PCI_MEMORY_VADDR)
 #endif
diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h
index da6981efdc39..ab2c79bb9505 100644
--- a/include/asm-arm/arch-integrator/smp.h
+++ b/include/asm-arm/arch-integrator/smp.h
@@ -1,7 +1,6 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
-#include <linux/config.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop3xx/io.h
index f39046a6ab14..36adbdf5055a 100644
--- a/include/asm-arm/arch-iop3xx/io.h
+++ b/include/asm-arm/arch-iop3xx/io.h
@@ -17,6 +17,5 @@
 #define __io(p)                 ((void __iomem *)(p))
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 #endif
diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h
index bc62f4b13235..e43ebd984745 100644
--- a/include/asm-arm/arch-iop3xx/memory.h
+++ b/include/asm-arm/arch-iop3xx/memory.h
@@ -5,7 +5,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-#include <linux/config.h>
 #include <asm/hardware.h>
 /*
diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h
index 472badb451c4..14ca8d0f7b29 100644
--- a/include/asm-arm/arch-iop3xx/timex.h
+++ b/include/asm-arm/arch-iop3xx/timex.h
@@ -3,7 +3,6 @@
 *
 * IOP3xx architecture timex specifications
 */
-#include <linux/config.h>
 #include <asm/hardware.h>
 #if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h
index c98eb6254b1f..fbdd5af644fe 100644
--- a/include/asm-arm/arch-iop3xx/uncompress.h
+++ b/include/asm-arm/arch-iop3xx/uncompress.h
@@ -1,7 +1,6 @@
 /*
 *  linux/include/asm-arm/arch-iop3xx/uncompress.h
 */
-#include <linux/config.h>
 #include <asm/types.h>
 #include <asm/mach-types.h>
 #include <linux/serial_reg.h>
diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S
index 0ef4e6016ac4..867761677b57 100644
--- a/include/asm-arm/arch-ixp23xx/entry-macro.S
+++ b/include/asm-arm/arch-ixp23xx/entry-macro.S
@@ -8,7 +8,7 @@
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                ldr     \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
                ldr     \irqnr, [\irqnr]        @ get interrupt number
-                cmp     \irqnr, #0x0            @ suprious interrupt ?
+                cmp     \irqnr, #0x0            @ spurious interrupt ?
                movne   \irqnr, \irqnr, lsr #2  @ skip unwanted low order bits
                subne   \irqnr, \irqnr, #1      @ convert to 0 based
diff --git a/include/asm-arm/arch-ixp23xx/ixp23xx.h b/include/asm-arm/arch-ixp23xx/ixp23xx.h
index e49e1ca61b1a..d0a72201ee96 100644
--- a/include/asm-arm/arch-ixp23xx/ixp23xx.h
+++ b/include/asm-arm/arch-ixp23xx/ixp23xx.h
@@ -124,6 +124,7 @@
 #define IXP23XX_EXP_UNIT_FUSE           IXP23XX_EXP_CFG_REG(0x28)
 #define IXP23XX_EXP_MSF_MUX             IXP23XX_EXP_CFG_REG(0x30)
+#define IXP23XX_EXP_CFG_FUSE            IXP23XX_EXP_CFG_REG(0x34)
 #define IXP23XX_EXP_BUS_PHYS            0x90000000
 #define IXP23XX_EXP_BUS_WINDOW_SIZE     0x01000000
@@ -251,7 +252,7 @@
 * CAP CSRs.
 ****************************************************************************/
 #define IXP23XX_GLOBAL_REG(x)           ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
-#define IXP23XX_PROD_IDG                IXP23XX_GLOBAL_REG(0x00)
+#define IXP23XX_PRODUCT_ID              IXP23XX_GLOBAL_REG(0x00)
 #define IXP23XX_MISC_CONTROL            IXP23XX_GLOBAL_REG(0x04)
 #define IXP23XX_MSF_CLK_CNTRL           IXP23XX_GLOBAL_REG(0x08)
 #define IXP23XX_RESET0                  IXP23XX_GLOBAL_REG(0x0c)
@@ -265,6 +266,8 @@
 #define IXP23XX_PCI_UNIT_RESET          (1 << 1)
 #define IXP23XX_XSCALE_RESET            (1 << 0)
+#define IXP23XX_UENGINE_CSR_VIRT_BASE   (IXP23XX_CAP_CSR_VIRT + 0x18000)
 /****************************************************************************
 * PCI CSRs.
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h
index e4d99060a049..19a73b39c864 100644
--- a/include/asm-arm/arch-ixp23xx/platform.h
+++ b/include/asm-arm/arch-ixp23xx/platform.h
@@ -14,6 +14,21 @@
 #ifndef __ASSEMBLY__
+extern inline unsigned long ixp2000_reg_read(volatile void *reg)
+{
+        return *((volatile unsigned long *)reg);
+}
+extern inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
+{
+        *((volatile unsigned long *)reg) = val;
+}
+extern inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
+{
+        *((volatile unsigned long *)reg) = val;
+}
 struct pci_sys_data;
 void ixp23xx_map_io(void);
diff --git a/include/asm-arm/arch-ixp4xx/dma.h b/include/asm-arm/arch-ixp4xx/dma.h
index b1a071ecebc8..789f7f53c357 100644
--- a/include/asm-arm/arch-ixp4xx/dma.h
+++ b/include/asm-arm/arch-ixp4xx/dma.h
@@ -11,7 +11,6 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
-#include <linux/config.h>
 #include <linux/device.h>
 #include <linux/pci.h>
 #include <asm/page.h>
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index cab8ad0adf09..cd080d8384d9 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -19,7 +19,6 @@
 */
 #define __io_pci(a)             ((void __iomem *)(PCIO_BASE + (a)))
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 #define __ioaddr(p)             __io_pci(p)
diff --git a/include/asm-arm/arch-lh7a40x/clocks.h b/include/asm-arm/arch-lh7a40x/clocks.h
new file mode 100644
index 000000000000..bee02fd8dab1
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/clocks.h
@@ -0,0 +1,20 @@
+/* include/asm-arm/arch-lh7a40x/clocks.h
+ *
+ *  Copyright (C) 2004 Marc Singer
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+#include <linux/config.h>
+#ifndef __ASM_ARCH_CLOCKS_H
+#define __ASM_ARCH_CLOCKS_H
+unsigned int fclkfreq_get (void);
+unsigned int hclkfreq_get (void);
+unsigned int pclkfreq_get (void);
+#endif  /* _ASM_ARCH_CLOCKS_H */
diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h
index 52c1cb9c39c6..51de96e87faf 100644
--- a/include/asm-arm/arch-lh7a40x/constants.h
+++ b/include/asm-arm/arch-lh7a40x/constants.h
@@ -12,7 +12,6 @@
 #ifndef __ASM_ARCH_CONSTANTS_H
 #define __ASM_ARCH_CONSTANTS_H
-#include <linux/config.h>
 /* Addressing constants */
@@ -29,8 +28,7 @@
 #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
-# define IOBARRIER_PHYS         0xc0000000 /* Start of SDRAM */
+# define IOBARRIER_PHYS         0x10000000 /* Second bank, fastest timing */
-/*# define IOBARRIER_PHYS               0x00000000 */ /* Start of flash */
 # define IOBARRIER_VIRT         0xf0000000
 # define IOBARRIER_SIZE         PAGE_SIZE
@@ -53,6 +51,9 @@
 # define CPLD08_PHYS            CPLDX_PHYS (0x08)
 # define CPLD08_VIRT            CPLDX_VIRT (0x08)
 # define CPLD08_SIZE            PAGE_SIZE
+# define CPLD0A_PHYS            CPLDX_PHYS (0x0a)
+# define CPLD0A_VIRT            CPLDX_VIRT (0x0a)
+# define CPLD0A_SIZE            PAGE_SIZE
 # define CPLD0C_PHYS            CPLDX_PHYS (0x0c)
 # define CPLD0C_VIRT            CPLDX_VIRT (0x0c)
 # define CPLD0C_SIZE            PAGE_SIZE
@@ -84,5 +85,7 @@
 #define XTAL_IN                 14745600        /* 14.7456 MHz crystal */
 #define PLL_CLOCK               (XTAL_IN * 21)  /* 309 MHz PLL clock */
 #define MAX_HCLK_KHZ            100000          /* HCLK max limit ~100MHz */
+#define HCLK                    (99993600)
+//#define HCLK                  (119808000)
 #endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h
index 15492e3253f6..a8cbd14bbf9d 100644
--- a/include/asm-arm/arch-lh7a40x/dma.h
+++ b/include/asm-arm/arch-lh7a40x/dma.h
@@ -1,9 +1,86 @@
 /* include/asm-arm/arch-lh7a40x/dma.h
 *
- *  Copyright (C) 2003 Coastal Environmental Systems
+ *  Copyright (C) 2005 Marc Singer
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  version 2 as published by the Free Software Foundation.
 *
 */
+typedef enum {
+        DMA_M2M0        = 0,
+        DMA_M2M1        = 1,
+        DMA_M2P0        = 2,    /* Tx */
+        DMA_M2P1        = 3,    /* Rx */
+        DMA_M2P2        = 4,    /* Tx */
+        DMA_M2P3        = 5,    /* Rx */
+        DMA_M2P4        = 6,    /* Tx - AC97 */
+        DMA_M2P5        = 7,    /* Rx - AC97 */
+        DMA_M2P6        = 8,    /* Tx */
+        DMA_M2P7        = 9,    /* Rx */
+} dma_device_t;
+#define DMA_LENGTH_MAX          ((64*1024) - 4) /* bytes */
+#define DMAC_GCA                __REG(DMAC_PHYS + 0x2b80)
+#define DMAC_GIR                __REG(DMAC_PHYS + 0x2bc0)
+#define DMAC_GIR_MMI1           (1<<11)
+#define DMAC_GIR_MMI0           (1<<10)
+#define DMAC_GIR_MPI8           (1<<9)
+#define DMAC_GIR_MPI9           (1<<8)
+#define DMAC_GIR_MPI6           (1<<7)
+#define DMAC_GIR_MPI7           (1<<6)
+#define DMAC_GIR_MPI4           (1<<5)
+#define DMAC_GIR_MPI5           (1<<4)
+#define DMAC_GIR_MPI2           (1<<3)
+#define DMAC_GIR_MPI3           (1<<2)
+#define DMAC_GIR_MPI0           (1<<1)
+#define DMAC_GIR_MPI1           (1<<0)
+#define DMAC_M2P0               0x0000
+#define DMAC_M2P1               0x0040
+#define DMAC_M2P2               0x0080
+#define DMAC_M2P3               0x00c0
+#define DMAC_M2P4               0x0240
+#define DMAC_M2P5               0x0200
+#define DMAC_M2P6               0x02c0
+#define DMAC_M2P7               0x0280
+#define DMAC_M2P8               0x0340
+#define DMAC_M2P9               0x0300
+#define DMAC_M2M0               0x0100
+#define DMAC_M2M1               0x0140
+#define DMAC_P_PCONTROL(c)      __REG(DMAC_PHYS + (c) + 0x00)
+#define DMAC_P_PINTERRUPT(c)    __REG(DMAC_PHYS + (c) + 0x04)
+#define DMAC_P_PPALLOC(c)       __REG(DMAC_PHYS + (c) + 0x08)
+#define DMAC_P_PSTATUS(c)       __REG(DMAC_PHYS + (c) + 0x0c)
+#define DMAC_P_REMAIN(c)        __REG(DMAC_PHYS + (c) + 0x14)
+#define DMAC_P_MAXCNT0(c)       __REG(DMAC_PHYS + (c) + 0x20)
+#define DMAC_P_BASE0(c)         __REG(DMAC_PHYS + (c) + 0x24)
+#define DMAC_P_CURRENT0(c)      __REG(DMAC_PHYS + (c) + 0x28)
+#define DMAC_P_MAXCNT1(c)       __REG(DMAC_PHYS + (c) + 0x30)
+#define DMAC_P_BASE1(c)         __REG(DMAC_PHYS + (c) + 0x34)
+#define DMAC_P_CURRENT1(c)      __REG(DMAC_PHYS + (c) + 0x38)
+#define DMAC_PCONTROL_ENABLE    (1<<4)
+#define DMAC_PORT_USB           0
+#define DMAC_PORT_SDMMC         1
+#define DMAC_PORT_AC97_1        2
+#define DMAC_PORT_AC97_2        3
+#define DMAC_PORT_AC97_3        4
+#define DMAC_PORT_UART1         6
+#define DMAC_PORT_UART2         7
+#define DMAC_PORT_UART3         8
+#define DMAC_PSTATUS_CURRSTATE_SHIFT    4
+#define DMAC_PSTATUS_CURRSTATE_MASK     0x3
+#define DMAC_PSTATUS_NEXTBUF     (1<<6)
+#define DMAC_PSTATUS_STALLRINT   (1<<0)
+#define DMAC_INT_CHE             (1<<3)
+#define DMAC_INT_NFB             (1<<1)
+#define DMAC_INT_STALL           (1<<0)
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S
index a2f67c06d9c9..9fc7f4988124 100644
--- a/include/asm-arm/arch-lh7a40x/entry-macro.S
+++ b/include/asm-arm/arch-lh7a40x/entry-macro.S
@@ -10,11 +10,73 @@
 #include <asm/hardware.h>
 #include <asm/arch/irqs.h>
-# if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
+/* In order to allow there to be support for both of the processor
-#  error "LH7A400 and LH7A404 are mutually exclusive"
+   classes at the same time, we make a hack here that isn't very
-# endif
+   pretty.  At startup, the link pointed to with the
+   branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
+   detected as a lh7a404.
-# if defined (CONFIG_ARCH_LH7A400)
+   *** FIXME: we should clean this up so that there is only one
+              implementation for each CPU's design.
+*/
+#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+branch_irq_lh7a400: b 1000f
+@ Implementation of the LH7A404 get_irqnr_and_base.
+                mov     \irqnr, #0                      @ VIC1 irq base
+                mov     \base, #io_p2v(0x80000000)      @ APB registers
+                add     \base, \base, #0x8000
+                ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
+                tst     \tmp, #VA_VECTORED              @ Direct vectored
+                bne     1002f
+                tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
+                ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
+                bne     1001f
+                add     \base, \base, #(0xa000 - 0x8000)
+                ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
+                tst     \tmp, #VA_VECTORED              @ Direct vectored
+                bne     1002f
+                ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
+                mov     \irqnr, #32                     @ VIC2 irq base
+1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
+                bcs     1008f                           @ Bit set; irq found
+                add     \irqnr, \irqnr, #1
+                bne     1001b                           @ Until no bits
+                b       1009f                           @ Nothing?  Hmm.
+1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
+1008:           movs    \irqstat, #1                    @ Force !Z
+                str     \tmp, [\base, #0x0030]          @ Clear vector
+                b       1009f
+@ Implementation of the LH7A400 get_irqnr_and_base.
+1000:           mov     \irqnr, #0
+                mov     \base, #io_p2v(0x80000000)      @ APB registers
+                ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
+1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
+                bcs     1008f                           @ Bit set; irq found
+                add     \irqnr, \irqnr, #1
+                bne     1001b                           @ Until no bits
+                b       1009f                           @ Nothing?  Hmm.
+1008:           movs    \irqstat, #1                    @ Force !Z
+1009:
+               .endm
+#elif defined (CONFIG_ARCH_LH7A400)
                .macro  disable_fiq
                .endm
diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h
index aeb07c162e25..e9ff74fd7939 100644
--- a/include/asm-arm/arch-lh7a40x/hardware.h
+++ b/include/asm-arm/arch-lh7a40x/hardware.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
+#include <asm/sizes.h>          /* Added for the sake of amba-clcd driver */
 #define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
 #define io_v2p(x) (             (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
@@ -53,6 +55,8 @@ typedef struct { volatile u8 offset[4096]; } __regbase8;
 #endif
+#define MASK_AND_SET(v,m,s)     (v) = ((v)&~(m))|(s)
 #include "registers.h"
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h
index bbcd4335f441..17bc94097481 100644
--- a/include/asm-arm/arch-lh7a40x/io.h
+++ b/include/asm-arm/arch-lh7a40x/io.h
@@ -18,6 +18,5 @@
 /* No ISA or PCI bus on this machine. */
 #define __io(a)                 ((void __iomem *)(a))
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 #endif /* __ASM_ARCH_IO_H */
diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h
index f91f3e59f3ab..afe8c7cbad6a 100644
--- a/include/asm-arm/arch-lh7a40x/irqs.h
+++ b/include/asm-arm/arch-lh7a40x/irqs.h
@@ -18,7 +18,6 @@
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
-#include <linux/config.h>
 #define FIQ_START       80
@@ -154,9 +153,10 @@
 #if !defined (IRQ_GPIO0INTR)
 # define IRQ_GPIO0INTR  IRQ_GPIO0FIQ
 #endif
-#define IRQ_TICK        IRQ_TINTR
+#define IRQ_TICK        IRQ_TINTR
 #define IRQ_PCC1_RDY    IRQ_GPIO6INTR   /* PCCard 1 ready */
 #define IRQ_PCC2_RDY    IRQ_GPIO7INTR   /* PCCard 2 ready */
+#define IRQ_USB         IRQ_USBINTR     /* USB device */
 #ifdef CONFIG_MACH_KEV7A400
 # define IRQ_TS         IRQ_GPIOFIQ     /* Touchscreen */
@@ -191,6 +191,10 @@
 # define IRQ_LPD7A400_TS        IRQ_LPD7A40X_CPLD + 1   /* Touch screen */
 #endif
+#if defined (CONFIG_MACH_LPD7A400)
+# define IRQ_TOUCH              IRQ_LPD7A400_TS
+#endif
 #define NR_IRQS         (NR_IRQ_CPU + NR_IRQ_BOARD)
 #endif
diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h
index 2edb22e35450..b4f09b3e2d03 100644
--- a/include/asm-arm/arch-lh7a40x/registers.h
+++ b/include/asm-arm/arch-lh7a40x/registers.h
@@ -9,7 +9,6 @@
 *
 */
-#include <linux/config.h>
 #include <asm/arch/constants.h>
 #ifndef __ASM_ARCH_REGISTERS_H
@@ -18,7 +17,7 @@
        /* Physical register base addresses */
-#define AC97_PHYS       (0x80000000)    /* AC97 Controller */
+#define AC97C_PHYS      (0x80000000)    /* AC97 Controller */
 #define MMC_PHYS        (0x80000100)    /* Multimedia Card Controller */
 #define USB_PHYS        (0x80000200)    /* USB Client */
 #define SCI_PHYS        (0x80000300)    /* Secure Card Interface */
@@ -35,6 +34,8 @@
 #define RTC_PHYS        (0x80000d00)    /* Real-time Clock */
 #define GPIO_PHYS       (0x80000e00)    /* General Purpose IO */
 #define BMI_PHYS        (0x80000f00)    /* Battery Monitor Interface */
+#define HRTFTC_PHYS     (0x80001000)    /* High-res TFT Controller (LH7A400) */
+#define ALI_PHYS        (0x80001000)    /* Advanced LCD Interface (LH7A404) */
 #define WDT_PHYS        (0x80001400)    /* Watchdog Timer */
 #define SMC_PHYS        (0x80002000)    /* Static Memory Controller */
 #define SDRC_PHYS       (0x80002400)    /* SDRAM Controller */
@@ -43,6 +44,7 @@
        /* Physical registers of the LH7A404 */
+#define ADC_PHYS        (0x80001300)    /* A/D & Touchscreen Controller */
 #define VIC1_PHYS       (0x80008000)    /* Vectored Interrupt Controller 1 */
 #define USBH_PHYS       (0x80009000)    /* USB OHCI host controller */
 #define VIC2_PHYS       (0x8000a000)    /* Vectored Interrupt Controller 2 */
@@ -53,10 +55,32 @@
        /* Clock/State Controller register */
+#define CSC_PWRSR       __REG(CSC_PHYS + 0x00) /* Reset register & ID */
 #define CSC_PWRCNT      __REG(CSC_PHYS + 0x04) /* Power control */
+#define CSC_CLKSET      __REG(CSC_PHYS + 0x20) /* Clock speed control */
+#define CSC_USBDRESET   __REG(CSC_PHYS + 0x4c) /* USB Device resets */
 #define CSC_PWRCNT_USBH_EN      (1<<28) /* USB Host power enable */
+#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
+#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
+#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
+#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
+#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
+#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
+#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
+#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
+#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
+#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
+#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
+#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
+#define CSC_PWRSR_CHIPMAN_SHIFT (24)
+#define CSC_PWRSR_CHIPMAN_MASK  (0xff)
+#define CSC_PWRSR_CHIPID_SHIFT  (16)
+#define CSC_PWRSR_CHIPID_MASK   (0xff)
+#define CSC_USBDRESET_APBRESETREG       (1<<1)
+#define CSC_USBDRESET_IORESETREG        (1<<0)
        /* Interrupt Controller registers */
@@ -109,6 +133,13 @@
 #define GPIO_GPIOFEOI   __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
 #define GPIO_GPIOINTEN  __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
 #define GPIO_INTSTATUS  __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
+#define GPIO_PINMUX     __REG(GPIO_PHYS + 0x2c)
+#define GPIO_PADD       __REG(GPIO_PHYS + 0x10)
+#define GPIO_PAD        __REG(GPIO_PHYS + 0x00)
+#define GPIO_PCD        __REG(GPIO_PHYS + 0x08)
+#define GPIO_PCDD       __REG(GPIO_PHYS + 0x18)
+#define GPIO_PEDD       __REG(GPIO_PHYS + 0x24)
+#define GPIO_PED        __REG(GPIO_PHYS + 0x20)
        /* Static Memory Controller registers */
@@ -138,20 +169,21 @@
 #endif
 #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
-# define CPLD_CONTROL           __REG8(CPLD02_PHYS)
-# define CPLD_SPI_DATA          __REG8(CPLD06_PHYS)
-# define CPLD_SPI_CONTROL       __REG8(CPLD08_PHYS)
-# define CPLD_SPI_EEPROM        __REG8(CPLD0A_PHYS)
-# define CPLD_INTERRUPTS        __REG8(CPLD0C_PHYS) /* IRQ mask/status */
-# define CPLD_BOOT_MODE         __REG8(CPLD0E_PHYS)
-# define CPLD_FLASH             __REG8(CPLD10_PHYS)
-# define CPLD_POWER_MGMT        __REG8(CPLD12_PHYS)
-# define CPLD_REVISION          __REG8(CPLD14_PHYS)
-# define CPLD_GPIO_EXT          __REG8(CPLD16_PHYS)
-# define CPLD_GPIO_DATA         __REG8(CPLD18_PHYS)
-# define CPLD_GPIO_DIR          __REG8(CPLD1A_PHYS)
-#endif
+# define CPLD_CONTROL           __REG16(CPLD02_PHYS)
+# define CPLD_SPI_DATA          __REG16(CPLD06_PHYS)
+# define CPLD_SPI_CONTROL       __REG16(CPLD08_PHYS)
+# define CPLD_SPI_EEPROM        __REG16(CPLD0A_PHYS)
+# define CPLD_INTERRUPTS        __REG16(CPLD0C_PHYS) /* IRQ mask/status */
+# define CPLD_BOOT_MODE         __REG16(CPLD0E_PHYS)
+# define CPLD_FLASH             __REG16(CPLD10_PHYS)
+# define CPLD_POWER_MGMT        __REG16(CPLD12_PHYS)
+# define CPLD_REVISION          __REG16(CPLD14_PHYS)
+# define CPLD_GPIO_EXT          __REG16(CPLD16_PHYS)
+# define CPLD_GPIO_DATA         __REG16(CPLD18_PHYS)
+# define CPLD_GPIO_DIR          __REG16(CPLD1A_PHYS)
+#endif
        /* Timer registers */
@@ -190,4 +222,3 @@
 #endif  /* _ASM_ARCH_REGISTERS_H */
diff --git a/include/asm-arm/arch-lh7a40x/ssp.h b/include/asm-arm/arch-lh7a40x/ssp.h
new file mode 100644
index 000000000000..132b1c4d5ce6
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/ssp.h
@@ -0,0 +1,71 @@
+/* ssp.h
+     $Id$
+   written by Marc Singer
+   6 Dec 2004
+   Copyright (C) 2004 Marc Singer
+   -----------
+   DESCRIPTION
+   -----------
+   This SSP header is available throughout the kernel, for this
+   machine/architecture, because drivers that use it may be dispersed.
+   This file was cloned from the 7952x implementation.  It would be
+   better to share them, but we're taking an easier approach for the
+   time being.
+*/
+#if !defined (__SSP_H__)
+#    define   __SSP_H__
+/* ----- Includes */
+/* ----- Types */
+struct ssp_driver {
+        int  (*init)            (void);
+        void (*exit)            (void);
+        void (*acquire)         (void);
+        void (*release)         (void);
+        int  (*configure)       (int device, int mode, int speed,
+                                 int frame_size_write, int frame_size_read);
+        void (*chip_select)     (int enable);
+        void (*set_callbacks)   (void* handle,
+                                 irqreturn_t (*callback_tx)(void*),
+                                 irqreturn_t (*callback_rx)(void*));
+        void (*enable)          (void);
+        void (*disable)         (void);
+//      int  (*save_state)      (void*);
+//      void (*restore_state)   (void*);
+        int  (*read)            (void);
+        int  (*write)           (u16 data);
+        int  (*write_read)      (u16 data);
+        void (*flush)           (void);
+        void (*write_async)     (void* pv, size_t cb);
+        size_t (*write_pos)     (void);
+};
+        /* These modes are only available on the LH79524 */
+#define SSP_MODE_SPI            (1)
+#define SSP_MODE_SSI            (2)
+#define SSP_MODE_MICROWIRE      (3)
+#define SSP_MODE_I2S            (4)
+        /* CPLD SPI devices */
+#define DEVICE_EEPROM   0       /* Configuration eeprom */
+#define DEVICE_MAC      1       /* MAC eeprom (LPD79524) */
+#define DEVICE_CODEC    2       /* Audio codec */
+#define DEVICE_TOUCH    3       /* Touch screen (LPD79520) */
+/* ----- Globals */
+/* ----- Prototypes */
+//extern struct ssp_driver lh79520_i2s_driver;
+extern struct ssp_driver lh7a400_cpld_ssp_driver;
+#endif  /* __SSP_H__ */
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
index f8053346f608..3d1ce0426a33 100644
--- a/include/asm-arm/arch-lh7a40x/uncompress.h
+++ b/include/asm-arm/arch-lh7a40x/uncompress.h
@@ -16,7 +16,7 @@
 #ifndef UART_R_STATUS
 # define UART_R_STATUS  (0x10)
 #endif
-#define nTxRdy          (0x20)  /* Not TxReady (literally Tx FIFO full) */
+#define nTxRdy          (0x20)  /* Not TxReady (literally Tx FIFO full) */
        /* Access UART with physical addresses before MMU is setup */
 #define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
diff --git a/include/asm-arm/arch-netx/debug-macro.S b/include/asm-arm/arch-netx/debug-macro.S
new file mode 100644
index 000000000000..a940d0e80cb2
--- /dev/null
+++ b/include/asm-arm/arch-netx/debug-macro.S
@@ -0,0 +1,38 @@
+/* linux/include/asm-arm/arch-netx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include "hardware.h"
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x00100000                @ physical
+                movne   \rx, #io_p2v(0x00100000)        @ virtual
+                orr     \rx, \rx, #0x00000a00
+                .endm
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0]
+                .endm
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x18]
+                tst     \rd, #(1 << 3)
+                bne     1002b
+                .endm
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]
+                tst     \rd, #(1 << 3)
+                bne     1001b
+                .endm
diff --git a/include/asm-arm/arch-netx/dma.h b/include/asm-arm/arch-netx/dma.h
new file mode 100644
index 000000000000..4eda5feed81c
--- /dev/null
+++ b/include/asm-arm/arch-netx/dma.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-netx/dma.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define MAX_DMA_CHANNELS 0
+#define MAX_DMA_ADDRESS ~0
diff --git a/include/asm-arm/arch-netx/entry-macro.S b/include/asm-arm/arch-netx/entry-macro.S
new file mode 100644
index 000000000000..658df4d60ff3
--- /dev/null
+++ b/include/asm-arm/arch-netx/entry-macro.S
@@ -0,0 +1,35 @@
+/*
+ * include/asm-arm/arch-netx/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Hilscher netX based platforms
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/hardware.h>
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \base, #io_p2v(0x00100000)
+                add     \base, \base, #0x000ff000
+                ldr     \irqstat, [\base, #0]
+                clz     \irqnr, \irqstat
+                rsb     \irqnr, \irqnr, #31
+                cmp     \irqstat, #0
+                .endm
diff --git a/include/asm-arm/arch-netx/eth.h b/include/asm-arm/arch-netx/eth.h
new file mode 100644
index 000000000000..643c90ef8b72
--- /dev/null
+++ b/include/asm-arm/arch-netx/eth.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-arm/arch-netx/eth.h
+ *
+ * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef ASMARM_ARCH_ETH_H
+#define ASMARM_ARCH_ETH_H
+struct netxeth_platform_data {
+        unsigned int xcno;      /* number of xmac/xpec engine this eth uses */
+};
+#endif
diff --git a/include/asm-arm/arch-netx/hardware.h b/include/asm-arm/arch-netx/hardware.h
new file mode 100644
index 000000000000..7786c45455cd
--- /dev/null
+++ b/include/asm-arm/arch-netx/hardware.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-arm/arch-netx/hardware.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#define NETX_IO_PHYS    0x00100000
+#define NETX_IO_VIRT    0xe0000000
+#define NETX_IO_SIZE    0x00100000
+#define SRAM_INTERNAL_PHYS_0 0x00000
+#define SRAM_INTERNAL_PHYS_1 0x08000
+#define SRAM_INTERNAL_PHYS_2 0x10000
+#define SRAM_INTERNAL_PHYS_3 0x18000
+#define SRAM_INTERNAL_PHYS(no) ((no) * 0x8000)
+#define XPEC_MEM_SIZE 0x4000
+#define XMAC_MEM_SIZE 0x1000
+#define SRAM_MEM_SIZE 0x8000
+#define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT)
+#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
+#endif
diff --git a/include/asm-arm/arch-netx/io.h b/include/asm-arm/arch-netx/io.h
new file mode 100644
index 000000000000..a7a53f80165d
--- /dev/null
+++ b/include/asm-arm/arch-netx/io.h
@@ -0,0 +1,28 @@
+/*
+ *  linux/include/asm-arm/arch-netx/io.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+#define __io(a)         ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-netx/irqs.h b/include/asm-arm/arch-netx/irqs.h
new file mode 100644
index 000000000000..a487dc6e2661
--- /dev/null
+++ b/include/asm-arm/arch-netx/irqs.h
@@ -0,0 +1,70 @@
+/*
+ * include/asm-arm/arch-netx/irqs.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define NETX_IRQ_VIC_START   0
+#define NETX_IRQ_SOFTINT     0
+#define NETX_IRQ_TIMER0      1
+#define NETX_IRQ_TIMER1      2
+#define NETX_IRQ_TIMER2      3
+#define NETX_IRQ_SYSTIME_NS  4
+#define NETX_IRQ_SYSTIME_S   5
+#define NETX_IRQ_GPIO_15     6
+#define NETX_IRQ_WATCHDOG    7
+#define NETX_IRQ_UART0       8
+#define NETX_IRQ_UART1       9
+#define NETX_IRQ_UART2      10
+#define NETX_IRQ_USB        11
+#define NETX_IRQ_SPI        12
+#define NETX_IRQ_I2C        13
+#define NETX_IRQ_LCD        14
+#define NETX_IRQ_HIF        15
+#define NETX_IRQ_GPIO_0_14  16
+#define NETX_IRQ_XPEC0      17
+#define NETX_IRQ_XPEC1      18
+#define NETX_IRQ_XPEC2      19
+#define NETX_IRQ_XPEC3      20
+#define NETX_IRQ_XPEC(no)   (17 + (no))
+#define NETX_IRQ_MSYNC0     21
+#define NETX_IRQ_MSYNC1     22
+#define NETX_IRQ_MSYNC2     23
+#define NETX_IRQ_MSYNC3     24
+#define NETX_IRQ_IRQ_PHY    25
+#define NETX_IRQ_ISO_AREA   26
+/* int 27 is reserved */
+/* int 28 is reserved */
+#define NETX_IRQ_TIMER3     29
+#define NETX_IRQ_TIMER4     30
+/* int 31 is reserved */
+#define NETX_IRQS 32
+/* for multiplexed irqs on gpio 0..14 */
+#define NETX_IRQ_GPIO(x) (NETX_IRQS + (x))
+#define NETX_IRQ_GPIO_LAST NETX_IRQ_GPIO(14)
+/* Host interface interrupts */
+#define NETX_IRQ_HIF_CHAINED(x)    (NETX_IRQ_GPIO_LAST + 1 + (x))
+#define NETX_IRQ_HIF_PIO35         NETX_IRQ_HIF_CHAINED(0)
+#define NETX_IRQ_HIF_PIO36         NETX_IRQ_HIF_CHAINED(1)
+#define NETX_IRQ_HIF_PIO40         NETX_IRQ_HIF_CHAINED(2)
+#define NETX_IRQ_HIF_PIO47         NETX_IRQ_HIF_CHAINED(3)
+#define NETX_IRQ_HIF_PIO72         NETX_IRQ_HIF_CHAINED(4)
+#define NETX_IRQ_HIF_LAST          NETX_IRQ_HIF_CHAINED(4)
+#define NR_IRQS (NETX_IRQ_HIF_LAST + 1)
diff --git a/include/asm-arm/arch-netx/memory.h b/include/asm-arm/arch-netx/memory.h
new file mode 100644
index 000000000000..6d8d2df3e99d
--- /dev/null
+++ b/include/asm-arm/arch-netx/memory.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/arch-netx/memory.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#define PHYS_OFFSET UL(0x80000000)
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+#endif
diff --git a/include/asm-arm/arch-netx/netx-regs.h b/include/asm-arm/arch-netx/netx-regs.h
new file mode 100644
index 000000000000..8ab45bea83ca
--- /dev/null
+++ b/include/asm-arm/arch-netx/netx-regs.h
@@ -0,0 +1,410 @@
+/*
+ * include/asm-arm/arch-netx/netx-regs.h
+ *
+ * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_NETX_REGS_H
+#define __ASM_ARCH_NETX_REGS_H
+/* offsets relative to the beginning of the io space */
+#define NETX_OFS_SYSTEM  0x00000
+#define NETX_OFS_MEMCR   0x00100
+#define NETX_OFS_DPMAS   0x03000
+#define NETX_OFS_GPIO    0x00800
+#define NETX_OFS_PIO     0x00900
+#define NETX_OFS_UART0   0x00a00
+#define NETX_OFS_UART1   0x00a40
+#define NETX_OFS_UART2   0x00a80
+#define NETX_OF_MIIMU    0x00b00
+#define NETX_OFS_SPI     0x00c00
+#define NETX_OFS_I2C     0x00d00
+#define NETX_OFS_SYSTIME 0x01100
+#define NETX_OFS_RTC     0x01200
+#define NETX_OFS_EXTBUS  0x03600
+#define NETX_OFS_LCD     0x04000
+#define NETX_OFS_USB     0x20000
+#define NETX_OFS_XMAC0   0x60000
+#define NETX_OFS_XMAC1   0x61000
+#define NETX_OFS_XMAC2   0x62000
+#define NETX_OFS_XMAC3   0x63000
+#define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000)
+#define NETX_OFS_PFIFO   0x64000
+#define NETX_OFS_XPEC0   0x70000
+#define NETX_OFS_XPEC1   0x74000
+#define NETX_OFS_XPEC2   0x78000
+#define NETX_OFS_XPEC3   0x7c000
+#define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000)
+#define NETX_OFS_VIC     0xff000
+/* physical addresses */
+#define NETX_PA_SYSTEM   (NETX_IO_PHYS + NETX_OFS_SYSTEM)
+#define NETX_PA_MEMCR    (NETX_IO_PHYS + NETX_OFS_MEMCR)
+#define NETX_PA_DPMAS    (NETX_IO_PHYS + NETX_OFS_DPMAS)
+#define NETX_PA_GPIO     (NETX_IO_PHYS + NETX_OFS_GPIO)
+#define NETX_PA_PIO      (NETX_IO_PHYS + NETX_OFS_PIO)
+#define NETX_PA_UART0    (NETX_IO_PHYS + NETX_OFS_UART0)
+#define NETX_PA_UART1    (NETX_IO_PHYS + NETX_OFS_UART1)
+#define NETX_PA_UART2    (NETX_IO_PHYS + NETX_OFS_UART2)
+#define NETX_PA_MIIMU    (NETX_IO_PHYS + NETX_OF_MIIMU)
+#define NETX_PA_SPI      (NETX_IO_PHYS + NETX_OFS_SPI)
+#define NETX_PA_I2C      (NETX_IO_PHYS + NETX_OFS_I2C)
+#define NETX_PA_SYSTIME  (NETX_IO_PHYS + NETX_OFS_SYSTIME)
+#define NETX_PA_RTC      (NETX_IO_PHYS + NETX_OFS_RTC)
+#define NETX_PA_EXTBUS   (NETX_IO_PHYS + NETX_OFS_EXTBUS)
+#define NETX_PA_LCD      (NETX_IO_PHYS + NETX_OFS_LCD)
+#define NETX_PA_USB      (NETX_IO_PHYS + NETX_OFS_USB)
+#define NETX_PA_XMAC0    (NETX_IO_PHYS + NETX_OFS_XMAC0)
+#define NETX_PA_XMAC1    (NETX_IO_PHYS + NETX_OFS_XMAC1)
+#define NETX_PA_XMAC2    (NETX_IO_PHYS + NETX_OFS_XMAC2)
+#define NETX_PA_XMAC3    (NETX_IO_PHYS + NETX_OFS_XMAC3)
+#define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no))
+#define NETX_PA_PFIFO    (NETX_IO_PHYS + NETX_OFS_PFIFO)
+#define NETX_PA_XPEC0    (NETX_IO_PHYS + NETX_OFS_XPEC0)
+#define NETX_PA_XPEC1    (NETX_IO_PHYS + NETX_OFS_XPEC1)
+#define NETX_PA_XPEC2    (NETX_IO_PHYS + NETX_OFS_XPEC2)
+#define NETX_PA_XPEC3    (NETX_IO_PHYS + NETX_OFS_XPEC3)
+#define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no))
+#define NETX_PA_VIC      (NETX_IO_PHYS + NETX_OFS_VIC)
+/* virual addresses */
+#define NETX_VA_SYSTEM   (NETX_IO_VIRT + NETX_OFS_SYSTEM)
+#define NETX_VA_MEMCR    (NETX_IO_VIRT + NETX_OFS_MEMCR)
+#define NETX_VA_DPMAS    (NETX_IO_VIRT + NETX_OFS_DPMAS)
+#define NETX_VA_GPIO     (NETX_IO_VIRT + NETX_OFS_GPIO)
+#define NETX_VA_PIO      (NETX_IO_VIRT + NETX_OFS_PIO)
+#define NETX_VA_UART0    (NETX_IO_VIRT + NETX_OFS_UART0)
+#define NETX_VA_UART1    (NETX_IO_VIRT + NETX_OFS_UART1)
+#define NETX_VA_UART2    (NETX_IO_VIRT + NETX_OFS_UART2)
+#define NETX_VA_MIIMU    (NETX_IO_VIRT + NETX_OF_MIIMU)
+#define NETX_VA_SPI      (NETX_IO_VIRT + NETX_OFS_SPI)
+#define NETX_VA_I2C      (NETX_IO_VIRT + NETX_OFS_I2C)
+#define NETX_VA_SYSTIME  (NETX_IO_VIRT + NETX_OFS_SYSTIME)
+#define NETX_VA_RTC      (NETX_IO_VIRT + NETX_OFS_RTC)
+#define NETX_VA_EXTBUS   (NETX_IO_VIRT + NETX_OFS_EXTBUS)
+#define NETX_VA_LCD      (NETX_IO_VIRT + NETX_OFS_LCD)
+#define NETX_VA_USB      (NETX_IO_VIRT + NETX_OFS_USB)
+#define NETX_VA_XMAC0    (NETX_IO_VIRT + NETX_OFS_XMAC0)
+#define NETX_VA_XMAC1    (NETX_IO_VIRT + NETX_OFS_XMAC1)
+#define NETX_VA_XMAC2    (NETX_IO_VIRT + NETX_OFS_XMAC2)
+#define NETX_VA_XMAC3    (NETX_IO_VIRT + NETX_OFS_XMAC3)
+#define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no))
+#define NETX_VA_PFIFO    (NETX_IO_VIRT + NETX_OFS_PFIFO)
+#define NETX_VA_XPEC0    (NETX_IO_VIRT + NETX_OFS_XPEC0)
+#define NETX_VA_XPEC1    (NETX_IO_VIRT + NETX_OFS_XPEC1)
+#define NETX_VA_XPEC2    (NETX_IO_VIRT + NETX_OFS_XPEC2)
+#define NETX_VA_XPEC3    (NETX_IO_VIRT + NETX_OFS_XPEC3)
+#define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no))
+#define NETX_VA_VIC      (NETX_IO_VIRT + NETX_OFS_VIC)
+/*********************************
+ * System functions              *
+ *********************************/
+/* Registers */
+#define NETX_SYSTEM_REG(ofs)            __io(NETX_VA_SYSTEM + (ofs))
+#define NETX_SYSTEM_BOO_SR          NETX_SYSTEM_REG(0x00)
+#define NETX_SYSTEM_IOC_CR          NETX_SYSTEM_REG(0x04)
+#define NETX_SYSTEM_IOC_MR          NETX_SYSTEM_REG(0x08)
+/* FIXME: Docs are not consistent */
+#define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x08)
+/* #define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x0c) */
+#define NETX_SYSTEM_PHY_CONTROL     NETX_SYSTEM_REG(0x10)
+#define NETX_SYSTEM_REV             NETX_SYSTEM_REG(0x34)
+#define NETX_SYSTEM_IOC_ACCESS_KEY  NETX_SYSTEM_REG(0x70)
+#define NETX_SYSTEM_WDG_TR          NETX_SYSTEM_REG(0x200)
+#define NETX_SYSTEM_WDG_CTR         NETX_SYSTEM_REG(0x204)
+#define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208)
+#define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c)
+/* Bits */
+#define NETX_SYSTEM_RES_CR_RSTIN         (1<<0)
+#define NETX_SYSTEM_RES_CR_WDG_RES       (1<<1)
+#define NETX_SYSTEM_RES_CR_HOST_RES      (1<<2)
+#define NETX_SYSTEM_RES_CR_FIRMW_RES     (1<<3)
+#define NETX_SYSTEM_RES_CR_XPEC0_RES     (1<<4)
+#define NETX_SYSTEM_RES_CR_XPEC1_RES     (1<<5)
+#define NETX_SYSTEM_RES_CR_XPEC2_RES     (1<<6)
+#define NETX_SYSTEM_RES_CR_XPEC3_RES     (1<<7)
+#define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16)
+#define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17)
+#define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18)
+#define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19)
+#define NETX_SYSTEM_RES_CR_FIRMW_FLG0    (1<<20)
+#define NETX_SYSTEM_RES_CR_FIRMW_FLG1    (1<<21)
+#define NETX_SYSTEM_RES_CR_FIRMW_FLG2    (1<<22)
+#define NETX_SYSTEM_RES_CR_FIRMW_FLG3    (1<<23)
+#define NETX_SYSTEM_RES_CR_FIRMW_RES_EN  (1<<24)
+#define NETX_SYSTEM_RES_CR_RSTOUT        (1<<25)
+#define NETX_SYSTEM_RES_CR_EN_RSTOUT     (1<<26)
+#define PHY_CONTROL_RESET            (1<<31)
+#define PHY_CONTROL_SIM_BYP          (1<<30)
+#define PHY_CONTROL_CLK_XLATIN       (1<<29)
+#define PHY_CONTROL_PHY1_EN          (1<<21)
+#define PHY_CONTROL_PHY1_NP_MSG_CODE
+#define PHY_CONTROL_PHY1_AUTOMDIX    (1<<17)
+#define PHY_CONTROL_PHY1_FIXMODE     (1<<16)
+#define PHY_CONTROL_PHY1_MODE(mode)  (((mode) & 0x7) << 13)
+#define PHY_CONTROL_PHY0_EN          (1<<12)
+#define PHY_CONTROL_PHY0_NP_MSG_CODE
+#define PHY_CONTROL_PHY0_AUTOMDIX    (1<<8)
+#define PHY_CONTROL_PHY0_FIXMODE     (1<<7)
+#define PHY_CONTROL_PHY0_MODE(mode)  (((mode) & 0x7) << 4)
+#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf)
+#define PHY_MODE_10BASE_T_HALF      0
+#define PHY_MODE_10BASE_T_FULL      1
+#define PHY_MODE_100BASE_TX_FX_FULL 2
+#define PHY_MODE_100BASE_TX_FX_HALF 3
+#define PHY_MODE_100BASE_TX_HALF    4
+#define PHY_MODE_REPEATER           5
+#define PHY_MODE_POWER_DOWN         6
+#define PHY_MODE_ALL                7
+/* Bits */
+#define VECT_CNTL_ENABLE               (1 << 5)
+/*******************************
+ * GPIO and timer module       *
+ *******************************/
+/* Registers */
+#define NETX_GPIO_REG(ofs)                     __io(NETX_VA_GPIO + (ofs))
+#define NETX_GPIO_CFG(gpio)                NETX_GPIO_REG(0x0  + ((gpio)<<2))
+#define NETX_GPIO_THRESHOLD_CAPTURE(gpio)  NETX_GPIO_REG(0x40 + ((gpio)<<2))
+#define NETX_GPIO_COUNTER_CTRL(counter)    NETX_GPIO_REG(0x80 + ((counter)<<2))
+#define NETX_GPIO_COUNTER_MAX(counter)     NETX_GPIO_REG(0x94 + ((counter)<<2))
+#define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2))
+#define NETX_GPIO_IRQ_ENABLE               NETX_GPIO_REG(0xbc)
+#define NETX_GPIO_IRQ_DISABLE              NETX_GPIO_REG(0xc0)
+#define NETX_GPIO_SYSTIME_NS_CMP           NETX_GPIO_REG(0xc4)
+#define NETX_GPIO_LINE                     NETX_GPIO_REG(0xc8)
+#define NETX_GPIO_IRQ                      NETX_GPIO_REG(0xd0)
+/* Bits */
+#define NETX_GPIO_CFG_IOCFG_GP_INPUT                 (0x0)
+#define NETX_GPIO_CFG_IOCFG_GP_OUTPUT                (0x1)
+#define NETX_GPIO_CFG_IOCFG_GP_UART                  (0x2)
+#define NETX_GPIO_CFG_INV                            (1<<2)
+#define NETX_GPIO_CFG_MODE_INPUT_READ                (0<<3)
+#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3)
+#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3)
+#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL  (3<<3)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER0             (0<<5)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER1             (1<<5)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER2             (2<<5)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER3             (3<<5)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER4             (4<<5)
+#define NETX_GPIO_CFG_COUNT_REF_SYSTIME              (7<<5)
+#define NETX_GPIO_COUNTER_CTRL_RUN                   (1<<0)
+#define NETX_GPIO_COUNTER_CTRL_SYM                   (1<<1)
+#define NETX_GPIO_COUNTER_CTRL_ONCE                  (1<<2)
+#define NETX_GPIO_COUNTER_CTRL_IRQ_EN                (1<<3)
+#define NETX_GPIO_COUNTER_CTRL_CNT_EVENT             (1<<4)
+#define NETX_GPIO_COUNTER_CTRL_RST_EN                (1<<5)
+#define NETX_GPIO_COUNTER_CTRL_SEL_EVENT             (1<<6)
+#define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */
+#define GPIO_BIT(gpio)                     (1<<(gpio))
+#define COUNTER_BIT(counter)               ((1<<16)<<(counter))
+/*******************************
+ * PIO                         *
+ *******************************/
+/* Registers */
+#define NETX_PIO_REG(ofs)        __io(NETX_VA_PIO + (ofs))
+#define NETX_PIO_INPIO       NETX_PIO_REG(0x0)
+#define NETX_PIO_OUTPIO      NETX_PIO_REG(0x4)
+#define NETX_PIO_OEPIO       NETX_PIO_REG(0x8)
+/*******************************
+ * MII Unit                    *
+ *******************************/
+/* Registers */
+#define NETX_MIIMU           __io(NETX_VA_MIIMU)
+/* Bits */
+#define MIIMU_SNRDY        (1<<0)
+#define MIIMU_PREAMBLE     (1<<1)
+#define MIIMU_OPMODE_WRITE (1<<2)
+#define MIIMU_MDC_PERIOD   (1<<3)
+#define MIIMU_PHY_NRES     (1<<4)
+#define MIIMU_RTA          (1<<5)
+#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6)
+#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11)
+#define MIIMU_DATA(data)   (((data) & 0xffff) << 16)
+/*******************************
+ * xmac / xpec                 *
+ *******************************/
+/* XPEC register offsets relative to NETX_VA_XPEC(no) */
+#define NETX_XPEC_R0_OFS           0x00
+#define NETX_XPEC_R1_OFS           0x04
+#define NETX_XPEC_R2_OFS           0x08
+#define NETX_XPEC_R3_OFS           0x0c
+#define NETX_XPEC_R4_OFS           0x10
+#define NETX_XPEC_R5_OFS           0x14
+#define NETX_XPEC_R6_OFS           0x18
+#define NETX_XPEC_R7_OFS           0x1c
+#define NETX_XPEC_RANGE01_OFS      0x20
+#define NETX_XPEC_RANGE23_OFS      0x24
+#define NETX_XPEC_RANGE45_OFS      0x28
+#define NETX_XPEC_RANGE67_OFS      0x2c
+#define NETX_XPEC_PC_OFS           0x48
+#define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2))
+#define NETX_XPEC_IRQ_OFS          0x8c
+#define NETX_XPEC_SYSTIME_NS_OFS   0x90
+#define NETX_XPEC_FIFO_DATA_OFS    0x94
+#define NETX_XPEC_SYSTIME_S_OFS    0x98
+#define NETX_XPEC_ADC_OFS          0x9c
+#define NETX_XPEC_URX_COUNT_OFS    0x40
+#define NETX_XPEC_UTX_COUNT_OFS    0x44
+#define NETX_XPEC_PC_OFS           0x48
+#define NETX_XPEC_ZERO_OFS         0x4c
+#define NETX_XPEC_STATCFG_OFS      0x50
+#define NETX_XPEC_EC_MASKA_OFS     0x54
+#define NETX_XPEC_EC_MASKB_OFS     0x58
+#define NETX_XPEC_EC_MASK0_OFS     0x5c
+#define NETX_XPEC_EC_MASK8_OFS     0x7c
+#define NETX_XPEC_EC_MASK9_OFS     0x80
+#define NETX_XPEC_XPU_HOLD_PC_OFS  0x100
+#define NETX_XPEC_RAM_START_OFS    0x2000
+/* Bits */
+#define XPU_HOLD_PC (1<<0)
+/* XMAC register offsets relative to NETX_VA_XMAC(no) */
+#define NETX_XMAC_RPU_PROGRAM_START_OFS       0x000
+#define NETX_XMAC_RPU_PROGRAM_END_OFS         0x3ff
+#define NETX_XMAC_TPU_PROGRAM_START_OFS       0x400
+#define NETX_XMAC_TPU_PROGRAM_END_OFS         0x7ff
+#define NETX_XMAC_RPU_HOLD_PC_OFS             0xa00
+#define NETX_XMAC_TPU_HOLD_PC_OFS             0xa04
+#define NETX_XMAC_STATUS_SHARED0_OFS          0x840
+#define NETX_XMAC_CONFIG_SHARED0_OFS          0x844
+#define NETX_XMAC_STATUS_SHARED1_OFS          0x848
+#define NETX_XMAC_CONFIG_SHARED1_OFS          0x84c
+#define NETX_XMAC_STATUS_SHARED2_OFS          0x850
+#define NETX_XMAC_CONFIG_SHARED2_OFS          0x854
+#define NETX_XMAC_STATUS_SHARED3_OFS          0x858
+#define NETX_XMAC_CONFIG_SHARED3_OFS          0x85c
+#define RPU_HOLD_PC            (1<<15)
+#define TPU_HOLD_PC            (1<<15)
+/*******************************
+ * Pointer FIFO                *
+ *******************************/
+/* Registers */
+#define NETX_PFIFO_REG(ofs)               __io(NETX_VA_PFIFO + (ofs))
+#define NETX_PFIFO_BASE(pfifo)        NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
+#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
+#define NETX_PFIFO_RESET              NETX_PFIFO_REG(0x100)
+#define NETX_PFIFO_FULL               NETX_PFIFO_REG(0x104)
+#define NETX_PFIFO_EMPTY              NETX_PFIFO_REG(0x108)
+#define NETX_PFIFO_OVEFLOW            NETX_PFIFO_REG(0x10c)
+#define NETX_PFIFO_UNDERRUN           NETX_PFIFO_REG(0x110)
+#define NETX_PFIFO_FILL_LEVEL(pfifo)  NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
+#define NETX_PFIFO_XPEC_ISR(xpec)     NETX_PFIFO_REG(0x400 + ((xpec) << 2))
+/*******************************
+ * Dual Port Memory            *
+ *******************************/
+/* Registers */
+#define NETX_DPMAS_REG(ofs)               __io(NETX_VA_DPMAS + (ofs))
+#define NETX_DPMAS_SYS_STAT           NETX_DPMAS_REG(0x4d8)
+#define NETX_DPMAS_INT_STAT           NETX_DPMAS_REG(0x4e0)
+#define NETX_DPMAS_INT_EN             NETX_DPMAS_REG(0x4f0)
+#define NETX_DPMAS_IF_CONF0           NETX_DPMAS_REG(0x608)
+#define NETX_DPMAS_IF_CONF1           NETX_DPMAS_REG(0x60c)
+#define NETX_DPMAS_EXT_CONFIG(cs)     NETX_DPMAS_REG(0x610 + 4 * (cs))
+#define NETX_DPMAS_IO_MODE0           NETX_DPMAS_REG(0x620) /* I/O 32..63 */
+#define NETX_DPMAS_DRV_EN0            NETX_DPMAS_REG(0x624)
+#define NETX_DPMAS_DATA0              NETX_DPMAS_REG(0x628)
+#define NETX_DPMAS_IO_MODE1           NETX_DPMAS_REG(0x630) /* I/O 64..84 */
+#define NETX_DPMAS_DRV_EN1            NETX_DPMAS_REG(0x634)
+#define NETX_DPMAS_DATA1              NETX_DPMAS_REG(0x638)
+/* Bits */
+#define NETX_DPMAS_INT_EN_GLB_EN         (1<<31)
+#define NETX_DPMAS_INT_EN_MEM_LCK        (1<<30)
+#define NETX_DPMAS_INT_EN_WDG            (1<<29)
+#define NETX_DPMAS_INT_EN_PIO72          (1<<28)
+#define NETX_DPMAS_INT_EN_PIO47          (1<<27)
+#define NETX_DPMAS_INT_EN_PIO40          (1<<26)
+#define NETX_DPMAS_INT_EN_PIO36          (1<<25)
+#define NETX_DPMAS_INT_EN_PIO35          (1<<24)
+#define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28)
+#define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS  (1<<28)
+#define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT  (2<<28)
+#define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28)
+#define NETX_DPMAS_IF_CONF0_HIF_IO       (4<<28)
+#define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP  (1<<14)
+#define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD  (2<<14)
+#define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14)
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26)
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27)
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28)
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29)
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30)
+#define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29)
+#define NETX_EXT_CONFIG_TADRHOLD(x)  (((x) & 0x7) << 26)
+#define NETX_EXT_CONFIG_TCSON(x)     (((x) & 0x7) << 23)
+#define NETX_EXT_CONFIG_TRDON(x)     (((x) & 0x7) << 20)
+#define NETX_EXT_CONFIG_TWRON(x)     (((x) & 0x7)  << 17)
+#define NETX_EXT_CONFIG_TWROFF(x)    (((x) & 0x1f) << 12)
+#define NETX_EXT_CONFIG_TRDWRCYC(x)  (((x) & 0x1f) << 7)
+#define NETX_EXT_CONFIG_WAIT_POL     (1<<6)
+#define NETX_EXT_CONFIG_WAIT_EN      (1<<5)
+#define NETX_EXT_CONFIG_NRD_MODE     (1<<4)
+#define NETX_EXT_CONFIG_DS_MODE      (1<<3)
+#define NETX_EXT_CONFIG_NWR_MODE     (1<<2)
+#define NETX_EXT_CONFIG_16BIT        (1<<1)
+#define NETX_EXT_CONFIG_CS_ENABLE    (1<<0)
+#define NETX_DPMAS_IO_MODE0_WRL   (1<<13)
+#define NETX_DPMAS_IO_MODE0_WAIT  (1<<14)
+#define NETX_DPMAS_IO_MODE0_READY (1<<15)
+#define NETX_DPMAS_IO_MODE0_CS0   (1<<19)
+#define NETX_DPMAS_IO_MODE0_EXTRD (1<<20)
+#define NETX_DPMAS_IO_MODE1_CS2           (1<<15)
+#define NETX_DPMAS_IO_MODE1_CS1           (1<<16)
+#define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR   (0<<30)
+#define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30)
+#define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30)
+#define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36  (3<<30)
+/*******************************
+ * I2C                         *
+ *******************************/
+#define NETX_I2C_REG(ofs)       __io(NETX_VA_I2C, (ofs))
+#define NETX_I2C_CTRL   NETX_I2C_REG(0x0)
+#define NETX_I2C_DATA   NETX_I2C_REG(0x4)
+#endif /* __ASM_ARCH_NETX_REGS_H */
diff --git a/include/asm-arm/arch-netx/param.h b/include/asm-arm/arch-netx/param.h
new file mode 100644
index 000000000000..7a80c26178a8
--- /dev/null
+++ b/include/asm-arm/arch-netx/param.h
@@ -0,0 +1,18 @@
+/*
+ *  linux/include/asm-arm/arch-netx/param.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-netx/pfifo.h b/include/asm-arm/arch-netx/pfifo.h
new file mode 100644
index 000000000000..4af2ee4a32c1
--- /dev/null
+++ b/include/asm-arm/arch-netx/pfifo.h
@@ -0,0 +1,54 @@
+/*
+ * include/asm-arm/arch-netx/pfifo.h
+ *
+ * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef ASM_ARCH_PFIFO_H
+#define ASM_ARCH_PFIFO_H
+static inline int pfifo_push(int no, unsigned int pointer)
+{
+        writel(pointer, NETX_PFIFO_BASE(no));
+        return 0;
+}
+static inline unsigned int pfifo_pop(int no)
+{
+        return readl(NETX_PFIFO_BASE(no));
+}
+static inline int pfifo_fill_level(int no)
+{
+        return readl(NETX_PFIFO_FILL_LEVEL(no));
+}
+static inline int pfifo_full(int no)
+{
+        return readl(NETX_PFIFO_FULL) & (1<<no) ? 1 : 0;
+}
+static inline int pfifo_empty(int no)
+{
+        return readl(NETX_PFIFO_EMPTY) & (1<<no) ? 1 : 0;
+}
+int pfifo_request(unsigned int pfifo_mask);
+void pfifo_free(unsigned int pfifo_mask);
+#endif /* ASM_ARCH_PFIFO_H */
diff --git a/include/asm-arm/arch-netx/system.h b/include/asm-arm/arch-netx/system.h
new file mode 100644
index 000000000000..52adf368d765
--- /dev/null
+++ b/include/asm-arm/arch-netx/system.h
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-netx/system.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include "netx-regs.h"
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
+               NETX_SYSTEM_RES_CR);
+}
+#endif
diff --git a/include/asm-arm/arch-netx/timex.h b/include/asm-arm/arch-netx/timex.h
new file mode 100644
index 000000000000..7fdb42da0b40
--- /dev/null
+++ b/include/asm-arm/arch-netx/timex.h
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-netx/timex.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define CLOCK_TICK_RATE 100000000
diff --git a/include/asm-arm/arch-netx/uncompress.h b/include/asm-arm/arch-netx/uncompress.h
new file mode 100644
index 000000000000..f89434547102
--- /dev/null
+++ b/include/asm-arm/arch-netx/uncompress.h
@@ -0,0 +1,76 @@
+/*
+ * include/asm-arm/arch-netx/uncompress.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+#define REG(x) (*(volatile unsigned long *)(x))
+#define UART1_BASE 0x100a00
+#define UART2_BASE 0x100a80
+#define UART_DR 0x0
+#define UART_CR 0x14
+#define CR_UART_EN (1<<0)
+#define UART_FR 0x18
+#define FR_BUSY (1<<3)
+#define FR_TXFF (1<<5)
+static void putc(char c)
+{
+        unsigned long base;
+        if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
+                base = UART1_BASE;
+        else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
+                base = UART2_BASE;
+        else
+                return;
+        while (REG(base + UART_FR) & FR_TXFF);
+        REG(base + UART_DR) = c;
+}
+static inline void flush(void)
+{
+        unsigned long base;
+        if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
+                base = UART1_BASE;
+        else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
+                base = UART2_BASE;
+        else
+                return;
+        while (REG(base + UART_FR) & FR_BUSY);
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-netx/vmalloc.h b/include/asm-arm/arch-netx/vmalloc.h
new file mode 100644
index 000000000000..da2da5a595da
--- /dev/null
+++ b/include/asm-arm/arch-netx/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-netx/vmalloc.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-netx/xc.h b/include/asm-arm/arch-netx/xc.h
new file mode 100644
index 000000000000..659af19512a9
--- /dev/null
+++ b/include/asm-arm/arch-netx/xc.h
@@ -0,0 +1,42 @@
+/*
+ *  linux/include/asm-arm/arch-netx/xc.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_XC_H
+#define __ASM_ARCH_XC_H
+struct xc {
+        int no;
+        unsigned int type;
+        unsigned int version;
+        void __iomem *xpec_base;
+        void __iomem *xmac_base;
+        void __iomem *sram_base;
+        int irq;
+        struct device *dev;
+};
+int xc_reset(struct xc *x);
+int xc_stop(struct xc* x);
+int xc_start(struct xc *x);
+int xc_running(struct xc *x);
+int xc_request_firmware(struct xc* x);
+struct xc* request_xc(int xcno, struct device *dev);
+void free_xc(struct xc *x);
+#endif /* __ASM_ARCH_XC_H */
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
index 6d6240a4681c..dfdbf06fd646 100644
--- a/include/asm-arm/arch-omap/board.h
+++ b/include/asm-arm/arch-omap/board.h
@@ -10,7 +10,6 @@
 #ifndef _OMAP_BOARD_H
 #define _OMAP_BOARD_H
-#include <linux/config.h>
 #include <linux/types.h>
 /* Different peripheral ids */
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 7909b729826c..c7d9e857795d 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -37,7 +37,6 @@
 #define __ASM_ARCH_OMAP_HARDWARE_H
 #include <asm/sizes.h>
-#include <linux/config.h>
 #ifndef __ASSEMBLER__
 #include <asm/types.h>
 #include <asm/arch/cpu.h>
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index b726acfcab14..78f68e6a4f0c 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -44,7 +44,6 @@
 */
 #define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 /*
 * ----------------------------------------------------------------------------
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
index 67970d1a2020..ac2bfa433f06 100644
--- a/include/asm-arm/arch-omap/system.h
+++ b/include/asm-arm/arch-omap/system.h
@@ -4,7 +4,6 @@
 */
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <linux/config.h>
 #include <linux/clk.h>
 #include <asm/mach-types.h>
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
index ca2c8bec82e7..aca0adfef1b8 100644
--- a/include/asm-arm/arch-omap/uncompress.h
+++ b/include/asm-arm/arch-omap/uncompress.h
@@ -17,7 +17,6 @@
 * kind, whether express or implied.
 */
-#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/serial_reg.h>
 #include <asm/arch/serial.h>
diff --git a/include/asm-arm/arch-pnx4008/clock.h b/include/asm-arm/arch-pnx4008/clock.h
new file mode 100644
index 000000000000..91ae0030fdf2
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/clock.h
@@ -0,0 +1,61 @@
+/*
+ * include/asm-arm/arch-pnx4008/clock.h
+ *
+ * Clock control driver for PNX4008 - header file
+ *
+ * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __PNX4008_CLOCK_H__
+#define __PNX4008_CLOCK_H__
+struct module;
+struct clk;
+#define PWRMAN_VA_BASE          IO_ADDRESS(PNX4008_PWRMAN_BASE)
+#define HCLKDIVCTRL_REG         (PWRMAN_VA_BASE + 0x40)
+#define PWRCTRL_REG             (PWRMAN_VA_BASE + 0x44)
+#define PLLCTRL_REG             (PWRMAN_VA_BASE + 0x48)
+#define OSC13CTRL_REG           (PWRMAN_VA_BASE + 0x4c)
+#define SYSCLKCTRL_REG          (PWRMAN_VA_BASE + 0x50)
+#define HCLKPLLCTRL_REG         (PWRMAN_VA_BASE + 0x58)
+#define USBCTRL_REG             (PWRMAN_VA_BASE + 0x64)
+#define SDRAMCLKCTRL_REG        (PWRMAN_VA_BASE + 0x68)
+#define MSCTRL_REG              (PWRMAN_VA_BASE + 0x80)
+#define BTCLKCTRL               (PWRMAN_VA_BASE + 0x84)
+#define DUMCLKCTRL_REG          (PWRMAN_VA_BASE + 0x90)
+#define I2CCLKCTRL_REG          (PWRMAN_VA_BASE + 0xac)
+#define KEYCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb0)
+#define TSCLKCTRL_REG           (PWRMAN_VA_BASE + 0xb4)
+#define PWMCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb8)
+#define SPICTRL_REG             (PWRMAN_VA_BASE + 0xc4)
+#define FLASHCLKCTRL_REG        (PWRMAN_VA_BASE + 0xc8)
+#define UART3CLK_REG            (PWRMAN_VA_BASE + 0xd0)
+#define UARTCLKCTRL_REG         (PWRMAN_VA_BASE + 0xe4)
+#define DMACLKCTRL_REG          (PWRMAN_VA_BASE + 0xe8)
+#define AUTOCLK_CTRL            (PWRMAN_VA_BASE + 0xec)
+#define JPEGCLKCTRL_REG         (PWRMAN_VA_BASE + 0xfc)
+#define AUDIOCONFIG_VA_BASE     IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
+#define DSPPLLCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x60)
+#define DSPCLKCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x64)
+#define AUDIOCLKCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x68)
+#define AUDIOPLLCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x6C)
+#define USB_OTG_CLKCTRL_REG     IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
+#define VFP9CLKCTRL_REG         IO_ADDRESS(PNX4008_DEBUG_BASE)
+#define CLK_RATE_13MHZ 13000
+#define CLK_RATE_1MHZ 1000
+#define CLK_RATE_208MHZ 208000
+#define CLK_RATE_48MHZ 48000
+#define CLK_RATE_32KHZ 32
+#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
+#endif
diff --git a/include/asm-arm/arch-pnx4008/debug-macro.S b/include/asm-arm/arch-pnx4008/debug-macro.S
new file mode 100644
index 000000000000..67d18a203d23
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/debug-macro.S
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-pnx4008/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                mov     \rx, #0x00090000
+                addeq   \rx, \rx, #0x40000000
+                addne   \rx, \rx, #0xf4000000
+                .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-pnx4008/dma.h b/include/asm-arm/arch-pnx4008/dma.h
new file mode 100644
index 000000000000..3aee1204795b
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/dma.h
@@ -0,0 +1,162 @@
+/*
+ *  linux/include/asm-arm/arch-pnx4008/dma.h
+ *
+ *  PNX4008 DMA header file
+ *
+ *  Author:     Vitaly Wool
+ *  Copyright:  MontaVista Software Inc. (c) 2005
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+#include "platform.h"
+#define MAX_DMA_ADDRESS         0xffffffff
+#define MAX_DMA_CHANNELS        8
+#define DMAC_BASE               IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
+#define DMAC_INT_STAT           (DMAC_BASE + 0x0000)
+#define DMAC_INT_TC_STAT        (DMAC_BASE + 0x0004)
+#define DMAC_INT_TC_CLEAR       (DMAC_BASE + 0x0008)
+#define DMAC_INT_ERR_STAT       (DMAC_BASE + 0x000c)
+#define DMAC_INT_ERR_CLEAR      (DMAC_BASE + 0x0010)
+#define DMAC_SOFT_SREQ          (DMAC_BASE + 0x0024)
+#define DMAC_CONFIG             (DMAC_BASE + 0x0030)
+#define DMAC_Cx_SRC_ADDR(c)     (DMAC_BASE + 0x0100 + (c) * 0x20)
+#define DMAC_Cx_DEST_ADDR(c)    (DMAC_BASE + 0x0104 + (c) * 0x20)
+#define DMAC_Cx_LLI(c)          (DMAC_BASE + 0x0108 + (c) * 0x20)
+#define DMAC_Cx_CONTROL(c)      (DMAC_BASE + 0x010c + (c) * 0x20)
+#define DMAC_Cx_CONFIG(c)       (DMAC_BASE + 0x0110 + (c) * 0x20)
+enum {
+        WIDTH_BYTE = 0,
+        WIDTH_HWORD,
+        WIDTH_WORD
+};
+enum {
+        FC_MEM2MEM_DMA,
+        FC_MEM2PER_DMA,
+        FC_PER2MEM_DMA,
+        FC_PER2PER_DMA,
+        FC_PER2PER_DPER,
+        FC_MEM2PER_PER,
+        FC_PER2MEM_PER,
+        FC_PER2PER_SPER
+};
+enum {
+        DMA_INT_UNKNOWN = 0,
+        DMA_ERR_INT = 1,
+        DMA_TC_INT = 2,
+};
+enum {
+        DMA_BUFFER_ALLOCATED = 1,
+        DMA_HAS_LL = 2,
+};
+enum {
+        PER_CAM_DMA_1 = 0,
+        PER_NDF_FLASH = 1,
+        PER_MBX_SLAVE_FIFO = 2,
+        PER_SPI2_REC_XMIT = 3,
+        PER_MS_SD_RX_XMIT = 4,
+        PER_HS_UART_1_XMIT = 5,
+        PER_HS_UART_1_RX = 6,
+        PER_HS_UART_2_XMIT = 7,
+        PER_HS_UART_2_RX = 8,
+        PER_HS_UART_7_XMIT = 9,
+        PER_HS_UART_7_RX = 10,
+        PER_SPI1_REC_XMIT = 11,
+        PER_MLC_NDF_SREC = 12,
+        PER_CAM_DMA_2 = 13,
+        PER_PRNG_INFIFO = 14,
+        PER_PRNG_OUTFIFO = 15,
+};
+struct pnx4008_dma_ch_ctrl {
+        int tc_mask;
+        int cacheable;
+        int bufferable;
+        int priv_mode;
+        int di;
+        int si;
+        int dest_ahb1;
+        int src_ahb1;
+        int dwidth;
+        int swidth;
+        int dbsize;
+        int sbsize;
+        int tr_size;
+};
+struct pnx4008_dma_ch_config {
+        int halt;
+        int active;
+        int lock;
+        int itc;
+        int ie;
+        int flow_cntrl;
+        int dest_per;
+        int src_per;
+};
+struct pnx4008_dma_ll {
+        unsigned long src_addr;
+        unsigned long dest_addr;
+        u32 next_dma;
+        unsigned long ch_ctrl;
+        struct pnx4008_dma_ll *next;
+        int flags;
+        void *alloc_data;
+        int (*free) (void *);
+};
+struct pnx4008_dma_config {
+        int is_ll;
+        unsigned long src_addr;
+        unsigned long dest_addr;
+        unsigned long ch_ctrl;
+        unsigned long ch_cfg;
+        struct pnx4008_dma_ll *ll;
+        u32 ll_dma;
+        int flags;
+        void *alloc_data;
+        int (*free) (void *);
+};
+extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
+extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
+extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
+extern int pnx4008_request_channel(char *, int,
+                                   void (*)(int, int, void *, struct pt_regs *),
+                                   void *);
+extern void pnx4008_free_channel(int);
+extern int pnx4008_config_dma(int, int, int);
+extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
+                                    unsigned long *);
+extern int pnx4008_dma_parse_control(unsigned long,
+                                     struct pnx4008_dma_ch_ctrl *);
+extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
+                                   unsigned long *);
+extern int pnx4008_dma_parse_config(unsigned long,
+                                    struct pnx4008_dma_ch_config *);
+extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
+extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
+extern int pnx4008_dma_ch_enable(int);
+extern int pnx4008_dma_ch_disable(int);
+extern int pnx4008_dma_ch_enabled(int);
+extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
+                                         struct pnx4008_dma_ch_ctrl *);
+extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
+                                       struct pnx4008_dma_ch_ctrl *);
+#endif                          /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-pnx4008/entry-macro.S b/include/asm-arm/arch-pnx4008/entry-macro.S
new file mode 100644
index 000000000000..c1c198e3680b
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/entry-macro.S
@@ -0,0 +1,121 @@
+/*
+ * include/asm-arm/arch-pnx4008/entry-macro.S
+ *
+ * Low-level IRQ helper macros for PNX4008-based platforms
+ *
+ * 2005-2006 (c) MontaVista Software, Inc.
+ * Author: Vitaly Wool <vwool@ru.mvista.com>
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include "platform.h"
+#define IO_BASE         0xF0000000
+#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
+#define INTRC_MASK                      0x00
+#define INTRC_RAW_STAT                  0x04
+#define INTRC_STAT                      0x08
+#define INTRC_POLAR                     0x0C
+#define INTRC_ACT_TYPE                  0x10
+#define INTRC_TYPE                      0x14
+#define SIC1_BASE_INT   32
+#define SIC2_BASE_INT   64
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+/* decode the MIC interrupt numbers */
+                ldr     \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
+                ldr     \irqstat, [\base, #INTRC_STAT]
+                cmp     \irqstat,#1<<16
+                movhs   \irqnr,#16
+                movlo   \irqnr,#0
+                movhs   \irqstat,\irqstat,lsr#16
+                cmp     \irqstat,#1<<8
+                addhs   \irqnr,\irqnr,#8
+                movhs   \irqstat,\irqstat,lsr#8
+                cmp     \irqstat,#1<<4
+                addhs   \irqnr,\irqnr,#4
+                movhs   \irqstat,\irqstat,lsr#4
+                cmp     \irqstat,#1<<2
+                addhs   \irqnr,\irqnr,#2
+                movhs   \irqstat,\irqstat,lsr#2
+                cmp     \irqstat,#1<<1
+                addhs   \irqnr,\irqnr,#1
+/* was there an interrupt ? if not then drop out with EQ status */
+                teq     \irqstat,#0
+                beq     1003f
+/* and now check for extended IRQ reasons */
+                cmp     \irqnr,#1
+                bls     1003f
+                cmp     \irqnr,#30
+                blo     1002f
+/* IRQ 31,30  : High priority cascade IRQ handle */
+/* read the correct SIC */
+/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
+/* set the base IRQ number */
+                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
+                moveq  \irqnr,#SIC1_BASE_INT
+                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
+                movne   \irqnr,#SIC2_BASE_INT
+                ldr     \irqstat, [\base, #INTRC_STAT]
+                ldr     \tmp,     [\base, #INTRC_TYPE]
+/* and with inverted mask : low priority interrupts  */
+                and     \irqstat,\irqstat,\tmp
+                b       1004f
+1003:
+/* IRQ 1,0  : Low priority cascade IRQ handle */
+/* read the correct SIC */
+/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
+/* read the correct SIC */
+/* set the base IRQ number  */
+                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
+                movne   \irqnr,#SIC1_BASE_INT
+                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
+                moveq   \irqnr,#SIC2_BASE_INT
+                ldr     \irqstat, [\base, #INTRC_STAT]
+                ldr     \tmp,     [\base, #INTRC_TYPE]
+/* and with inverted mask : low priority interrupts  */
+                bic     \irqstat,\irqstat,\tmp
+1004:
+                cmp     \irqstat,#1<<16
+                addhs   \irqnr,\irqnr,#16
+                movhs   \irqstat,\irqstat,lsr#16
+                cmp     \irqstat,#1<<8
+                addhs   \irqnr,\irqnr,#8
+                movhs   \irqstat,\irqstat,lsr#8
+                cmp     \irqstat,#1<<4
+                addhs   \irqnr,\irqnr,#4
+                movhs   \irqstat,\irqstat,lsr#4
+                cmp     \irqstat,#1<<2
+                addhs   \irqnr,\irqnr,#2
+                movhs   \irqstat,\irqstat,lsr#2
+                cmp     \irqstat,#1<<1
+                addhs   \irqnr,\irqnr,#1
+/* is irqstat not zero */
+1002:
+/* we assert that irqstat is not equal to zero and return ne status if true*/
+                teq     \irqstat,#0
+1003:
+                .endm
+                .macro  irq_prio_table
+                .endm
diff --git a/include/asm-arm/arch-pnx4008/gpio.h b/include/asm-arm/arch-pnx4008/gpio.h
new file mode 100644
index 000000000000..d01bf83d55c2
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/gpio.h
@@ -0,0 +1,241 @@
+/*
+ * include/asm-arm/arch-pnx4008/gpio.h
+ *
+ * PNX4008 GPIO driver - header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
+ * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef _PNX4008_GPIO_H_
+#define _PNX4008_GPIO_H_
+/* Block numbers */
+#define GPIO_IN         (0)
+#define GPIO_OUT                (0x100)
+#define GPIO_BID                (0x200)
+#define GPIO_RAM                (0x300)
+#define GPIO_MUX                (0x400)
+#define GPIO_TYPE_MASK(K) ((K) & 0x700)
+/* INPUT GPIOs */
+/* GPI */
+#define GPI_00          (GPIO_IN | 0)
+#define GPI_01          (GPIO_IN | 1)
+#define GPI_02          (GPIO_IN | 2)
+#define GPI_03          (GPIO_IN | 3)
+#define GPI_04          (GPIO_IN | 4)
+#define GPI_05          (GPIO_IN | 5)
+#define GPI_06          (GPIO_IN | 6)
+#define GPI_07          (GPIO_IN | 7)
+#define GPI_08          (GPIO_IN | 8)
+#define GPI_09          (GPIO_IN | 9)
+#define U1_RX           (GPIO_IN | 15)
+#define U2_HTCS         (GPIO_IN | 16)
+#define U2_RX           (GPIO_IN | 17)
+#define U3_RX           (GPIO_IN | 18)
+#define U4_RX           (GPIO_IN | 19)
+#define U5_RX           (GPIO_IN | 20)
+#define U6_IRRX         (GPIO_IN | 21)
+#define U7_HCTS         (GPIO_IN | 22)
+#define U7_RX           (GPIO_IN | 23)
+/* MISC IN */
+#define SPI1_DATIN      (GPIO_IN | 25)
+#define DISP_SYNC       (GPIO_IN | 26)
+#define SPI2_DATIN      (GPIO_IN | 27)
+#define GPI_11          (GPIO_IN | 28)
+#define GPIO_IN_MASK   0x1eff83ff
+/* OUTPUT GPIOs */
+/* GPO */
+#define GPO_00          (GPIO_OUT | 0)
+#define GPO_01          (GPIO_OUT | 1)
+#define GPO_02          (GPIO_OUT | 2)
+#define GPO_03          (GPIO_OUT | 3)
+#define GPO_04          (GPIO_OUT | 4)
+#define GPO_05          (GPIO_OUT | 5)
+#define GPO_06          (GPIO_OUT | 6)
+#define GPO_07          (GPIO_OUT | 7)
+#define GPO_08          (GPIO_OUT | 8)
+#define GPO_09          (GPIO_OUT | 9)
+#define GPO_10          (GPIO_OUT | 10)
+#define GPO_11          (GPIO_OUT | 11)
+#define GPO_12          (GPIO_OUT | 12)
+#define GPO_13          (GPIO_OUT | 13)
+#define GPO_14          (GPIO_OUT | 14)
+#define GPO_15          (GPIO_OUT | 15)
+#define GPO_16          (GPIO_OUT | 16)
+#define GPO_17          (GPIO_OUT | 17)
+#define GPO_18          (GPIO_OUT | 18)
+#define GPO_19          (GPIO_OUT | 19)
+#define GPO_20          (GPIO_OUT | 20)
+#define GPO_21          (GPIO_OUT | 21)
+#define GPO_22          (GPIO_OUT | 22)
+#define GPO_23          (GPIO_OUT | 23)
+#define GPIO_OUT_MASK   0xffffff
+/* BIDIRECTIONAL GPIOs */
+/* RAM pins */
+#define RAM_D19         (GPIO_RAM | 0)
+#define RAM_D20         (GPIO_RAM | 1)
+#define RAM_D21         (GPIO_RAM | 2)
+#define RAM_D22         (GPIO_RAM | 3)
+#define RAM_D23         (GPIO_RAM | 4)
+#define RAM_D24         (GPIO_RAM | 5)
+#define RAM_D25         (GPIO_RAM | 6)
+#define RAM_D26         (GPIO_RAM | 7)
+#define RAM_D27         (GPIO_RAM | 8)
+#define RAM_D28         (GPIO_RAM | 9)
+#define RAM_D29         (GPIO_RAM | 10)
+#define RAM_D30         (GPIO_RAM | 11)
+#define RAM_D31         (GPIO_RAM | 12)
+#define GPIO_RAM_MASK   0x1fff
+/* I/O pins */
+#define GPIO_00         (GPIO_BID | 25)
+#define GPIO_01         (GPIO_BID | 26)
+#define GPIO_02         (GPIO_BID | 27)
+#define GPIO_03         (GPIO_BID | 28)
+#define GPIO_04         (GPIO_BID | 29)
+#define GPIO_05         (GPIO_BID | 30)
+#define GPIO_BID_MASK   0x7e000000
+/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
+#define GPIO_SDRAM_SEL  (GPIO_MUX | 3)
+#define GPIO_MUX_MASK   0x8
+/* Extraction/assembly macros */
+#define GPIO_BIT_MASK(K) ((K) & 0x1F)
+#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
+#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
+#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
+#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
+#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
+#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
+/* Start Enable Pin Interrupts - table 58 page 66 */
+#define SE_PIN_BASE_INT   32
+#define SE_U7_RX_INT            63
+#define SE_U7_HCTS_INT          62
+#define SE_BT_CLKREQ_INT        61
+#define SE_U6_IRRX_INT          60
+/*59 unused*/
+#define SE_U5_RX_INT            58
+#define SE_GPI_11_INT           57
+#define SE_U3_RX_INT            56
+#define SE_U2_HCTS_INT          55
+#define SE_U2_RX_INT            54
+#define SE_U1_RX_INT            53
+#define SE_DISP_SYNC_INT        52
+/*51 unused*/
+#define SE_SDIO_INT_N           50
+#define SE_MSDIO_START_INT      49
+#define SE_GPI_06_INT           48
+#define SE_GPI_05_INT           47
+#define SE_GPI_04_INT           46
+#define SE_GPI_03_INT           45
+#define SE_GPI_02_INT           44
+#define SE_GPI_01_INT           43
+#define SE_GPI_00_INT           42
+#define SE_SYSCLKEN_PIN_INT     41
+#define SE_SPI1_DATAIN_INT      40
+#define SE_GPI_07_INT           39
+#define SE_SPI2_DATAIN_INT      38
+#define SE_GPI_10_INT           37
+#define SE_GPI_09_INT           36
+#define SE_GPI_08_INT           35
+/*34-32 unused*/
+/* Start Enable Internal Interrupts - table 57 page 65 */
+#define SE_INT_BASE_INT   0
+#define SE_TS_IRQ               31
+#define SE_TS_P_INT             30
+#define SE_TS_AUX_INT           29
+/*27-28 unused*/
+#define SE_USB_AHB_NEED_CLK_INT 26
+#define SE_MSTIMER_INT          25
+#define SE_RTC_INT              24
+#define SE_USB_NEED_CLK_INT     23
+#define SE_USB_INT              22
+#define SE_USB_I2C_INT          21
+#define SE_USB_OTG_TIMER_INT    20
+#define SE_USB_OTG_ATX_INT_N    19
+/*18 unused*/
+#define SE_DSP_GPIO4_INT        17
+#define SE_KEY_IRQ              16
+#define SE_DSP_SLAVEPORT_INT    15
+#define SE_DSP_GPIO1_INT        14
+#define SE_DSP_GPIO0_INT        13
+#define SE_DSP_AHB_INT          12
+/*11-6 unused*/
+#define SE_GPIO_05_INT          5
+#define SE_GPIO_04_INT          4
+#define SE_GPIO_03_INT          3
+#define SE_GPIO_02_INT          2
+#define SE_GPIO_01_INT          1
+#define SE_GPIO_00_INT          0
+#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
+#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
+extern int pnx4008_gpio_register_pin(unsigned short pin);
+extern int pnx4008_gpio_unregister_pin(unsigned short pin);
+extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
+extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
+extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
+extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
+extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
+extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
+static inline void start_int_umask(u8 irq)
+{
+        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
+                     START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
+}
+static inline void start_int_mask(u8 irq)
+{
+        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
+                     ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
+}
+static inline void start_int_ack(u8 irq)
+{
+        __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
+}
+static inline void start_int_set_falling_edge(u8 irq)
+{
+        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
+                     ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
+}
+static inline void start_int_set_rising_edge(u8 irq)
+{
+        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
+                     START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
+}
+#endif                          /* _PNX4008_GPIO_H_ */
diff --git a/include/asm-arm/arch-pnx4008/hardware.h b/include/asm-arm/arch-pnx4008/hardware.h
new file mode 100644
index 000000000000..a4410397a921
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/hardware.h
@@ -0,0 +1,32 @@
+/*
+ * linux/include/asm-arm/arch-pnx4008/hardware.h
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <asm/sizes.h>
+#include <asm/arch/platform.h>
+/* Start of virtual addresses for IO devices */
+#define IO_BASE         0xF0000000
+/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
+#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
+#endif
diff --git a/include/asm-arm/arch-pnx4008/io.h b/include/asm-arm/arch-pnx4008/io.h
new file mode 100644
index 000000000000..29ee43955c52
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/io.h
@@ -0,0 +1,21 @@
+/*
+ *  include/asm-arm/arch-pnx4008/io.h
+ *
+ * Author: Dmitry Chigirev <chigirev@ru.mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-pnx4008/irq.h b/include/asm-arm/arch-pnx4008/irq.h
new file mode 100644
index 000000000000..fabff5dc337f
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/irq.h
@@ -0,0 +1,42 @@
+/*
+ * include/asm-arm/arch-pnx4008/irq.h
+ *
+ * PNX4008 IRQ controller driver - header file
+ * this one is used in entry-arnv.S as well so it cannot contain C code
+ *
+ * Copyright (c) 2005 Philips Semiconductors
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef __PNX4008_IRQ_H__
+#define __PNX4008_IRQ_H__
+#define MIC_VA_BASE             IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
+#define SIC1_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
+#define SIC2_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
+/* Manual: Chapter 20, page 195 */
+#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
+#define INTC_ER(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
+#define INTC_RSR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
+#define INTC_SR(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
+#define INTC_APR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
+#define INTC_ATR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
+#define INTC_ITR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
+#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
+#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
+extern void __init pnx4008_init_irq(void);
+#endif /* __PNX4008_IRQ_H__ */
diff --git a/include/asm-arm/arch-pnx4008/irqs.h b/include/asm-arm/arch-pnx4008/irqs.h
new file mode 100644
index 000000000000..13ec7ed0f501
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/irqs.h
@@ -0,0 +1,215 @@
+/*
+ * include/asm-arm/arch-pnx4008/irqs.h
+ *
+ * PNX4008 IRQ controller driver - header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __PNX4008_IRQS_h__
+#define __PNX4008_IRQS_h__
+#define NR_IRQS         96
+/*Manual: table 259, page 199*/
+/*SUB2 Interrupt Routing (SIC2)*/
+#define SIC2_BASE_INT   64
+#define CLK_SWITCH_ARM_INT 95   /*manual: Clkswitch ARM  */
+#define CLK_SWITCH_DSP_INT 94   /*manual: ClkSwitch DSP  */
+#define CLK_SWITCH_AUD_INT 93   /*manual: Clkswitch AUD  */
+#define GPI_06_INT         92
+#define GPI_05_INT         91
+#define GPI_04_INT         90
+#define GPI_03_INT         89
+#define GPI_02_INT         88
+#define GPI_01_INT         87
+#define GPI_00_INT         86
+#define BT_CLKREQ_INT      85
+#define SPI1_DATIN_INT     84
+#define U5_RX_INT          83
+#define SDIO_INT_N         82
+#define CAM_HS_INT         81
+#define CAM_VS_INT         80
+#define GPI_07_INT         79
+#define DISP_SYNC_INT      78
+#define DSP_INT8           77
+#define U7_HCTS_INT        76
+#define GPI_10_INT         75
+#define GPI_09_INT         74
+#define GPI_08_INT         73
+#define DSP_INT7           72
+#define U2_HCTS_INT        71
+#define SPI2_DATIN_INT     70
+#define GPIO_05_INT        69
+#define GPIO_04_INT        68
+#define GPIO_03_INT        67
+#define GPIO_02_INT        66
+#define GPIO_01_INT        65
+#define GPIO_00_INT        64
+/*Manual: table 258, page 198*/
+/*SUB1 Interrupt Routing (SIC1)*/
+#define SIC1_BASE_INT   32
+#define USB_I2C_INT        63
+#define USB_DEV_HP_INT     62
+#define USB_DEV_LP_INT     61
+#define USB_DEV_DMA_INT    60
+#define USB_HOST_INT       59
+#define USB_OTG_ATX_INT_N  58
+#define USB_OTG_TIMER_INT  57
+#define SW_INT             56
+#define SPI1_INT           55
+#define KEY_IRQ            54
+#define DSP_M_INT          53
+#define RTC_INT            52
+#define I2C_1_INT          51
+#define I2C_2_INT          50
+#define PLL1_LOCK_INT      49
+#define PLL2_LOCK_INT      48
+#define PLL3_LOCK_INT      47
+#define PLL4_LOCK_INT      46
+#define PLL5_LOCK_INT      45
+#define SPI2_INT           44
+#define DSP_INT1           43
+#define DSP_INT2           42
+#define DSP_TDM_INT2       41
+#define TS_AUX_INT         40
+#define TS_IRQ             39
+#define TS_P_INT           38
+#define UOUT1_TO_PAD_INT   37
+#define GPI_11_INT         36
+#define DSP_INT4           35
+#define JTAG_COMM_RX_INT   34
+#define JTAG_COMM_TX_INT   33
+#define DSP_INT3           32
+/*Manual: table 257, page 197*/
+/*MAIN Interrupt Routing*/
+#define MAIN_BASE_INT   0
+#define SUB2_FIQ_N         31   /*active low */
+#define SUB1_FIQ_N         30   /*active low */
+#define JPEG_INT           29
+#define DMA_INT            28
+#define MSTIMER_INT        27
+#define IIR1_INT           26
+#define IIR2_INT           25
+#define IIR7_INT           24
+#define DSP_TDM_INT0       23
+#define DSP_TDM_INT1       22
+#define DSP_P_INT          21
+#define DSP_INT0           20
+#define DUM_INT            19
+#define UOUT0_TO_PAD_INT   18
+#define MP4_ENC_INT        17
+#define MP4_DEC_INT        16
+#define SD0_INT            15
+#define MBX_INT            14
+#define SD1_INT            13
+#define MS_INT_N           12
+#define FLASH_INT          11 /*NAND*/
+#define IIR6_INT           10
+#define IIR5_INT           9
+#define IIR4_INT           8
+#define IIR3_INT           7
+#define WATCH_INT          6
+#define HSTIMER_INT        5
+#define ARCH_TIMER_IRQ     HSTIMER_INT
+#define CAM_INT            4
+#define PRNG_INT           3
+#define CRYPTO_INT         2
+#define SUB2_IRQ_N         1    /*active low */
+#define SUB1_IRQ_N         0    /*active low */
+#define PNX4008_IRQ_TYPES \
+{                                           /*IRQ #'s: */         \
+IRQT_LOW,  IRQT_LOW,  IRQT_LOW,  IRQT_HIGH, /*  0, 1, 2, 3 */     \
+IRQT_LOW,  IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /*  4, 5, 6, 7 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /*  8, 9,10,11 */     \
+IRQT_LOW,  IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_LOW,  IRQT_LOW,  /* 28,29,30,31 */     \
+IRQT_HIGH, IRQT_LOW,  IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */  \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_LOW,  IRQT_LOW,  /* 48,49,50,51 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_LOW,  IRQT_HIGH, /* 56,57,58,59 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */     \
+IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */     \
+}
+/* Start Enable Pin Interrupts - table 58 page 66 */
+#define SE_PIN_BASE_INT   32
+#define SE_U7_RX_INT            63
+#define SE_U7_HCTS_INT          62
+#define SE_BT_CLKREQ_INT        61
+#define SE_U6_IRRX_INT          60
+/*59 unused*/
+#define SE_U5_RX_INT            58
+#define SE_GPI_11_INT           57
+#define SE_U3_RX_INT            56
+#define SE_U2_HCTS_INT          55
+#define SE_U2_RX_INT            54
+#define SE_U1_RX_INT            53
+#define SE_DISP_SYNC_INT        52
+/*51 unused*/
+#define SE_SDIO_INT_N           50
+#define SE_MSDIO_START_INT      49
+#define SE_GPI_06_INT           48
+#define SE_GPI_05_INT           47
+#define SE_GPI_04_INT           46
+#define SE_GPI_03_INT           45
+#define SE_GPI_02_INT           44
+#define SE_GPI_01_INT           43
+#define SE_GPI_00_INT           42
+#define SE_SYSCLKEN_PIN_INT     41
+#define SE_SPI1_DATAIN_INT      40
+#define SE_GPI_07_INT           39
+#define SE_SPI2_DATAIN_INT      38
+#define SE_GPI_10_INT           37
+#define SE_GPI_09_INT           36
+#define SE_GPI_08_INT           35
+/*34-32 unused*/
+/* Start Enable Internal Interrupts - table 57 page 65 */
+#define SE_INT_BASE_INT   0
+#define SE_TS_IRQ               31
+#define SE_TS_P_INT             30
+#define SE_TS_AUX_INT           29
+/*27-28 unused*/
+#define SE_USB_AHB_NEED_CLK_INT 26
+#define SE_MSTIMER_INT          25
+#define SE_RTC_INT              24
+#define SE_USB_NEED_CLK_INT     23
+#define SE_USB_INT              22
+#define SE_USB_I2C_INT          21
+#define SE_USB_OTG_TIMER_INT    20
+#endif /* __PNX4008_IRQS_h__ */
diff --git a/include/asm-arm/arch-pnx4008/memory.h b/include/asm-arm/arch-pnx4008/memory.h
new file mode 100644
index 000000000000..0d8268a95261
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/memory.h
@@ -0,0 +1,24 @@
+/*
+ * linux/include/asm-arm/arch-pnx4008/memory.h
+ *
+ * Copyright (c) 2005 Philips Semiconductors
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x80000000)
+#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET)
+#endif
diff --git a/include/asm-arm/arch-pnx4008/param.h b/include/asm-arm/arch-pnx4008/param.h
new file mode 100644
index 000000000000..95d5f547b416
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/param.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-pnx4008/param.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define HZ 100
diff --git a/include/asm-arm/arch-pnx4008/platform.h b/include/asm-arm/arch-pnx4008/platform.h
new file mode 100644
index 000000000000..485a3651b4d7
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/platform.h
@@ -0,0 +1,69 @@
+/*
+ * include/asm-arm/arch-pnx4008/platfrom.h
+ *
+ * PNX4008 Base addresses - header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * Based on reference code received from Philips:
+ * Copyright (C) 2003 Philips Semiconductors
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_PLATFORM_H__
+#define __ASM_ARCH_PLATFORM_H__
+#define PNX4008_IRAM_BASE               0x08000000
+#define PNX4008_IRAM_SIZE               0x00010000
+#define PNX4008_YUV_SLAVE_BASE          0x10000000
+#define PNX4008_DUM_SLAVE_BASE          0x18000000
+#define PNX4008_NDF_FLASH_BASE          0x20020000
+#define PNX4008_SPI1_BASE               0x20088000
+#define PNX4008_SPI2_BASE               0x20090000
+#define PNX4008_SD_CONFIG_BASE          0x20098000
+#define PNX4008_FLASH_DATA              0x200B0000
+#define PNX4008_MLC_FLASH_BASE          0x200B8000
+#define PNX4008_JPEG_CONFIG_BASE        0x300A0000
+#define PNX4008_DMA_CONFIG_BASE         0x31000000
+#define PNX4008_USB_CONFIG_BASE         0x31020000
+#define PNX4008_SDRAM_CFG_BASE          0x31080000
+#define PNX4008_AHB2FAB_BASE            0x40000000
+#define PNX4008_PWRMAN_BASE             0x40004000
+#define PNX4008_INTCTRLMIC_BASE         0x40008000
+#define PNX4008_INTCTRLSIC1_BASE        0x4000C000
+#define PNX4008_INTCTRLSIC2_BASE        0x40010000
+#define PNX4008_HSUART1_BASE            0x40014000
+#define PNX4008_HSUART2_BASE            0x40018000
+#define PNX4008_HSUART7_BASE            0x4001C000
+#define PNX4008_RTC_BASE                0x40024000
+#define PNX4008_PIO_BASE                0x40028000
+#define PNX4008_MSTIMER_BASE            0x40034000
+#define PNX4008_HSTIMER_BASE            0x40038000
+#define PNX4008_WDOG_BASE               0x4003C000
+#define PNX4008_DEBUG_BASE              0x40040000
+#define PNX4008_TOUCH1_BASE             0x40048000
+#define PNX4008_KEYSCAN_BASE            0x40050000
+#define PNX4008_UARTCTRL_BASE           0x40054000
+#define PNX4008_PWM_BASE                0x4005C000
+#define PNX4008_UART3_BASE              0x40080000
+#define PNX4008_UART4_BASE              0x40088000
+#define PNX4008_UART5_BASE              0x40090000
+#define PNX4008_UART6_BASE              0x40098000
+#define PNX4008_I2C1_BASE               0x400A0000
+#define PNX4008_I2C2_BASE               0x400A8000
+#define PNX4008_MAGICGATE_BASE          0x400B0000
+#define PNX4008_DUMCONF_BASE            0x400B8000
+#define PNX4008_DUM_MAINCFG_BASE        0x400BC000
+#define PNX4008_DSP_BASE                0x400C0000
+#define PNX4008_PROFCOUNTER_BASE        0x400C8000
+#define PNX4008_CRYPTO_BASE             0x400D0000
+#define PNX4008_CAMIFCONF_BASE          0x400D8000
+#define PNX4008_YUV2RGB_BASE            0x400E0000
+#define PNX4008_AUDIOCONFIG_BASE        0x400E8000
+#endif
diff --git a/include/asm-arm/arch-pnx4008/pm.h b/include/asm-arm/arch-pnx4008/pm.h
new file mode 100644
index 000000000000..bac1634cb3e0
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/pm.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-pnx4008/pm.h
+ *
+ * PNX4008 Power Management Routiness - header file
+ *
+ * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_PNX4008_PM_H
+#define __ASM_ARCH_PNX4008_PM_H
+#ifndef __ASSEMBLER__
+#include "irq.h"
+#include "irqs.h"
+#include "clock.h"
+extern void pnx4008_pm_idle(void);
+extern void pnx4008_pm_suspend(void);
+extern unsigned int pnx4008_cpu_suspend_sz;
+extern void pnx4008_cpu_suspend(void);
+extern unsigned int pnx4008_cpu_standby_sz;
+extern void pnx4008_cpu_standby(void);
+extern int pnx4008_startup_pll(struct clk *);
+extern int pnx4008_shutdown_pll(struct clk *);
+#endif                          /* ASSEMBLER */
+#endif                          /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/include/asm-arm/arch-pnx4008/system.h b/include/asm-arm/arch-pnx4008/system.h
new file mode 100644
index 000000000000..6e3da70ab107
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/system.h
@@ -0,0 +1,38 @@
+/*
+ * linux/include/asm-arm/arch-pnx4008/system.h
+ *
+ * Copyright (C) 2003 Philips Semiconductors
+ * Copyright (C) 2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+static void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+#endif
diff --git a/include/asm-arm/arch-pnx4008/timex.h b/include/asm-arm/arch-pnx4008/timex.h
new file mode 100644
index 000000000000..ee470a39089a
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/timex.h
@@ -0,0 +1,73 @@
+/*
+ * include/asm-arm/arch-pnx4008/timex.h
+ *
+ * PNX4008 timers header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __PNX4008_TIMEX_H
+#define __PNX4008_TIMEX_H
+#include <asm/hardware.h>
+#include <asm/io.h>
+#define CLOCK_TICK_RATE         1000000
+#define TICKS2USECS(x)  (x)
+/* MilliSecond Timer - Chapter 21 Page 202 */
+#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
+#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
+#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
+#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
+#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
+#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
+/* High Speed Timer - Chpater 22, Page 205 */
+#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
+#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
+#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
+#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
+#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
+#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
+#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
+#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
+#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
+#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
+#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
+#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
+/* IMPORTANT: both timers are UPCOUNTING */
+/* xSTIM_MCTRL bit definitions */
+#define MR0_INT        1
+#define RESET_COUNT0   (1<<1)
+#define STOP_COUNT0    (1<<2)
+#define MR1_INT        (1<<3)
+#define RESET_COUNT1   (1<<4)
+#define STOP_COUNT1    (1<<5)
+#define MR2_INT        (1<<6)
+#define RESET_COUNT2   (1<<7)
+#define STOP_COUNT2    (1<<8)
+/* xSTIM_CTRL bit definitions */
+#define COUNT_ENAB     1
+#define RESET_COUNT    (1<<1)
+#define DEBUG_EN       (1<<2)
+/* xSTIM_INT bit definitions */
+#define MATCH0_INT     1
+#define MATCH1_INT     (1<<1)
+#define MATCH2_INT     (1<<2)
+#define RTC_TICK0      (1<<4)
+#define RTC_TICK1      (1<<5)
+#endif
diff --git a/include/asm-arm/arch-pnx4008/uncompress.h b/include/asm-arm/arch-pnx4008/uncompress.h
new file mode 100644
index 000000000000..8fa4d24b72b4
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/uncompress.h
@@ -0,0 +1,46 @@
+/*
+ *  linux/include/asm-arm/arch-pnx4008/uncompress.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define UART5_BASE 0x40090000
+#define UART5_DR    (*(volatile unsigned char *) (UART5_BASE))
+#define UART5_FR    (*(volatile unsigned char *) (UART5_BASE + 18))
+static __inline__ void putc(char c)
+{
+        while (UART5_FR & (1 << 5))
+                barrier();
+        UART5_DR = c;
+}
+/*
+ * This does not append a newline
+ */
+static inline void flush(void)
+{
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pnx4008/vmalloc.h b/include/asm-arm/arch-pnx4008/vmalloc.h
new file mode 100644
index 000000000000..140d925f6f37
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/vmalloc.h
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-pnx4008/vmalloc.h
+ *
+ * Author: Vitaly Wool <source@mvista.com>
+ *
+ * 2006 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h
index e7ef497417bb..b6952534a4e1 100644
--- a/include/asm-arm/arch-pxa/idp.h
+++ b/include/asm-arm/arch-pxa/idp.h
@@ -15,7 +15,6 @@
 *             Changes for 2.6 kernel.
 */
-#include <linux/config.h>
 /*
 * Note: this file must be safe to include in assembly files
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h
index eb2dd58d397f..7f8d817b446f 100644
--- a/include/asm-arm/arch-pxa/io.h
+++ b/include/asm-arm/arch-pxa/io.h
@@ -16,6 +16,5 @@
 */
 #define __io(a)                 ((void __iomem *)(a))
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 #endif
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index 67af238a8f8e..f3bc70eee35b 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -10,7 +10,6 @@
 * published by the Free Software Foundation.
 */
-#include <linux/config.h>
 #ifdef CONFIG_PXA27x
 #define PXA_IRQ_SKIP    0
diff --git a/include/asm-arm/arch-pxa/poodle.h b/include/asm-arm/arch-pxa/poodle.h
index 6b5ac5144e70..4d6a40315764 100644
--- a/include/asm-arm/arch-pxa/poodle.h
+++ b/include/asm-arm/arch-pxa/poodle.h
@@ -31,6 +31,7 @@
 #define POODLE_GPIO_CF_CD               (14)
 #define POODLE_GPIO_CF_STSCHG           (14)
 #define POODLE_GPIO_SD_PWR              (33)
+#define POODLE_GPIO_SD_PWR1             (3)
 #define POODLE_GPIO_nSD_CLK             (6)
 #define POODLE_GPIO_nSD_WP              (7)
 #define POODLE_GPIO_nSD_INT             (8)
@@ -42,6 +43,7 @@
 #define POODLE_GPIO_BYPASS_ON           (36)
 #define POODLE_GPIO_CHRG_ON             (38)
 #define POODLE_GPIO_CHRG_FULL           (16)
+#define POODLE_GPIO_DISCHARGE_ON        (42) /* Enable battery discharge */
 /* PXA GPIOs */
 #define POODLE_IRQ_GPIO_ON_KEY          IRQ_GPIO(0)
@@ -68,4 +70,6 @@
 #define POODLE_SCOOP_IO_DIR     ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
 #define POODLE_SCOOP_IO_OUT     ( 0 )
+extern struct platform_device poodle_locomo_device;
 #endif /* __ASM_ARCH_POODLE_H  */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index c8f53a71c076..9f83f4adfbf3 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -13,7 +13,6 @@
 #ifndef __PXA_REGS_H
 #define __PXA_REGS_H
-#include <linux/config.h>
 /*
 * PXA Chip selects
@@ -1626,7 +1625,7 @@
 #define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
 #define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
 #define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
-#define SSCR0_SlotsPerFrm(c) ((x) - 1)  /* Time slots per frame [1..8] */
+#define SSCR0_SlotsPerFrm(x) ((x) - 1)  /* Time slots per frame [1..8] */
 #define SSCR0_ADC       (1 << 30)       /* Audio clock select */
 #define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
 #endif
@@ -1707,6 +1706,10 @@
 #if defined (CONFIG_PXA27x)
 #define SSTO_P1         __REG(0x41000028)  /* SSP Port 1 Time Out Register */
 #define SSPSP_P1        __REG(0x4100002C)  /* SSP Port 1 Programmable Serial Protocol */
+#define SSTSA_P1        __REG(0x41000030)  /* SSP Port 1 Tx Timeslot Active */
+#define SSRSA_P1        __REG(0x41000034)  /* SSP Port 1 Rx Timeslot Active */
+#define SSTSS_P1        __REG(0x41000038)  /* SSP Port 1 Timeslot Status */
+#define SSACD_P1        __REG(0x4100003C)  /* SSP Port 1 Audio Clock Divider */
 #define SSCR0_P2        __REG(0x41700000)  /* SSP Port 2 Control Register 0 */
 #define SSCR1_P2        __REG(0x41700004)  /* SSP Port 2 Control Register 1 */
 #define SSSR_P2         __REG(0x41700008)  /* SSP Port 2 Status Register */
@@ -1714,6 +1717,10 @@
 #define SSDR_P2         __REG(0x41700010)  /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
 #define SSTO_P2         __REG(0x41700028)  /* SSP Port 2 Time Out Register */
 #define SSPSP_P2        __REG(0x4170002C)  /* SSP Port 2 Programmable Serial Protocol */
+#define SSTSA_P2        __REG(0x41700030)  /* SSP Port 2 Tx Timeslot Active */
+#define SSRSA_P2        __REG(0x41700034)  /* SSP Port 2 Rx Timeslot Active */
+#define SSTSS_P2        __REG(0x41700038)  /* SSP Port 2 Timeslot Status */
+#define SSACD_P2        __REG(0x4170003C)  /* SSP Port 2 Audio Clock Divider */
 #define SSCR0_P3        __REG(0x41900000)  /* SSP Port 3 Control Register 0 */
 #define SSCR1_P3        __REG(0x41900004)  /* SSP Port 3 Control Register 1 */
 #define SSSR_P3         __REG(0x41900008)  /* SSP Port 3 Status Register */
@@ -1721,6 +1728,10 @@
 #define SSDR_P3         __REG(0x41900010)  /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
 #define SSTO_P3         __REG(0x41900028)  /* SSP Port 3 Time Out Register */
 #define SSPSP_P3        __REG(0x4190002C)  /* SSP Port 3 Programmable Serial Protocol */
+#define SSTSA_P3        __REG(0x41900030)  /* SSP Port 3 Tx Timeslot Active */
+#define SSRSA_P3        __REG(0x41900034)  /* SSP Port 3 Rx Timeslot Active */
+#define SSTSS_P3        __REG(0x41900038)  /* SSP Port 3 Timeslot Status */
+#define SSACD_P3        __REG(0x4190003C)  /* SSP Port 3 Audio Clock Divider */
 #else /* PXA255 (only port 2) and PXA26x ports*/
 #define SSTO_P1         __REG(0x41000028)  /* SSP Port 1 Time Out Register */
 #define SSPSP_P1        __REG(0x4100002C)  /* SSP Port 1 Programmable Serial Protocol */
@@ -1747,6 +1758,10 @@
 #define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
 #define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
 #define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
+#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
+#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
+#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
+#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
 /*
 * MultiMediaCard (MMC) controller
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index 840a46bfbc54..1d56a3ef89fd 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -10,6 +10,7 @@
 * published by the Free Software Foundation.
 */
+#include <asm/proc-fns.h>
 #include "hardware.h"
 #include "pxa-regs.h"
diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h
index aa125ec56a32..2473bb51d0a6 100644
--- a/include/asm-arm/arch-pxa/timex.h
+++ b/include/asm-arm/arch-pxa/timex.h
@@ -10,7 +10,6 @@
 * published by the Free Software Foundation.
 */
-#include <linux/config.h>
 #if defined(CONFIG_PXA25x)
 /* PXA250/210 timer base */
diff --git a/include/asm-arm/arch-realview/io.h b/include/asm-arm/arch-realview/io.h
index d444a68ac330..c70f1dfbe135 100644
--- a/include/asm-arm/arch-realview/io.h
+++ b/include/asm-arm/arch-realview/io.h
@@ -29,6 +29,5 @@ static inline void __iomem *__io(unsigned long addr)
 #define __io(a)                 __io(a)
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 #endif
diff --git a/include/asm-arm/arch-realview/smp.h b/include/asm-arm/arch-realview/smp.h
index fc87783e8e8b..515819efd046 100644
--- a/include/asm-arm/arch-realview/smp.h
+++ b/include/asm-arm/arch-realview/smp.h
@@ -1,7 +1,6 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
-#include <linux/config.h>
 #include <asm/hardware/gic.h>
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 5f8223e700d3..b7d15d125458 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -33,7 +33,7 @@
                .endm
                .macro  senduart,rd,rx
-                str     \rd, [\rx, # S3C2410_UTXH ]
+                strb    \rd, [\rx, # S3C2410_UTXH ]
                .endm
                .macro  busyuart, rd, rx
@@ -42,6 +42,12 @@
                beq     1001f                           @
                @ FIFO enabled...
 1003:
+                @ check for arm920 vs arm926. currently assume all arm926
+                @ devices have an 64 byte FIFO identical to the s3c2440
+                mrc     p15, 0, \rd, c0, c0
+                and     \rd, \rd, #0xff0
+                teq     \rd, #0x260
+                beq     1004f
                mrc     p15, 0, \rd, c1, c0
                tst     \rd, #1
                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -50,7 +56,7 @@
                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
                and     \rd, \rd, #0x00ff0000
                teq     \rd, #0x00440000                @ is it 2440?
+1004:
                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
                moveq   \rd, \rd, lsr #SHIFT_2440TXF
                tst     \rd, #S3C2410_UFSTAT_TXFULL
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index b011e14f3bc6..72964f9b8414 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -18,7 +18,6 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
-#include <linux/config.h>
 #include <linux/sysdev.h>
 #include "hardware.h"
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S
index 894c35cf3b1e..e09a6b8ec153 100644
--- a/include/asm-arm/arch-s3c2410/entry-macro.S
+++ b/include/asm-arm/arch-s3c2410/entry-macro.S
@@ -18,8 +18,6 @@
 #define INTPND          (0x10)
 #define INTOFFSET       (0x14)
-#define EXTINTPEND      (0xa8)
-#define EXTINTMASK      (0xa4)
 #include <asm/hardware.h>
 #include <asm/arch/irqs.h>
@@ -28,37 +26,23 @@
                mov     \base, #S3C24XX_VA_IRQ
-                ldr     \irqstat, [ \base, #INTPND]
-                bics    \irqnr, \irqstat, #3<<4         @@ only an GPIO IRQ
-                beq     2000f
                @@ try the interrupt offset register, since it is there
+                ldr     \irqstat, [ \base, #INTPND ]
+                teq     \irqstat, #0
+                beq     1002f
                ldr     \irqnr, [ \base, #INTOFFSET ]
                mov     \tmp, #1
                tst     \irqstat, \tmp, lsl \irqnr
-                addne   \irqnr, \irqnr, #IRQ_EINT0
                bne     1001f
                @@ the number specified is not a valid irq, so try
                @@ and work it out for ourselves
-                mov     \irqnr, #IRQ_EINT0              @@ start here
+                mov     \irqnr, #0              @@ start here
-                b       3000f
-2000:
-                @@ load the GPIO interrupt register, and check it
-                add     \tmp, \base, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
-                ldr     \irqstat, [ \tmp, # EXTINTPEND ]
-                ldr     \irqnr,   [ \tmp, # EXTINTMASK ]
-                bics    \irqstat, \irqstat, \irqnr
-                beq     1001f
-                mov     \irqnr, #(IRQ_EINT4 - 4)
                @@ work out which irq (if any) we got
-3000:
                movs    \tmp, \irqstat, lsl#16
                addeq   \irqnr, \irqnr, #16
                moveq   \irqstat, \irqstat, lsr#16
@@ -75,9 +59,9 @@
                addeq   \irqnr, \irqnr, #1
                @@ we have the value
-                movs    \irqnr, \irqnr
 1001:
+                adds    \irqnr, \irqnr, #IRQ_EINT0
+1002:
                @@ exit here, Z flag unset if IRQ
        .endm
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index c380d264a847..fae2766ff32b 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -126,9 +126,18 @@
 #define S3C24XX_SZ_IIS     SZ_1M
 /* GPIO ports */
-#define S3C24XX_VA_GPIO    S3C2410_ADDR(0x00E00000)
+/* the calculation for the VA of this must ensure that
+ * it is the same distance apart from the UART in the
+ * phsyical address space, as the initial mapping for the IO
+ * is done as a 1:1 maping. This puts it (currently) at
+ * 0xF6800000, which is not in the way of any current mapping
+ * by the base system.
+*/
 #define S3C2400_PA_GPIO    (0x15600000)
 #define S3C2410_PA_GPIO    (0x56000000)
+#define S3C24XX_VA_GPIO    ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
 #define S3C24XX_SZ_GPIO    SZ_1M
 /* RTC */
@@ -227,4 +236,20 @@
 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
 #endif
+/* deal with the registers that move under the 2412/2413 */
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#ifndef __ASSEMBLY__
+extern void __iomem *s3c24xx_va_gpio2;
+#endif
+#ifdef CONFIG_CPU_S3C2412_ONLY
+#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
+#else
+#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
+#endif
+#else
+#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
+#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
+#endif
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 34360706e016..a7c61feb8433 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -1,6 +1,6 @@
 /* linux/include/asm/arch-s3c2410/regs-clock.h
 *
- * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
 *                    http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
@@ -114,7 +114,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
 #endif /* __ASSEMBLY__ */
-#ifdef CONFIG_CPU_S3C2440
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 /* extra registers */
 #define S3C2440_CAMDIVN     S3C2410_CLKREG(0x18)
@@ -136,7 +136,70 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
 #define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
 #define S3C2440_CAMDIVN_DVSEN        (1<<12)
-#endif /* CONFIG_CPU_S3C2440 */
+#define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)
+#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#define S3C2412_OSCSET          S3C2410_CLKREG(0x18)
+#define S3C2412_CLKSRC          S3C2410_CLKREG(0x1C)
+#define S3C2412_PLLCON_OFF              (1<<20)
+#define S3C2412_CLKDIVN_PDIVN           (1<<2)
+#define S3C2412_CLKDIVN_HDIVN_MASK      (3<<0)
+#define S3C2421_CLKDIVN_ARMDIVN         (1<<3)
+#define S3C2412_CLKDIVN_USB48DIV        (1<<6)
+#define S3C2412_CLKDIVN_UARTDIV_MASK    (15<<8)
+#define S3C2412_CLKDIVN_UARTDIV_SHIFT   (8)
+#define S3C2412_CLKDIVN_I2SDIV_MASK     (15<<12)
+#define S3C2412_CLKDIVN_I2SDIV_SHIFT    (12)
+#define S3C2412_CLKDIVN_CAMDIV_MASK     (15<<16)
+#define S3C2412_CLKDIVN_CAMDIV_SHIFT    (16)
+#define S3C2412_CLKCON_WDT              (1<<28)
+#define S3C2412_CLKCON_SPI              (1<<27)
+#define S3C2412_CLKCON_IIS              (1<<26)
+#define S3C2412_CLKCON_IIC              (1<<25)
+#define S3C2412_CLKCON_ADC              (1<<24)
+#define S3C2412_CLKCON_RTC              (1<<23)
+#define S3C2412_CLKCON_GPIO             (1<<22)
+#define S3C2412_CLKCON_UART2            (1<<21)
+#define S3C2412_CLKCON_UART1            (1<<20)
+#define S3C2412_CLKCON_UART0            (1<<19)
+#define S3C2412_CLKCON_SDI              (1<<18)
+#define S3C2412_CLKCON_PWMT             (1<<17)
+#define S3C2412_CLKCON_USBD             (1<<16)
+#define S3C2412_CLKCON_CAMCLK           (1<<15)
+#define S3C2412_CLKCON_UARTCLK          (1<<14)
+/* missing 13 */
+#define S3C2412_CLKCON_USB_HOST48       (1<<12)
+#define S3C2412_CLKCON_USB_DEV48        (1<<11)
+#define S3C2412_CLKCON_HCLKdiv2         (1<<10)
+#define S3C2412_CLKCON_HCLKx2           (1<<9)
+#define S3C2412_CLKCON_SDRAM            (1<<8)
+/* missing 7 */
+#define S3C2412_CLKCON_USBH             S3C2410_CLKCON_USBH
+#define S3C2412_CLKCON_LCDC             S3C2410_CLKCON_LCDC
+#define S3C2412_CLKCON_NAND             S3C2410_CLKCON_NAND
+#define S3C2412_CLKCON_DMA3             (1<<3)
+#define S3C2412_CLKCON_DMA2             (1<<2)
+#define S3C2412_CLKCON_DMA1             (1<<1)
+#define S3C2412_CLKCON_DMA0             (1<<0)
+/* clock sourec controls */
+#define S3C2412_CLKSRC_EXTCLKDIV_MASK           (7 << 0)
+#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT          (0)
+#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV        (1<<3)
+#define S3C2412_CLKSRC_MSYSCLK_MPLL             (1<<4)
+#define S3C2412_CLKSRC_USYSCLK_UPLL             (1<<5)
+#define S3C2412_CLKSRC_UARTCLK_MPLL             (1<<8)
+#define S3C2412_CLKSRC_I2SCLK_MPLL              (1<<9)
+#define S3C2412_CLKSRC_USBCLK_HCLK              (1<<10)
+#define S3C2412_CLKSRC_CAMCLK_HCLK              (1<<11)
+#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
 #endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index a023b0434efe..84aca61cbaa3 100644
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -23,6 +23,9 @@
 #define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
 #define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
+#define S3C2412_DSC0       S3C2410_GPIOREG(0xdc)
+#define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
 #define S3C2440_SELECT_DSC0 (0)
 #define S3C2440_SELECT_DSC1 (1<<31)
@@ -170,7 +173,7 @@
 #define S3C2440_DSC1_CS1_4mA    (3<<2)
 #define S3C2440_DSC1_CS1_MASK   (3<<2)
-#define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0
+#define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0)
 #define S3C2440_DSC1_CS0_10mA   (0<<0)
 #define S3C2440_DSC1_CS0_8mA    (1<<0)
 #define S3C2440_DSC1_CS0_6mA    (2<<0)
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index d2574084697f..6dd17f0f84e0 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -45,7 +45,7 @@
 #define S3C24XX_MISCCR        S3C2400_MISCCR
 #else
 #define S3C24XX_GPIO_BASE(x)  S3C2410_GPIO_BASE(x)
-#define S3C24XX_MISCCR        S3C2410_MISCCR
+#define S3C24XX_MISCCR        S3C24XX_GPIOREG2(0x80)
 #endif /* CONFIG_CPU_S3C2400 */
@@ -73,9 +73,15 @@
 #define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* not available on A */
 #define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
-/* configure GPIO ports A..G */
+/* register address for the GPIO registers.
+ * S3C24XX_GPIOREG2 is for the second set of registers in the
+ * GPIO which move between s3c2410 and s3c2412 type systems */
 #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
+#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
+/* configure GPIO ports A..G */
 /* port A - S3C2410: 22bits, zero in bit X makes pin X output
 *          S3C2400: 18bits, zero in bit X makes pin X output
@@ -450,12 +456,14 @@
 #define S3C2410_GPD0_OUTP       (0x01 << 0)
 #define S3C2410_GPD0_VD8        (0x02 << 0)
 #define S3C2400_GPD0_VFRAME     (0x02 << 0)
+#define S3C2442_GPD0_nSPICS1    (0x03 << 0)
 #define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
 #define S3C2410_GPD1_INP        (0x00 << 2)
 #define S3C2410_GPD1_OUTP       (0x01 << 2)
 #define S3C2410_GPD1_VD9        (0x02 << 2)
 #define S3C2400_GPD1_VM         (0x02 << 2)
+#define S3C2442_GPD1_SPICLK1    (0x03 << 2)
 #define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
 #define S3C2410_GPD2_INP        (0x00 << 4)
@@ -858,6 +866,7 @@
 #define S3C2410_GPG12_OUTP    (0x01 << 24)
 #define S3C2410_GPG12_EINT20  (0x02 << 24)
 #define S3C2410_GPG12_XMON    (0x03 << 24)
+#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
 #define S3C2410_GPG13         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
 #define S3C2410_GPG13_INP     (0x00 << 26)
@@ -943,17 +952,25 @@
 #define S3C2410_GPH9_INP      (0x00 << 18)
 #define S3C2410_GPH9_OUTP     (0x01 << 18)
 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
+#define S3C2442_GPH9_nSPICS0  (0x03 << 18)
 #define S3C2410_GPH10         S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
 #define S3C2410_GPH10_INP     (0x00 << 20)
 #define S3C2410_GPH10_OUTP    (0x01 << 20)
 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
+/* The S3C2412 and S3C2413 move the GPJ register set to after
+ * GPH, which means all registers after 0x80 are now offset by 0x10
+ * for the 2412/2413 from the 2410/2440/2442
+*/
 /* miscellaneous control */
 #define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
 #define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
+#define S3C24XX_DCLKCON    S3C24XX_GPIOREG2(0x84)
 /* see clock.h for dclk definitions */
 /* pullup control on databus */
@@ -981,6 +998,8 @@
 #define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
 #define S3C2410_MISCCR_CLK0_MASK    (7<<4)
+#define S3C2412_MISCCR_CLK0_RTC     (2<<4)
 #define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
 #define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
 #define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
@@ -989,6 +1008,8 @@
 #define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
 #define S3C2410_MISCCR_CLK1_MASK    (7<<8)
+#define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
@@ -996,7 +1017,7 @@
 #define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
 #define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
-#define S3C2410_MISCCR_nEN_SCLKE    (1<<19)
+#define S3C2410_MISCCR_nEN_SCLKE    (1<<19)     /* not 2412 */
 #define S3C2410_MISCCR_SDSLEEP      (7<<17)
 /* external interrupt control... */
@@ -1013,6 +1034,10 @@
 #define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
 #define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
+#define S3C24XX_EXTINT0    S3C24XX_GPIOREG2(0x88)
+#define S3C24XX_EXTINT1    S3C24XX_GPIOREG2(0x8C)
+#define S3C24XX_EXTINT2    S3C24XX_GPIOREG2(0x90)
 /* values for S3C2410_EXTINT0/1/2 */
 #define S3C2410_EXTINT_LOWLEV    (0x00)
 #define S3C2410_EXTINT_HILEV     (0x01)
@@ -1026,6 +1051,11 @@
 #define S3C2410_EINFLT2    S3C2410_GPIOREG(0x9C)
 #define S3C2410_EINFLT3    S3C2410_GPIOREG(0xA0)
+#define S3C24XX_EINFLT0    S3C24XX_GPIOREG2(0x94)
+#define S3C24XX_EINFLT1    S3C24XX_GPIOREG2(0x98)
+#define S3C24XX_EINFLT2    S3C24XX_GPIOREG2(0x9C)
+#define S3C24XX_EINFLT3    S3C24XX_GPIOREG2(0xA0)
 /* values for interrupt filtering */
 #define S3C2410_EINTFLT_PCLK            (0x00)
 #define S3C2410_EINTFLT_EXTCLK          (1<<7)
@@ -1035,6 +1065,7 @@
 /* GSTATUS have miscellaneous information in them
 *
+ * These move between s3c2410 and s3c2412 style systems.
 */
 #define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
@@ -1043,6 +1074,18 @@
 #define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
 #define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
+#define S3C2412_GSTATUS0   S3C2410_GPIOREG(0x0BC)
+#define S3C2412_GSTATUS1   S3C2410_GPIOREG(0x0C0)
+#define S3C2412_GSTATUS2   S3C2410_GPIOREG(0x0C4)
+#define S3C2412_GSTATUS3   S3C2410_GPIOREG(0x0C8)
+#define S3C2412_GSTATUS4   S3C2410_GPIOREG(0x0CC)
+#define S3C24XX_GSTATUS0   S3C24XX_GPIOREG2(0x0AC)
+#define S3C24XX_GSTATUS1   S3C24XX_GPIOREG2(0x0B0)
+#define S3C24XX_GSTATUS2   S3C24XX_GPIOREG2(0x0B4)
+#define S3C24XX_GSTATUS3   S3C24XX_GPIOREG2(0x0B8)
+#define S3C24XX_GSTATUS4   S3C24XX_GPIOREG2(0x0BC)
 #define S3C2410_GSTATUS0_nWAIT     (1<<3)
 #define S3C2410_GSTATUS0_NCON      (1<<2)
 #define S3C2410_GSTATUS0_RnB       (1<<1)
@@ -1050,7 +1093,9 @@
 #define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
 #define S3C2410_GSTATUS1_2410      (0x32410000)
+#define S3C2410_GSTATUS1_2412      (0x32412001)
 #define S3C2410_GSTATUS1_2440      (0x32440000)
+#define S3C2410_GSTATUS1_2442      (0x32440aaa)
 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
 #define S3C2410_GSTATUS2_OFFRESET  (1<<1)
@@ -1072,5 +1117,22 @@
 #define S3C2400_OPENCR_OPC_MOSIDIS  (0<<5)
 #define S3C2400_OPENCR_OPC_MOSIEN   (1<<5)
+/* 2412/2413 sleep configuration registers */
+#define S3C2412_GPBSLPCON       S3C2410_GPIOREG(0x1C)
+#define S3C2412_GPCSLPCON       S3C2410_GPIOREG(0x2C)
+#define S3C2412_GPDSLPCON       S3C2410_GPIOREG(0x3C)
+#define S3C2412_GPESLPCON       S3C2410_GPIOREG(0x4C)
+#define S3C2412_GPFSLPCON       S3C2410_GPIOREG(0x5C)
+#define S3C2412_GPGSLPCON       S3C2410_GPIOREG(0x6C)
+#define S3C2412_GPHSLPCON       S3C2410_GPIOREG(0x7C)
+/* definitions for each pin bit */
+#define S3C2412_SLPCON_LOW(x)   ( 0x00 << ((x) * 2))
+#define S3C2412_SLPCON_HI(x)    ( 0x01 << ((x) * 2))
+#define S3C2412_SLPCON_IN(x)    ( 0x02 << ((x) * 2))
+#define S3C2412_SLPCON_PDWN(x)  ( 0x03 << ((x) * 2))
+#define S3C2412_SLPCON_MASK(x)  ( 0x03 << ((x) * 2))
 #endif  /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
index 3ad2324acc39..18edae50d0b8 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpioj.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h
@@ -32,6 +32,11 @@
 #define S3C2440_GPJDAT      S3C2410_GPIOREG(0xd4)
 #define S3C2440_GPJUP       S3C2410_GPIOREG(0xd8)
+#define S3C2413_GPJCON          S3C2410_GPIOREG(0x80)
+#define S3C2413_GPJDAT          S3C2410_GPIOREG(0x84)
+#define S3C2413_GPJUP           S3C2410_GPIOREG(0x88)
+#define S3C2413_GPJSLPCON       S3C2410_GPIOREG(0x8C)
 #define S3C2440_GPJ0            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
 #define S3C2440_GPJ0_INP        (0x00 << 0)
 #define S3C2440_GPJ0_OUTP       (0x01 << 0)
diff --git a/include/asm-arm/arch-s3c2410/regs-irq.h b/include/asm-arm/arch-s3c2410/regs-irq.h
index 24b7292df79e..572fca5d9acf 100644
--- a/include/asm-arm/arch-s3c2410/regs-irq.h
+++ b/include/asm-arm/arch-s3c2410/regs-irq.h
@@ -23,6 +23,7 @@
 #define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
 #define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
+#define S3C24XX_EINTREG(x)  ((x) + S3C24XX_VA_GPIO2)
 #define S3C2410_SRCPND         S3C2410_IRQREG(0x000)
 #define S3C2410_INTMOD         S3C2410_IRQREG(0x004)
@@ -40,5 +41,10 @@
 #define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
 #define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
+#define S3C2412_EINTMASK       S3C2410_EINTREG(0x0B4)
+#define S3C2412_EINTPEND       S3C2410_EINTREG(0X0B8)
+#define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x0A4)
+#define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X0A8)
 #endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
index 83b01254c4ac..93f651ae2967 100644
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/arch-s3c2410/regs-serial.h
@@ -82,6 +82,12 @@
 #define S3C2440_UCON2_DIVMASK     (7 << 12)
 #define S3C2440_UCON_DIVSHIFT     (12)
+#define S3C2412_UCON_CLKMASK    (3<<10)
+#define S3C2412_UCON_UCLK       (1<<10)
+#define S3C2412_UCON_USYSCLK    (3<<10)
+#define S3C2412_UCON_PCLK       (0<<10)
+#define S3C2412_UCON_PCLK2      (2<<10)
 #define S3C2410_UCON_UCLK         (1<<10)
 #define S3C2410_UCON_SBREAK       (1<<4)
@@ -124,6 +130,15 @@
 #define S3C2410_UMCOM_AFC         (1<<4)
 #define S3C2410_UMCOM_RTS_LOW     (1<<0)
+#define S3C2412_UMCON_AFC_63    (0<<5)
+#define S3C2412_UMCON_AFC_56    (1<<5)
+#define S3C2412_UMCON_AFC_48    (2<<5)
+#define S3C2412_UMCON_AFC_40    (3<<5)
+#define S3C2412_UMCON_AFC_32    (4<<5)
+#define S3C2412_UMCON_AFC_24    (5<<5)
+#define S3C2412_UMCON_AFC_16    (6<<5)
+#define S3C2412_UMCON_AFC_8     (7<<5)
 #define S3C2410_UFSTAT_TXFULL     (1<<9)
 #define S3C2410_UFSTAT_RXFULL     (1<<8)
 #define S3C2410_UFSTAT_TXMASK     (15<<4)
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index a6f6a0e44afa..8e152a05e533 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -22,7 +22,6 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
-#include <linux/config.h>
 /* defines for UART registers */
 #include "asm/arch/regs-serial.h"
@@ -82,7 +81,8 @@ static void putc(int ch)
                while (1) {
                        level = uart_rd(S3C2410_UFSTAT);
-                        if (cpuid == S3C2410_GSTATUS1_2440) {
+                        if (cpuid == S3C2410_GSTATUS1_2440 ||
+                            cpuid == S3C2410_GSTATUS1_2442) {
                                level &= S3C2440_UFSTAT_TXMASK;
                                level >>= S3C2440_UFSTAT_TXSHIFT;
                        } else {
@@ -130,7 +130,7 @@ static void arch_decomp_wdog_start(void)
 {
        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
 }
 #else
diff --git a/include/asm-arm/arch-sa1100/assabet.h b/include/asm-arm/arch-sa1100/assabet.h
index 1f59b368c3f6..d6a1bb5b4944 100644
--- a/include/asm-arm/arch-sa1100/assabet.h
+++ b/include/asm-arm/arch-sa1100/assabet.h
@@ -12,7 +12,6 @@
 #ifndef __ASM_ARCH_ASSABET_H
 #define __ASM_ARCH_ASSABET_H
-#include <linux/config.h>
 /* System Configuration Register flags */
diff --git a/include/asm-arm/arch-sa1100/cerf.h b/include/asm-arm/arch-sa1100/cerf.h
index 356d5ba88991..9a19c3d07c1e 100644
--- a/include/asm-arm/arch-sa1100/cerf.h
+++ b/include/asm-arm/arch-sa1100/cerf.h
@@ -10,7 +10,6 @@
 #ifndef _INCLUDE_CERF_H_
 #define _INCLUDE_CERF_H_
-#include <linux/config.h>
 #define CERF_ETH_IO                     0xf0000000
 #define CERF_ETH_IRQ IRQ_GPIO26
diff --git a/include/asm-arm/arch-sa1100/collie.h b/include/asm-arm/arch-sa1100/collie.h
index d49e5ff63ca4..14a344aa3cc7 100644
--- a/include/asm-arm/arch-sa1100/collie.h
+++ b/include/asm-arm/arch-sa1100/collie.h
@@ -13,7 +13,6 @@
 #ifndef __ASM_ARCH_COLLIE_H
 #define __ASM_ARCH_COLLIE_H
-#include <linux/config.h>
 #define COLLIE_SCP_CHARGE_ON    SCOOP_GPCR_PA11
 #define COLLIE_SCP_DIAG_BOOT1   SCOOP_GPCR_PA12
diff --git a/include/asm-arm/arch-sa1100/dma.h b/include/asm-arm/arch-sa1100/dma.h
index 02575d72ac6b..6b7917a2e77a 100644
--- a/include/asm-arm/arch-sa1100/dma.h
+++ b/include/asm-arm/arch-sa1100/dma.h
@@ -10,7 +10,6 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
-#include <linux/config.h>
 #include "hardware.h"
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
index ee008a5484f3..1abd7cfc8bce 100644
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -12,7 +12,6 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
-#include <linux/config.h>
 #define UNCACHEABLE_ADDR        0xfa050000
diff --git a/include/asm-arm/arch-sa1100/ide.h b/include/asm-arm/arch-sa1100/ide.h
index 2153538069c7..98b10bcf9f1b 100644
--- a/include/asm-arm/arch-sa1100/ide.h
+++ b/include/asm-arm/arch-sa1100/ide.h
@@ -9,7 +9,6 @@
 *              architectures.
 */
-#include <linux/config.h>
 #include <asm/irq.h>
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h
index 040ccde7a11e..0756269404b1 100644
--- a/include/asm-arm/arch-sa1100/io.h
+++ b/include/asm-arm/arch-sa1100/io.h
@@ -22,6 +22,5 @@ static inline void __iomem *__io(unsigned long addr)
 }
 #define __io(a)                 __io(a)
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 #endif
diff --git a/include/asm-arm/arch-sa1100/irqs.h b/include/asm-arm/arch-sa1100/irqs.h
index eabd3be3d705..d7940683efb1 100644
--- a/include/asm-arm/arch-sa1100/irqs.h
+++ b/include/asm-arm/arch-sa1100/irqs.h
@@ -7,7 +7,6 @@
 *
 * 2001/11/14   RMK     Cleaned up and standardised a lot of the IRQs.
 */
-#include <linux/config.h>
 #define IRQ_GPIO0               0
 #define IRQ_GPIO1               1
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index a29fac1387ca..1ff172dc8e33 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -7,7 +7,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-#include <linux/config.h>
 #include <asm/sizes.h>
 /*
diff --git a/include/asm-arm/arch-sa1100/system.h b/include/asm-arm/arch-sa1100/system.h
index 0f0612f79b2b..aef91e3b63fe 100644
--- a/include/asm-arm/arch-sa1100/system.h
+++ b/include/asm-arm/arch-sa1100/system.h
@@ -3,7 +3,6 @@
 *
 * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
 */
-#include <linux/config.h>
 #include <asm/hardware.h>
 static inline void arch_idle(void)
diff --git a/include/asm-arm/arch-versatile/io.h b/include/asm-arm/arch-versatile/io.h
index 47e904cf25c7..c4d01948e00b 100644
--- a/include/asm-arm/arch-versatile/io.h
+++ b/include/asm-arm/arch-versatile/io.h
@@ -28,6 +28,5 @@ static inline void __iomem *__io(unsigned long addr)
 }
 #define __io(a) __io(a)
 #define __mem_pci(a)            (a)
-#define __mem_isa(a)            (a)
 #endif
diff --git a/include/asm-arm/arch-versatile/system.h b/include/asm-arm/arch-versatile/system.h
index 8889a189739f..71c6254c0d9b 100644
--- a/include/asm-arm/arch-versatile/system.h
+++ b/include/asm-arm/arch-versatile/system.h
@@ -36,16 +36,14 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode)
 {
-        unsigned int hdr_ctrl = (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_RESETCTL_OFFSET);
+        u32 val;
-        unsigned int val;
-        /*
+        val = __raw_readl(IO_ADDRESS(VERSATILE_SYS_RESETCTL)) & ~0x7;
-         * To reset, we hit the on-board reset register
+        val |= 0x105;
-         * in the system FPGA
-         */
+        __raw_writel(0xa05f, IO_ADDRESS(VERSATILE_SYS_LOCK));
-        val = __raw_readl(hdr_ctrl);
+        __raw_writel(val, IO_ADDRESS(VERSATILE_SYS_RESETCTL));
-        val |= VERSATILE_SYS_CTRL_RESET_CONFIGCLR;
+        __raw_writel(0, IO_ADDRESS(VERSATILE_SYS_LOCK));
-        __raw_writel(val, hdr_ctrl);
 }
 #endif
diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
index 3d7283d84405..4b0ce3e7de9a 100644
--- a/include/asm-arm/atomic.h
+++ b/include/asm-arm/atomic.h
@@ -11,7 +11,6 @@
 #ifndef __ASM_ARM_ATOMIC_H
 #define __ASM_ARM_ATOMIC_H
-#include <linux/config.h>
 #include <linux/compiler.h>
 typedef struct { volatile int counter; } atomic_t;
diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h
index 5ab8216f5204..7fb02138f585 100644
--- a/include/asm-arm/bug.h
+++ b/include/asm-arm/bug.h
@@ -2,7 +2,6 @@
 #define _ASMARM_BUG_H
 #include <linux/config.h>
-#include <linux/stddef.h>
 #ifdef CONFIG_BUG
 #ifdef CONFIG_DEBUG_BUGVERBOSE
diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h
index 17eaf8bdf092..e6f7fcdc73b0 100644
--- a/include/asm-arm/byteorder.h
+++ b/include/asm-arm/byteorder.h
@@ -22,16 +22,18 @@ static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
 {
        __u32 t;
-        if (__builtin_constant_p(x)) {
+#ifndef __thumb__
-                t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
+        if (!__builtin_constant_p(x)) {
-        } else {
                /*
                 * The compiler needs a bit of a hint here to always do the
                 * right thing and not screw it up to different degrees
                 * depending on the gcc version.
                 */
                asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x));
-        }
+        } else
+#endif
+                t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
        x = (x << 24) | (x >> 8);               /* mov r0,r0,ror #8      */
        t &= ~0x00FF0000;                       /* bic r1,r1,#0x00FF0000 */
        x ^= (t >> 8);                          /* eor r0,r0,r1,lsr #8   */
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 746be56b1b70..fe0c744e0266 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -10,7 +10,6 @@
 #ifndef _ASMARM_CACHEFLUSH_H
 #define _ASMARM_CACHEFLUSH_H
-#include <linux/config.h>
 #include <linux/sched.h>
 #include <linux/mm.h>
diff --git a/include/asm-arm/cpu.h b/include/asm-arm/cpu.h
index 751bc7462074..715426b9b08e 100644
--- a/include/asm-arm/cpu.h
+++ b/include/asm-arm/cpu.h
@@ -10,7 +10,6 @@
 #ifndef __ASM_ARM_CPU_H
 #define __ASM_ARM_CPU_H
-#include <linux/config.h>
 #include <linux/percpu.h>
 struct cpuinfo_arm {
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
index 63ca7412a462..55eb4dc3253d 100644
--- a/include/asm-arm/dma-mapping.h
+++ b/include/asm-arm/dma-mapping.h
@@ -3,7 +3,6 @@
 #ifdef __KERNEL__
-#include <linux/config.h>
 #include <linux/mm.h> /* need struct page */
 #include <asm/scatterlist.h>
diff --git a/include/asm-arm/dma.h b/include/asm-arm/dma.h
index 49c01e2bf7c8..9f2c5305c260 100644
--- a/include/asm-arm/dma.h
+++ b/include/asm-arm/dma.h
@@ -3,7 +3,6 @@
 typedef unsigned int dmach_t;
-#include <linux/config.h>
 #include <linux/spinlock.h>
 #include <asm/system.h>
 #include <asm/scatterlist.h>
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index 2d44b42d1847..71061ca5c5d0 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -1,7 +1,6 @@
 #ifndef __ASMARM_ELF_H
 #define __ASMARM_ELF_H
-#include <linux/config.h>
 /*
 * ELF register definitions..
diff --git a/include/asm-arm/fpstate.h b/include/asm-arm/fpstate.h
index 52bae088a185..132c3c5628b2 100644
--- a/include/asm-arm/fpstate.h
+++ b/include/asm-arm/fpstate.h
@@ -11,7 +11,6 @@
 #ifndef __ASM_ARM_FPSTATE_H
 #define __ASM_ARM_FPSTATE_H
-#include <linux/config.h>
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/glue.h b/include/asm-arm/glue.h
index 223e0d6c41be..0cc5d3b10ce2 100644
--- a/include/asm-arm/glue.h
+++ b/include/asm-arm/glue.h
@@ -15,7 +15,6 @@
 */
 #ifdef __KERNEL__
-#include <linux/config.h>
 #ifdef __STDC__
 #define ____glue(name,fn)       name##fn
diff --git a/include/asm-arm/hardirq.h b/include/asm-arm/hardirq.h
index 1cbb173bf5b1..182310b99195 100644
--- a/include/asm-arm/hardirq.h
+++ b/include/asm-arm/hardirq.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_HARDIRQ_H
 #define __ASM_HARDIRQ_H
-#include <linux/config.h>
 #include <linux/cache.h>
 #include <linux/threads.h>
 #include <asm/irq.h>
diff --git a/include/asm-arm/hardware/dec21285.h b/include/asm-arm/hardware/dec21285.h
index 6685e3fb97b1..546f7077be9c 100644
--- a/include/asm-arm/hardware/dec21285.h
+++ b/include/asm-arm/hardware/dec21285.h
@@ -18,7 +18,6 @@
 #define DC21285_PCI_IO                  0x7c000000
 #define DC21285_PCI_MEM                 0x80000000
-#include <linux/config.h>
 #ifndef __ASSEMBLY__
 #include <asm/hardware.h>
 #define DC21285_IO(x)           ((volatile unsigned long *)(ARMCSR_BASE+(x)))
diff --git a/include/asm-arm/hardware/iomd.h b/include/asm-arm/hardware/iomd.h
index 82fa2c279a18..396e55ad06c6 100644
--- a/include/asm-arm/hardware/iomd.h
+++ b/include/asm-arm/hardware/iomd.h
@@ -13,7 +13,6 @@
 #ifndef __ASMARM_HARDWARE_IOMD_H
 #define __ASMARM_HARDWARE_IOMD_H
-#include <linux/config.h>
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/hardware/sharpsl_pm.h b/include/asm-arm/hardware/sharpsl_pm.h
index 36983e5f3665..ecf15b83956f 100644
--- a/include/asm-arm/hardware/sharpsl_pm.h
+++ b/include/asm-arm/hardware/sharpsl_pm.h
@@ -16,6 +16,7 @@ struct sharpsl_charger_machinfo {
        void (*exit)(void);
        int gpio_acin;
        int gpio_batfull;
+        int batfull_irq;
        int gpio_batlock;
        int gpio_fatal;
        void (*discharge)(int);
@@ -34,9 +35,19 @@ struct sharpsl_charger_machinfo {
 #define SHARPSL_STATUS_FATAL    7
        unsigned long (*charger_wakeup)(void);
        int (*should_wakeup)(unsigned int resume_on_alarm);
+        void (*backlight_limit)(int);
+        int (*backlight_get_status) (void);
+        int charge_on_volt;
+        int charge_on_temp;
+        int charge_acin_high;
+        int charge_acin_low;
+        int fatal_acin_volt;
+        int fatal_noacin_volt;
        int bat_levels;
        struct battery_thresh *bat_levels_noac;
        struct battery_thresh *bat_levels_acin;
+        struct battery_thresh *bat_levels_noac_bl;
+        struct battery_thresh *bat_levels_acin_bl;
        int status_high_acin;
        int status_low_acin;
        int status_high_noac;
diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h
index 60b5105c9c93..66e67e60bc56 100644
--- a/include/asm-arm/irq.h
+++ b/include/asm-arm/irq.h
@@ -47,10 +47,6 @@ void disable_irq_wake(unsigned int irq);
 void enable_irq_wake(unsigned int irq);
 int setup_irq(unsigned int, struct irqaction *);
-struct irqaction;
-struct pt_regs;
-int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
 extern void migrate_irqs(void);
 #endif
diff --git a/include/asm-arm/leds.h b/include/asm-arm/leds.h
index 88ce4124f854..12290ea55801 100644
--- a/include/asm-arm/leds.h
+++ b/include/asm-arm/leds.h
@@ -13,7 +13,6 @@
 #ifndef ASM_ARM_LEDS_H
 #define ASM_ARM_LEDS_H
-#include <linux/config.h>
 typedef enum {
        led_idle_start,
diff --git a/include/asm-arm/mach/serial_at91rm9200.h b/include/asm-arm/mach/serial_at91.h
index 98f4b0cb883c..1290bb32802d 100644
--- a/include/asm-arm/mach/serial_at91rm9200.h
+++ b/include/asm-arm/mach/serial_at91.h
@@ -1,5 +1,5 @@
 /*
- *  linux/include/asm-arm/mach/serial_at91rm9200.h
+ *  linux/include/asm-arm/mach/serial_at91.h
 *
 *  Based on serial_sa1100.h  by Nicolas Pitre
 *
@@ -7,7 +7,6 @@
 *
 *  Low level machine dependent UART functions.
 */
-#include <linux/config.h>
 struct uart_port;
@@ -15,7 +14,7 @@ struct uart_port;
 * This is a temporary structure for registering these
 * functions; it is intended to be discarded after boot.
 */
-struct at91rm9200_port_fns {
+struct at91_port_fns {
        void    (*set_mctrl)(struct uart_port *, u_int);
        u_int   (*get_mctrl)(struct uart_port *);
        void    (*enable_ms)(struct uart_port *);
@@ -26,11 +25,9 @@ struct at91rm9200_port_fns {
 };
 #if defined(CONFIG_SERIAL_AT91)
-void at91_register_uart_fns(struct at91rm9200_port_fns *fns);
+void at91_register_uart_fns(struct at91_port_fns *fns);
-void at91_register_uart(int idx, int port);
 #else
 #define at91_register_uart_fns(fns) do { } while (0)
-#define at91_register_uart(idx,port) do { } while (0)
 #endif
diff --git a/include/asm-arm/mach/serial_sa1100.h b/include/asm-arm/mach/serial_sa1100.h
index 9162018585df..20c22bb218d9 100644
--- a/include/asm-arm/mach/serial_sa1100.h
+++ b/include/asm-arm/mach/serial_sa1100.h
@@ -7,7 +7,6 @@
 *
 * Low level machine dependent UART functions.
 */
-#include <linux/config.h>
 struct uart_port;
 struct uart_info;
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 96c6db7dd0e1..9f28073559e8 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -50,6 +50,7 @@ struct sys_timer {
 #define DYN_TICK_ENABLED        (1 << 1)
 struct dyn_tick_timer {
+        spinlock_t      lock;
        unsigned int    state;                  /* Current state */
        int             (*enable)(void);        /* Enables dynamic tick */
        int             (*disable)(void);       /* Disables dynamic tick */
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index 209289407595..731e321a57d1 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -22,7 +22,6 @@
 #define UL(x) (x)
 #endif
-#include <linux/config.h>
 #include <linux/compiler.h>
 #include <asm/arch/memory.h>
 #include <asm/sizes.h>
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index a404d2bf0c68..66cfeb5290ea 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -10,7 +10,6 @@
 #ifndef _ASMARM_PAGE_H
 #define _ASMARM_PAGE_H
-#include <linux/config.h>
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT              12
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index ead3ced38cb8..f21abd4ddac6 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -2,7 +2,6 @@
 #define ASMARM_PCI_H
 #ifdef __KERNEL__
-#include <linux/config.h>
 #include <asm-generic/pci-dma-compat.h>
 #include <asm/hardware.h> /* for PCIBIOS_MIN_* */
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 106045edb862..e9310895e79d 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -13,7 +13,6 @@
 #ifdef __KERNEL__
-#include <linux/config.h>
 /*
 * Work out if we need multiple CPU support
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index 77adb7fa169b..2bebe3dc0a30 100644
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -10,7 +10,6 @@
 #ifndef __ASM_ARM_PTRACE_H
 #define __ASM_ARM_PTRACE_H
-#include <linux/config.h>
 #define PTRACE_GETREGS          12
 #define PTRACE_SETREGS          13
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index fe45f7f61223..f67acce387e7 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -10,7 +10,6 @@
 #ifndef __ASM_ARM_SMP_H
 #define __ASM_ARM_SMP_H
-#include <linux/config.h>
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 #include <linux/thread_info.h>
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 7c9568d30307..6001febfe63b 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -3,7 +3,6 @@
 #ifdef __KERNEL__
-#include <linux/config.h>
 #define CPU_ARCH_UNKNOWN        0
 #define CPU_ARCH_ARMv3          1
@@ -108,6 +107,9 @@ extern void __show_regs(struct pt_regs *);
 extern int cpu_architecture(void);
 extern void cpu_init(void);
+void arm_machine_restart(char mode);
+extern void (*arm_pm_restart)(char str);
 /*
 * Intel's XScale3 core supports some v6 features (supersections, L2)
 * but advertises itself as v5 as it does not support the v6 ISA.  For
diff --git a/include/asm-arm/thread_notify.h b/include/asm-arm/thread_notify.h
new file mode 100644
index 000000000000..8866e5216840
--- /dev/null
+++ b/include/asm-arm/thread_notify.h
@@ -0,0 +1,48 @@
+/*
+ *  linux/include/asm-arm/thread_notify.h
+ *
+ *  Copyright (C) 2006 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_THREAD_NOTIFY_H
+#define ASMARM_THREAD_NOTIFY_H
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#include <linux/notifier.h>
+#include <asm/thread_info.h>
+static inline int thread_register_notifier(struct notifier_block *n)
+{
+        extern struct atomic_notifier_head thread_notify_head;
+        return atomic_notifier_chain_register(&thread_notify_head, n);
+}
+static inline void thread_unregister_notifier(struct notifier_block *n)
+{
+        extern struct atomic_notifier_head thread_notify_head;
+        atomic_notifier_chain_unregister(&thread_notify_head, n);
+}
+static inline void thread_notify(unsigned long rc, struct thread_info *thread)
+{
+        extern struct atomic_notifier_head thread_notify_head;
+        atomic_notifier_call_chain(&thread_notify_head, rc, thread);
+}
+#endif
+/*
+ * These are the reason codes for the thread notifier.
+ */
+#define THREAD_NOTIFY_FLUSH     0
+#define THREAD_NOTIFY_RELEASE   1
+#define THREAD_NOTIFY_SWITCH    2
+#endif
+#endif
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 728992451dd1..d97fc76189a5 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -10,7 +10,6 @@
 #ifndef _ASMARM_TLBFLUSH_H
 #define _ASMARM_TLBFLUSH_H
-#include <linux/config.h>
 #ifndef CONFIG_MMU
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index cbf39a56dbe7..1e891f860ef3 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -13,8 +13,6 @@
 #ifndef __ASM_ARM_UNISTD_H
 #define __ASM_ARM_UNISTD_H
-#include <linux/linkage.h>
 #define __NR_OABI_SYSCALL_BASE  0x900000
 #if defined(__thumb__) || defined(__ARM_EABI__)
@@ -378,6 +376,9 @@
 #undef __NR_ipc
 #endif
+#ifdef __KERNEL__
+#include <linux/linkage.h>
 #define __sys2(x) #x
 #define __sys1(x) __sys2(x)
@@ -526,7 +527,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
  __syscall_return(type,__res);                                         \
 }
-#ifdef __KERNEL__
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_GETHOSTNAME
@@ -547,7 +547,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_SYS_SOCKETCALL
 #endif
-#endif
 #ifdef __KERNEL_SYSCALLS__
@@ -571,7 +570,7 @@ asmlinkage long sys_rt_sigaction(int sig,
                                struct sigaction __user *oact,
                                size_t sigsetsize);
-#endif
+#endif /* __KERNEL_SYSCALLS__ */
 /*
 * "Conditional" syscalls
@@ -581,4 +580,5 @@ asmlinkage long sys_rt_sigaction(int sig,
 */
 #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+#endif /* __KERNEL__ */
 #endif /* __ASM_ARM_UNISTD_H */
diff --git a/include/asm-arm/vga.h b/include/asm-arm/vga.h
index 926e5ee128e9..1e0b913c3d71 100644
--- a/include/asm-arm/vga.h
+++ b/include/asm-arm/vga.h
@@ -4,7 +4,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
-#define VGA_MAP_MEM(x)  (PCIMEM_BASE + (x))
+#define VGA_MAP_MEM(x,s)        (PCIMEM_BASE + (x))
 #define vga_readb(x)    (*((volatile unsigned char *)x))
 #define vga_writeb(x,y) (*((volatile unsigned char *)y) = (x))