119 files changed, 2160 insertions, 3007 deletions
diff --git a/include/asm-arm/arch-aaec2000/dma.h b/include/asm-arm/arch-aaec2000/dma.h
index 28c890b4a1d3..e100b1e526fe 100644
--- a/include/asm-arm/arch-aaec2000/dma.h
+++ b/include/asm-arm/arch-aaec2000/dma.h
@@ -7,11 +7,3 @@
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-#define MAX_DMA_CHANNELS        0
-#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
new file mode 100644
index 000000000000..58f40931a5c1
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -0,0 +1,261 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Common definitions.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_H
+#define AT91RM9200_H
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ     0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS     1       /* System Peripheral */
+#define AT91_ID_PIOA    2       /* Parallel IO Controller A */
+#define AT91_ID_PIOB    3       /* Parallel IO Controller B */
+#define AT91_ID_PIOC    4       /* Parallel IO Controller C */
+#define AT91_ID_PIOD    5       /* Parallel IO Controller D */
+#define AT91_ID_US0     6       /* USART 0 */
+#define AT91_ID_US1     7       /* USART 1 */
+#define AT91_ID_US2     8       /* USART 2 */
+#define AT91_ID_US3     9       /* USART 3 */
+#define AT91_ID_MCI     10      /* Multimedia Card Interface */
+#define AT91_ID_UDP     11      /* USB Device Port */
+#define AT91_ID_TWI     12      /* Two-Wire Interface */
+#define AT91_ID_SPI     13      /* Serial Peripheral Interface */
+#define AT91_ID_SSC0    14      /* Serial Synchronous Controller 0 */
+#define AT91_ID_SSC1    15      /* Serial Synchronous Controller 1 */
+#define AT91_ID_SSC2    16      /* Serial Synchronous Controller 2 */
+#define AT91_ID_TC0     17      /* Timer Counter 0 */
+#define AT91_ID_TC1     18      /* Timer Counter 1 */
+#define AT91_ID_TC2     19      /* Timer Counter 2 */
+#define AT91_ID_TC3     20      /* Timer Counter 3 */
+#define AT91_ID_TC4     21      /* Timer Counter 4 */
+#define AT91_ID_TC5     22      /* Timer Counter 5 */
+#define AT91_ID_UHP     23      /* USB Host port */
+#define AT91_ID_EMAC    24      /* Ethernet MAC */
+#define AT91_ID_IRQ0    25      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91_ID_IRQ1    26      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91_ID_IRQ2    27      /* Advanced Interrupt Controller (IRQ2) */
+#define AT91_ID_IRQ3    28      /* Advanced Interrupt Controller (IRQ3) */
+#define AT91_ID_IRQ4    29      /* Advanced Interrupt Controller (IRQ4) */
+#define AT91_ID_IRQ5    30      /* Advanced Interrupt Controller (IRQ5) */
+#define AT91_ID_IRQ6    31      /* Advanced Interrupt Controller (IRQ6) */
+/*
+ * Peripheral physical base addresses.
+ */
+#define AT91_BASE_TCB0          0xfffa0000
+#define AT91_BASE_TC0           0xfffa0000
+#define AT91_BASE_TC1           0xfffa0040
+#define AT91_BASE_TC2           0xfffa0080
+#define AT91_BASE_TCB1          0xfffa4000
+#define AT91_BASE_TC3           0xfffa4000
+#define AT91_BASE_TC4           0xfffa4040
+#define AT91_BASE_TC5           0xfffa4080
+#define AT91_BASE_UDP           0xfffb0000
+#define AT91_BASE_MCI           0xfffb4000
+#define AT91_BASE_TWI           0xfffb8000
+#define AT91_BASE_EMAC          0xfffbc000
+#define AT91_BASE_US0           0xfffc0000
+#define AT91_BASE_US1           0xfffc4000
+#define AT91_BASE_US2           0xfffc8000
+#define AT91_BASE_US3           0xfffcc000
+#define AT91_BASE_SSC0          0xfffd0000
+#define AT91_BASE_SSC1          0xfffd4000
+#define AT91_BASE_SSC2          0xfffd8000
+#define AT91_BASE_SPI           0xfffe0000
+#define AT91_BASE_SYS           0xfffff000
+/*
+ * PIO pin definitions (peripheral A/B multiplexing).
+ */
+#define AT91_PA0_MISO           (1 <<  0)       /* A: SPI Master-In Slave-Out */
+#define AT91_PA0_PCK3           (1 <<  0)       /* B: PMC Programmable Clock Output 3 */
+#define AT91_PA1_MOSI           (1 <<  1)       /* A: SPI Master-Out Slave-In */
+#define AT91_PA1_PCK0           (1 <<  1)       /* B: PMC Programmable Clock Output 0 */
+#define AT91_PA2_SPCK           (1 <<  2)       /* A: SPI Serial Clock */
+#define AT91_PA2_IRQ4           (1 <<  2)       /* B: External Interrupt 4 */
+#define AT91_PA3_NPCS0          (1 <<  3)       /* A: SPI Peripheral Chip Select 0 */
+#define AT91_PA3_IRQ5           (1 <<  3)       /* B: External Interrupt 5 */
+#define AT91_PA4_NPCS1          (1 <<  4)       /* A: SPI Peripheral Chip Select 1 */
+#define AT91_PA4_PCK1           (1 <<  4)       /* B: PMC Programmable Clock Output 1 */
+#define AT91_PA5_NPCS2          (1 <<  5)       /* A: SPI Peripheral Chip Select 2 */
+#define AT91_PA5_TXD3           (1 <<  5)       /* B: USART Transmit Data 3 */
+#define AT91_PA6_NPCS3          (1 <<  6)       /* A: SPI Peripheral Chip Select 3 */
+#define AT91_PA6_RXD3           (1 <<  6)       /* B: USART Receive Data 3 */
+#define AT91_PA7_ETXCK_EREFCK   (1 <<  7)       /* A: Ethernet Reference Clock / Transmit Clock */
+#define AT91_PA7_PCK2           (1 <<  7)       /* B: PMC Programmable Clock Output 2 */
+#define AT91_PA8_ETXEN          (1 <<  8)       /* A: Ethernet Transmit Enable */
+#define AT91_PA8_MCCDB          (1 <<  8)       /* B: MMC Multimedia Card B Command */
+#define AT91_PA9_ETX0           (1 <<  9)       /* A: Ethernet Transmit Data 0 */
+#define AT91_PA9_MCDB0          (1 <<  9)       /* B: MMC Multimedia Card B Data 0 */
+#define AT91_PA10_ETX1          (1 << 10)       /* A: Ethernet Transmit Data 1 */
+#define AT91_PA10_MCDB1         (1 << 10)       /* B: MMC Multimedia Card B Data 1 */
+#define AT91_PA11_ECRS_ECRSDV   (1 << 11)       /* A: Ethernet Carrier Sense / Data Valid */
+#define AT91_PA11_MCDB2         (1 << 11)       /* B: MMC Multimedia Card B Data 2 */
+#define AT91_PA12_ERX0          (1 << 12)       /* A: Ethernet Receive Data 0 */
+#define AT91_PA12_MCDB3         (1 << 12)       /* B: MMC Multimedia Card B Data 3 */
+#define AT91_PA13_ERX1          (1 << 13)       /* A: Ethernet Receive Data 1 */
+#define AT91_PA13_TCLK0         (1 << 13)       /* B: TC External Clock Input 0 */
+#define AT91_PA14_ERXER         (1 << 14)       /* A: Ethernet Receive Error */
+#define AT91_PA14_TCLK1         (1 << 14)       /* B: TC External Clock Input 1 */
+#define AT91_PA15_EMDC          (1 << 15)       /* A: Ethernet Management Data Clock */
+#define AT91_PA15_TCLK2         (1 << 15)       /* B: TC External Clock Input 2 */
+#define AT91_PA16_EMDIO         (1 << 16)       /* A: Ethernet Management Data I/O */
+#define AT91_PA16_IRQ6          (1 << 16)       /* B: External Interrupt 6 */
+#define AT91_PA17_TXD0          (1 << 17)       /* A: USART Transmit Data 0 */
+#define AT91_PA17_TIOA0         (1 << 17)       /* B: TC I/O Line A 0 */
+#define AT91_PA18_RXD0          (1 << 18)       /* A: USART Receive Data 0 */
+#define AT91_PA18_TIOB0         (1 << 18)       /* B: TC I/O Line B 0 */
+#define AT91_PA19_SCK0          (1 << 19)       /* A: USART Serial Clock 0 */
+#define AT91_PA19_TIOA1         (1 << 19)       /* B: TC I/O Line A 1 */
+#define AT91_PA20_CTS0          (1 << 20)       /* A: USART Clear To Send 0 */
+#define AT91_PA20_TIOB1         (1 << 20)       /* B: TC I/O Line B 1 */
+#define AT91_PA21_RTS0          (1 << 21)       /* A: USART Ready To Send 0 */
+#define AT91_PA21_TIOA2         (1 << 21)       /* B: TC I/O Line A 2 */
+#define AT91_PA22_RXD2          (1 << 22)       /* A: USART Receive Data 2 */
+#define AT91_PA22_TIOB2         (1 << 22)       /* B: TC I/O Line B 2 */
+#define AT91_PA23_TXD2          (1 << 23)       /* A: USART Transmit Data 2 */
+#define AT91_PA23_IRQ3          (1 << 23)       /* B: External Interrupt 3 */
+#define AT91_PA24_SCK2          (1 << 24)       /* A: USART Serial Clock 2 */
+#define AT91_PA24_PCK1          (1 << 24)       /* B: PMC Programmable Clock Output 1 */
+#define AT91_PA25_TWD           (1 << 25)       /* A: TWI Two-wire Serial Data */
+#define AT91_PA25_IRQ2          (1 << 25)       /* B: External Interrupt 2 */
+#define AT91_PA26_TWCK          (1 << 26)       /* A: TWI Two-wire Serial Clock */
+#define AT91_PA26_IRQ1          (1 << 26)       /* B: External Interrupt 1 */
+#define AT91_PA27_MCCK          (1 << 27)       /* A: MMC Multimedia Card Clock */
+#define AT91_PA27_TCLK3         (1 << 27)       /* B: TC External Clock Input 3 */
+#define AT91_PA28_MCCDA         (1 << 28)       /* A: MMC Multimedia Card A Command */
+#define AT91_PA28_TCLK4         (1 << 28)       /* B: TC External Clock Input 4 */
+#define AT91_PA29_MCDA0         (1 << 29)       /* A: MMC Multimedia Card A Data 0 */
+#define AT91_PA29_TCLK5         (1 << 29)       /* B: TC External Clock Input 5 */
+#define AT91_PA30_DRXD          (1 << 30)       /* A: DBGU Receive Data */
+#define AT91_PA30_CTS2          (1 << 30)       /* B: USART Clear To Send 2 */
+#define AT91_PA31_DTXD          (1 << 31)       /* A: DBGU Transmit Data */
+#define AT91_PA31_RTS2          (1 << 31)       /* B: USART Ready To Send 2 */
+#define AT91_PB0_TF0            (1 <<  0)       /* A: SSC Transmit Frame Sync 0 */
+#define AT91_PB0_RTS3           (1 <<  0)       /* B: USART Ready To Send 3 */
+#define AT91_PB1_TK0            (1 <<  1)       /* A: SSC Transmit Clock 0 */
+#define AT91_PB1_CTS3           (1 <<  1)       /* B: USART Clear To Send 3 */
+#define AT91_PB2_TD0            (1 <<  2)       /* A: SSC Transmit Data 0 */
+#define AT91_PB2_SCK3           (1 <<  2)       /* B: USART Serial Clock 3 */
+#define AT91_PB3_RD0            (1 <<  3)       /* A: SSC Receive Data 0 */
+#define AT91_PB3_MCDA1          (1 <<  3)       /* B: MMC Multimedia Card A Data 1 */
+#define AT91_PB4_RK0            (1 <<  4)       /* A: SSC Receive Clock 0 */
+#define AT91_PB4_MCDA2          (1 <<  4)       /* B: MMC Multimedia Card A Data 2 */
+#define AT91_PB5_RF0            (1 <<  5)       /* A: SSC Receive Frame Sync 0 */
+#define AT91_PB5_MCDA3          (1 <<  5)       /* B: MMC Multimedia Card A Data 3 */
+#define AT91_PB6_TF1            (1 <<  6)       /* A: SSC Transmit Frame Sync 1 */
+#define AT91_PB6_TIOA3          (1 <<  6)       /* B: TC I/O Line A 3 */
+#define AT91_PB7_TK1            (1 <<  7)       /* A: SSC Transmit Clock 1 */
+#define AT91_PB7_TIOB3          (1 <<  7)       /* B: TC I/O Line B 3 */
+#define AT91_PB8_TD1            (1 <<  8)       /* A: SSC Transmit Data 1 */
+#define AT91_PB8_TIOA4          (1 <<  8)       /* B: TC I/O Line A 4 */
+#define AT91_PB9_RD1            (1 <<  9)       /* A: SSC Receive Data 1 */
+#define AT91_PB9_TIOB4          (1 <<  9)       /* B: TC I/O Line B 4 */
+#define AT91_PB10_RK1           (1 << 10)       /* A: SSC Receive Clock 1 */
+#define AT91_PB10_TIOA5         (1 << 10)       /* B: TC I/O Line A 5 */
+#define AT91_PB11_RF1           (1 << 11)       /* A: SSC Receive Frame Sync 1 */
+#define AT91_PB11_TIOB5         (1 << 11)       /* B: TC I/O Line B 5 */
+#define AT91_PB12_TF2           (1 << 12)       /* A: SSC Transmit Frame Sync 2 */
+#define AT91_PB12_ETX2          (1 << 12)       /* B: Ethernet Transmit Data 2 */
+#define AT91_PB13_TK2           (1 << 13)       /* A: SSC Transmit Clock 3 */
+#define AT91_PB13_ETX3          (1 << 13)       /* B: Ethernet Transmit Data 3 */
+#define AT91_PB14_TD2           (1 << 14)       /* A: SSC Transmit Data 2 */
+#define AT91_PB14_ETXER         (1 << 14)       /* B: Ethernet Transmit Coding Error */
+#define AT91_PB15_RD2           (1 << 15)       /* A: SSC Receive Data 2 */
+#define AT91_PB15_ERX2          (1 << 15)       /* B: Ethernet Receive Data 2 */
+#define AT91_PB16_RK2           (1 << 16)       /* A: SSC Receive Clock 2 */
+#define AT91_PB16_ERX3          (1 << 16)       /* B: Ethernet Receive Data 3 */
+#define AT91_PB17_RF2           (1 << 17)       /* A: SSC Receive Frame Sync 2 */
+#define AT91_PB17_ERXDV         (1 << 17)       /* B: Ethernet Receive Data Valid */
+#define AT91_PB18_RI1           (1 << 18)       /* A: USART Ring Indicator 1 */
+#define AT91_PB18_ECOL          (1 << 18)       /* B: Ethernet Collision Detected */
+#define AT91_PB19_DTR1          (1 << 19)       /* A: USART Data Terminal Ready 1 */
+#define AT91_PB19_ERXCK         (1 << 19)       /* B: Ethernet Receive Clock */
+#define AT91_PB20_TXD1          (1 << 20)       /* A: USART Transmit Data 1 */
+#define AT91_PB21_RXD1          (1 << 21)       /* A: USART Receive Data 1 */
+#define AT91_PB22_SCK1          (1 << 22)       /* A: USART Serial Clock 1 */
+#define AT91_PB23_DCD1          (1 << 23)       /* A: USART Data Carrier Detect 1 */
+#define AT91_PB24_CTS1          (1 << 24)       /* A: USART Clear To Send 1 */
+#define AT91_PB25_DSR1          (1 << 25)       /* A: USART Data Set Ready 1 */
+#define AT91_PB25_EF100         (1 << 25)       /* B: Ethernet Force 100 Mbit */
+#define AT91_PB26_RTS1          (1 << 26)       /* A: USART Ready To Send 1 */
+#define AT91_PB27_PCK0          (1 << 27)       /* B: PMC Programmable Clock Output 0 */
+#define AT91_PB28_FIQ           (1 << 28)       /* A: Fast Interrupt */
+#define AT91_PB29_IRQ0          (1 << 29)       /* A: External Interrupt 0 */
+#define AT91_PC0_BFCK           (1 <<  0)       /* A: Burst Flash Clock */
+#define AT91_PC1_BFRDY_SMOE     (1 <<  1)       /* A: Burst Flash Ready / SmartMedia Output Enable */
+#define AT91_PC2_BFAVD          (1 <<  2)       /* A: Burst Flash Address Valid */
+#define AT91_PC3_BFBAA_SMWE     (1 <<  3)       /* A: Burst Flash Address Advance / SmartMedia Write Enable */
+#define AT91_PC4_BFOE           (1 <<  4)       /* A: Burst Flash Output Enable */
+#define AT91_PC5_BFWE           (1 <<  5)       /* A: Burst Flash Write Enable */
+#define AT91_PC6_NWAIT          (1 <<  6)       /* A: SMC Wait Signal */
+#define AT91_PC7_A23            (1 <<  7)       /* A: Address Bus 23 */
+#define AT91_PC8_A24            (1 <<  8)       /* A: Address Bus 24 */
+#define AT91_PC9_A25_CFRNW      (1 <<  9)       /* A: Address Bus 25 / Compact Flash Read Not Write */
+#define AT91_PC10_NCS4_CFCS     (1 << 10)       /* A: SMC Chip Select 4 / Compact Flash Chip Select */
+#define AT91_PC11_NCS5_CFCE1    (1 << 11)       /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
+#define AT91_PC12_NCS6_CFCE2    (1 << 12)       /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
+#define AT91_PC13_NCS7          (1 << 13)       /* A: Chip Select 7 */
+#define AT91_PD0_ETX0           (1 <<  0)       /* A: Ethernet Transmit Data 0 */
+#define AT91_PD1_ETX1           (1 <<  1)       /* A: Ethernet Transmit Data 1 */
+#define AT91_PD2_ETX2           (1 <<  2)       /* A: Ethernet Transmit Data 2 */
+#define AT91_PD3_ETX3           (1 <<  3)       /* A: Ethernet Transmit Data 3 */
+#define AT91_PD4_ETXEN          (1 <<  4)       /* A: Ethernet Transmit Enable */
+#define AT91_PD5_ETXER          (1 <<  5)       /* A: Ethernet Transmit Coding Error */
+#define AT91_PD6_DTXD           (1 <<  6)       /* A: DBGU Transmit Data */
+#define AT91_PD7_PCK0           (1 <<  7)       /* A: PMC Programmable Clock Output 0 */
+#define AT91_PD7_TSYNC          (1 <<  7)       /* B: ETM Trace Synchronization Signal */
+#define AT91_PD8_PCK1           (1 <<  8)       /* A: PMC Programmable Clock Output 1 */
+#define AT91_PD8_TCLK           (1 <<  8)       /* B: ETM Trace Clock */
+#define AT91_PD9_PCK2           (1 <<  9)       /* A: PMC Programmable Clock Output 2 */
+#define AT91_PD9_TPS0           (1 <<  9)       /* B: ETM Trace ARM Pipeline Status 0 */
+#define AT91_PD10_PCK3          (1 << 10)       /* A: PMC Programmable Clock Output 3 */
+#define AT91_PD10_TPS1          (1 << 10)       /* B: ETM Trace ARM Pipeline Status 1 */
+#define AT91_PD11_TPS2          (1 << 11)       /* B: ETM Trace ARM Pipeline Status 2 */
+#define AT91_PD12_TPK0          (1 << 12)       /* B: ETM Trace Packet Port 0 */
+#define AT91_PD13_TPK1          (1 << 13)       /* B: ETM Trace Packet Port 1 */
+#define AT91_PD14_TPK2          (1 << 14)       /* B: ETM Trace Packet Port 2 */
+#define AT91_PD15_TD0           (1 << 15)       /* A: SSC Transmit Data 0 */
+#define AT91_PD15_TPK3          (1 << 15)       /* B: ETM Trace Packet Port 3 */
+#define AT91_PD16_TD1           (1 << 16)       /* A: SSC Transmit Data 1 */
+#define AT91_PD16_TPK4          (1 << 16)       /* B: ETM Trace Packet Port 4 */
+#define AT91_PD17_TD2           (1 << 17)       /* A: SSC Transmit Data 2 */
+#define AT91_PD17_TPK5          (1 << 17)       /* B: ETM Trace Packet Port 5 */
+#define AT91_PD18_NPCS1         (1 << 18)       /* A: SPI Peripheral Chip Select 1 */
+#define AT91_PD18_TPK6          (1 << 18)       /* B: ETM Trace Packet Port 6 */
+#define AT91_PD19_NPCS2         (1 << 19)       /* A: SPI Peripheral Chip Select 2 */
+#define AT91_PD19_TPK7          (1 << 19)       /* B: ETM Trace Packet Port 7 */
+#define AT91_PD20_NPCS3         (1 << 20)       /* A: SPI Peripheral Chip Select 3 */
+#define AT91_PD20_TPK8          (1 << 20)       /* B: ETM Trace Packet Port 8 */
+#define AT91_PD21_RTS0          (1 << 21)       /* A: USART Ready To Send 0 */
+#define AT91_PD21_TPK9          (1 << 21)       /* B: ETM Trace Packet Port 9 */
+#define AT91_PD22_RTS1          (1 << 22)       /* A: USART Ready To Send 1 */
+#define AT91_PD22_TPK10         (1 << 22)       /* B: ETM Trace Packet Port 10 */
+#define AT91_PD23_RTS2          (1 << 23)       /* A: USART Ready To Send 2 */
+#define AT91_PD23_TPK11         (1 << 23)       /* B: ETM Trace Packet Port 11 */
+#define AT91_PD24_RTS3          (1 << 24)       /* A: USART Ready To Send 3 */
+#define AT91_PD24_TPK12         (1 << 24)       /* B: ETM Trace Packet Port 12 */
+#define AT91_PD25_DTR1          (1 << 25)       /* A: USART Data Terminal Ready 1 */
+#define AT91_PD25_TPK13         (1 << 25)       /* B: ETM Trace Packet Port 13 */
+#define AT91_PD26_TPK14         (1 << 26)       /* B: ETM Trace Packet Port 14 */
+#define AT91_PD27_TPK15         (1 << 27)       /* B: ETM Trace Packet Port 15 */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
new file mode 100644
index 000000000000..ce1150d4438d
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Peripheral Data Controller (PDC) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_PDC_H
+#define AT91RM9200_PDC_H
+#define AT91_PDC_RPR            0x100   /* Receive Pointer Register */
+#define AT91_PDC_RCR            0x104   /* Receive Counter Register */
+#define AT91_PDC_TPR            0x108   /* Transmit Pointer Register */
+#define AT91_PDC_TCR            0x10c   /* Transmit Counter Register */
+#define AT91_PDC_RNPR           0x110   /* Receive Next Pointer Register */
+#define AT91_PDC_RNCR           0x114   /* Receive Next Counter Register */
+#define AT91_PDC_TNPR           0x118   /* Transmit Next Pointer Register */
+#define AT91_PDC_TNCR           0x11c   /* Transmit Next Counter Register */
+#define AT91_PDC_PTCR           0x120   /* Transfer Control Register */
+#define         AT91_PDC_RXTEN          (1 << 0)        /* Receiver Transfer Enable */
+#define         AT91_PDC_RXTDIS         (1 << 1)        /* Receiver Transfer Disable */
+#define         AT91_PDC_TXTEN          (1 << 8)        /* Transmitter Transfer Enable */
+#define         AT91_PDC_TXTDIS         (1 << 9)        /* Transmitter Transfer Disable */
+#define AT91_PDC_PTSR           0x124   /* Transfer Status Register */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
new file mode 100644
index 000000000000..9bfffdbf1e0b
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -0,0 +1,328 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_SYS_H
+#define AT91RM9200_SYS_H
+/*
+ * Advanced Interrupt Controller.
+ */
+#define AT91_AIC        0x000
+#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
+#define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
+#define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
+#define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
+#define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
+#define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
+#define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
+#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
+#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
+#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
+#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
+#define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
+#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
+#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
+#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
+#define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
+#define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
+#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
+#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
+#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
+#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
+#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
+#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
+#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
+#define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
+#define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
+/*
+ * Debug Unit.
+ */
+#define AT91_DBGU       0x200
+#define AT91_DBGU_CR            (AT91_DBGU + 0x00)      /* Control Register */
+#define AT91_DBGU_MR            (AT91_DBGU + 0x04)      /* Mode Register */
+#define AT91_DBGU_IER           (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
+#define         AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
+#define         AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
+#define AT91_DBGU_IDR           (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
+#define AT91_DBGU_IMR           (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
+#define AT91_DBGU_SR            (AT91_DBGU + 0x14)      /* Status Register */
+#define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
+#define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
+#define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
+#define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
+#define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
+/*
+ * PIO Controllers.
+ */
+#define AT91_PIOA       0x400
+#define AT91_PIOB       0x600
+#define AT91_PIOC       0x800
+#define AT91_PIOD       0xa00
+#define PIO_PER         0x00    /* Enable Register */
+#define PIO_PDR         0x04    /* Disable Register */
+#define PIO_PSR         0x08    /* Status Register */
+#define PIO_OER         0x10    /* Output Enable Register */
+#define PIO_ODR         0x14    /* Output Disable Register */
+#define PIO_OSR         0x18    /* Output Status Register */
+#define PIO_IFER        0x20    /* Glitch Input Filter Enable */
+#define PIO_IFDR        0x24    /* Glitch Input Filter Disable */
+#define PIO_IFSR        0x28    /* Glitch Input Filter Status */
+#define PIO_SODR        0x30    /* Set Output Data Register */
+#define PIO_CODR        0x34    /* Clear Output Data Register */
+#define PIO_ODSR        0x38    /* Output Data Status Register */
+#define PIO_PDSR        0x3c    /* Pin Data Status Register */
+#define PIO_IER         0x40    /* Interrupt Enable Register */
+#define PIO_IDR         0x44    /* Interrupt Disable Register */
+#define PIO_IMR         0x48    /* Interrupt Mask Register */
+#define PIO_ISR         0x4c    /* Interrupt Status Register */
+#define PIO_MDER        0x50    /* Multi-driver Enable Register */
+#define PIO_MDDR        0x54    /* Multi-driver Disable Register */
+#define PIO_MDSR        0x58    /* Multi-driver Status Register */
+#define PIO_PUDR        0x60    /* Pull-up Disable Register */
+#define PIO_PUER        0x64    /* Pull-up Enable Register */
+#define PIO_PUSR        0x68    /* Pull-up Status Register */
+#define PIO_ASR         0x70    /* Peripheral A Select Register */
+#define PIO_BSR         0x74    /* Peripheral B Select Register */
+#define PIO_ABSR        0x78    /* AB Status Register */
+#define PIO_OWER        0xa0    /* Output Write Enable Register */
+#define PIO_OWDR        0xa4    /* Output Write Disable Register */
+#define PIO_OWSR        0xa8    /* Output Write Status Register */
+#define AT91_PIO_P(n)   (1 << (n))
+/*
+ * Power Management Controller.
+ */
+#define AT91_PMC        0xc00
+#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
+#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
+#define         AT91_PMC_UDP            (1 <<  1)               /* USB Devcice Port Clock */
+#define         AT91_PMC_MCKUDP         (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend */
+#define         AT91_PMC_UHP            (1 <<  4)               /* USB Host Port Clock */
+#define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
+#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
+#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
+#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
+#define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
+#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
+#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
+#define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
+#define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
+#define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
+#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
+#define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
+#define                 AT91_PMC_CSS_SLOW               (0 << 0)
+#define                 AT91_PMC_CSS_MAIN               (1 << 0)
+#define                 AT91_PMC_CSS_PLLA               (2 << 0)
+#define                 AT91_PMC_CSS_PLLB               (3 << 0)
+#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
+#define                 AT91_PMC_PRES_1                 (0 << 2)
+#define                 AT91_PMC_PRES_2                 (1 << 2)
+#define                 AT91_PMC_PRES_4                 (2 << 2)
+#define                 AT91_PMC_PRES_8                 (3 << 2)
+#define                 AT91_PMC_PRES_16                (4 << 2)
+#define                 AT91_PMC_PRES_32                (5 << 2)
+#define                 AT91_PMC_PRES_64                (6 << 2)
+#define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
+#define                 AT91_PMC_MDIV_1                 (0 << 8)
+#define                 AT91_PMC_MDIV_2                 (1 << 8)
+#define                 AT91_PMC_MDIV_3                 (2 << 8)
+#define                 AT91_PMC_MDIV_4                 (3 << 8)
+#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
+#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
+#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
+#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
+#define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
+#define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
+#define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
+#define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
+#define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
+#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
+/*
+ * System Timer.
+ */
+#define AT91_ST         0xd00
+#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
+#define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
+#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
+#define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
+#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
+#define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
+#define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
+#define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
+#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
+#define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
+#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
+#define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
+#define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
+#define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
+#define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
+#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
+#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
+#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
+#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
+#define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
+#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
+#define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
+/*
+ * Real-time Clock.
+ */
+#define AT91_RTC        0xe00
+#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
+#define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
+#define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
+#define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
+#define                 AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
+#define                 AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
+#define         AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
+#define                 AT91_RTC_CALEVSEL_WEEK          (0 << 16)
+#define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
+#define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
+#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
+#define         AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
+#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
+#define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
+#define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
+#define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
+#define         At91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
+#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
+#define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
+#define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
+#define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
+#define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
+#define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
+#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
+#define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
+#define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
+#define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
+#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
+#define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
+#define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
+#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
+#define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
+#define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
+#define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
+#define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
+#define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
+#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
+#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
+#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
+#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
+#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
+#define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
+#define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
+#define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
+#define         AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
+/*
+ * Memory Controller.
+ */
+#define AT91_MC         0xf00
+#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
+#define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
+#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
+#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
+#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
+/* External Bus Interface (EBI) registers */
+#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
+#define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
+#define                 AT91_EBI_CS0A_SMC               (0 << 0)
+#define                 AT91_EBI_CS0A_BFC               (1 << 0)
+#define         AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
+#define                 AT91_EBI_CS1A_SMC               (0 << 1)
+#define                 AT91_EBI_CS1A_SDRAMC            (1 << 1)
+#define         AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
+#define                 AT91_EBI_CS3A_SMC               (0 << 3)
+#define                 AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
+#define         AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
+#define                 AT91_EBI_CS4A_SMC               (0 << 4)
+#define                 AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
+#define AT91_EBI_CFGR           (AT91_MC + 0x64)        /* Configuration Register */
+#define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
+#define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
+#define         AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
+#define         AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
+#define         AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
+#define                 AT91_SMC_DBW_16         (1 << 13)
+#define                 AT91_SMC_DBW_8          (2 << 13)
+#define         AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
+#define         AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
+#define                 AT91_SMC_ACSS_STD       (0 << 16)
+#define                 AT91_SMC_ACSS_1         (1 << 16)
+#define                 AT91_SMC_ACSS_2         (2 << 16)
+#define                 AT91_SMC_ACSS_3         (3 << 16)
+#define         AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
+#define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_usart.h b/include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
new file mode 100644
index 000000000000..79f851e31b9c
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
@@ -0,0 +1,123 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * USART registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_USART_H
+#define AT91RM9200_USART_H
+#define AT91_US_CR              0x00                    /* Control Register */
+#define         AT91_US_RSTRX           (1 <<  2)               /* Reset Receiver */
+#define         AT91_US_RSTTX           (1 <<  3)               /* Reset Transmitter */
+#define         AT91_US_RXEN            (1 <<  4)               /* Receiver Enable */
+#define         AT91_US_RXDIS           (1 <<  5)               /* Receiver Disable */
+#define         AT91_US_TXEN            (1 <<  6)               /* Transmitter Enable */
+#define         AT91_US_TXDIS           (1 <<  7)               /* Transmitter Disable */
+#define         AT91_US_RSTSTA          (1 <<  8)               /* Reset Status Bits */
+#define         AT91_US_STTBRK          (1 <<  9)               /* Start Break */
+#define         AT91_US_STPBRK          (1 << 10)               /* Stop Break */
+#define         AT91_US_STTTO           (1 << 11)               /* Start Time-out */
+#define         AT91_US_SENDA           (1 << 12)               /* Send Address */
+#define         AT91_US_RSTIT           (1 << 13)               /* Reset Iterations */
+#define         AT91_US_RSTNACK         (1 << 14)               /* Reset Non Acknowledge */
+#define         AT91_US_RETTO           (1 << 15)               /* Rearm Time-out */
+#define         AT91_US_DTREN           (1 << 16)               /* Data Terminal Ready Enable */
+#define         AT91_US_DTRDIS          (1 << 17)               /* Data Terminal Ready Disable */
+#define         AT91_US_RTSEN           (1 << 18)               /* Request To Send Enable */
+#define         AT91_US_RTSDIS          (1 << 19)               /* Request To Send Disable */
+#define AT91_US_MR              0x04                    /* Mode Register */
+#define         AT91_US_USMODE          (0xf <<  0)             /* Mode of the USART */
+#define                 AT91_US_USMODE_NORMAL           0
+#define                 AT91_US_USMODE_RS485            1
+#define                 AT91_US_USMODE_HWHS             2
+#define                 AT91_US_USMODE_MODEM            3
+#define                 AT91_US_USMODE_ISO7816_T0       4
+#define                 AT91_US_USMODE_ISO7816_T1       6
+#define                 AT91_US_USMODE_IRDA             8
+#define         AT91_US_USCLKS          (3   <<  4)             /* Clock Selection */
+#define         AT91_US_CHRL            (3   <<  6)             /* Character Length */
+#define                 AT91_US_CHRL_5                  (0 <<  6)
+#define                 AT91_US_CHRL_6                  (1 <<  6)
+#define                 AT91_US_CHRL_7                  (2 <<  6)
+#define                 AT91_US_CHRL_8                  (3 <<  6)
+#define         AT91_US_SYNC            (1 <<  8)               /* Synchronous Mode Select */
+#define         AT91_US_PAR             (7 <<  9)               /* Parity Type */
+#define                 AT91_US_PAR_EVEN                (0 <<  9)
+#define                 AT91_US_PAR_ODD                 (1 <<  9)
+#define                 AT91_US_PAR_SPACE               (2 <<  9)
+#define                 AT91_US_PAR_MARK                (3 <<  9)
+#define                 AT91_US_PAR_NONE                (4 <<  9)
+#define                 AT91_US_PAR_MULTI_DROP          (6 <<  9)
+#define         AT91_US_NBSTOP          (3 << 12)               /* Number of Stop Bits */
+#define                 AT91_US_NBSTOP_1                (0 << 12)
+#define                 AT91_US_NBSTOP_1_5              (1 << 12)
+#define                 AT91_US_NBSTOP_2                (2 << 12)
+#define         AT91_US_CHMODE          (3 << 14)               /* Channel Mode */
+#define                 AT91_US_CHMODE_NORMAL           (0 << 14)
+#define                 AT91_US_CHMODE_ECHO             (1 << 14)
+#define                 AT91_US_CHMODE_LOC_LOOP         (2 << 14)
+#define                 AT91_US_CHMODE_REM_LOOP         (3 << 14)
+#define         AT91_US_MSBF            (1 << 16)               /* Bit Order */
+#define         AT91_US_MODE9           (1 << 17)               /* 9-bit Character Length */
+#define         AT91_US_CLKO            (1 << 18)               /* Clock Output Select */
+#define         AT91_US_OVER            (1 << 19)               /* Oversampling Mode */
+#define         AT91_US_INACK           (1 << 20)               /* Inhibit Non Acknowledge */
+#define         AT91_US_DSNACK          (1 << 21)               /* Disable Successive NACK */
+#define         AT91_US_MAX_ITER        (7 << 24)               /* Max Iterations */
+#define         AT91_US_FILTER          (1 << 28)               /* Infrared Receive Line Filter */
+#define AT91_US_IER             0x08                    /* Interrupt Enable Register */
+#define         AT91_US_RXRDY           (1 <<  0)               /* Receiver Ready */
+#define         AT91_US_TXRDY           (1 <<  1)               /* Transmitter Ready */
+#define         AT91_US_RXBRK           (1 <<  2)               /* Break Received / End of Break */
+#define         AT91_US_ENDRX           (1 <<  3)               /* End of Receiver Transfer */
+#define         AT91_US_ENDTX           (1 <<  4)               /* End of Transmitter Transfer */
+#define         AT91_US_OVRE            (1 <<  5)               /* Overrun Error */
+#define         AT91_US_FRAME           (1 <<  6)               /* Framing Error */
+#define         AT91_US_PARE            (1 <<  7)               /* Parity Error */
+#define         AT91_US_TIMEOUT         (1 <<  8)               /* Receiver Time-out */
+#define         AT91_US_TXEMPTY         (1 <<  9)               /* Transmitter Empty */
+#define         AT91_US_ITERATION       (1 << 10)               /* Max number of Repetitions Reached */
+#define         AT91_US_TXBUFE          (1 << 11)               /* Transmission Buffer Empty */
+#define         AT91_US_RXBUFF          (1 << 12)               /* Reception Buffer Full */
+#define         AT91_US_NACK            (1 << 13)               /* Non Acknowledge */
+#define         AT91_US_RIIC            (1 << 16)               /* Ring Indicator Input Change */
+#define         AT91_US_DSRIC           (1 << 17)               /* Data Set Ready Input Change */
+#define         AT91_US_DCDIC           (1 << 18)               /* Data Carrier Detect Input Change */
+#define         AT91_US_CTSIC           (1 << 19)               /* Clear to Send Input Change */
+#define         AT91_US_RI              (1 << 20)               /* RI */
+#define         AT91_US_DSR             (1 << 21)               /* DSR */
+#define         AT91_US_DCD             (1 << 22)               /* DCD */
+#define         AT91_US_CTS             (1 << 23)               /* CTS */
+#define AT91_US_IDR             0x0c                    /* Interrupt Disable Register */
+#define AT91_US_IMR             0x10                    /* Interrupt Mask Register */
+#define AT91_US_CSR             0x14                    /* Channel Status Register */
+#define AT91_US_RHR             0x18                    /* Receiver Holding Register */
+#define AT91_US_THR             0x1c                    /* Transmitter Holding Register */
+#define AT91_US_BRGR            0x20                    /* Baud Rate Generator Register */
+#define         AT91_US_CD              (0xffff << 0)           /* Clock Divider */
+#define AT91_US_RTOR            0x24                    /* Receiver Time-out Register */
+#define         AT91_US_TO              (0xffff << 0)           /* Time-out Value */
+#define AT91_US_TTGR            0x28                    /* Transmitter Timeguard Register */
+#define         AT91_US_TG              (0xff << 0)             /* Timeguard Value */
+#define AT91_US_FIDI            0x40                    /* FI DI Ratio Register */
+#define AT91_US_NER             0x44                    /* Number of Errors Register */
+#define AT91_US_IF              0x4c                    /* IrDA Filter Register */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
new file mode 100644
index 000000000000..2e7d1139a799
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -0,0 +1,80 @@
+/*
+ * include/asm-arm/arch-at91rm9200/board.h
+ *
+ *  Copyright (C) 2005 HP Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/*
+ * These are data structures found in platform_device.dev.platform_data,
+ * and describing board-specfic data needed by drivers.  For example,
+ * which pin is used for a given GPIO role.
+ *
+ * In 2.6, drivers should strongly avoid board-specific knowledge so
+ * that supporting new boards normally won't require driver patches.
+ * Most board-specific knowledge should be in arch/.../board-*.c files.
+ */
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+ /* Clocks */
+extern unsigned long at91_master_clock;
+ /* Serial Port */
+extern int at91_serial_map[AT91_NR_UART];
+extern int at91_console_port;
+ /* USB Device */
+struct at91_udc_data {
+        u8      vbus_pin;               /* high == host powering us */
+        u8      pullup_pin;             /* high == D+ pulled up */
+};
+extern void __init at91_add_device_udc(struct at91_udc_data *data);
+ /* Compact Flash */
+struct at91_cf_data {
+        u8      irq_pin;                /* I/O IRQ */
+        u8      det_pin;                /* Card detect */
+        u8      vcc_pin;                /* power switching */
+        u8      rst_pin;                /* card reset */
+};
+extern void __init at91_add_device_cf(struct at91_cf_data *data);
+ /* MMC / SD */
+struct at91_mmc_data {
+        u8              det_pin;        /* card detect IRQ */
+        unsigned        is_b:1;         /* uses B side (vs A) */
+        unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
+        u8              wp_pin;         /* (SD) writeprotect detect */
+        u8              vcc_pin;        /* power switching (high == on) */
+};
+extern void __init at91_add_device_mmc(struct at91_mmc_data *data);
+ /* Ethernet */
+struct at91_eth_data {
+        u8              phy_irq_pin;    /* PHY IRQ */
+        u8              is_rmii;        /* using RMII interface? */
+};
+extern void __init at91_add_device_eth(struct at91_eth_data *data);
+ /* USB Host */
+struct at91_usbh_data {
+        u8              ports;          /* number of ports on root hub */
+};
+extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S
new file mode 100644
index 000000000000..f496b54c4c3e
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/debug-macro.S
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-at91rm9200/debug-macro.S
+ *
+ *  Copyright (C) 2003-2005 SAN People
+ *
+ * Debugging macro include header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <asm/hardware.h>
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                         @ MMU enabled?
+        ldreq   \rx, =AT91_BASE_SYS             @ System peripherals (phys address)
+        ldrne   \rx, =AT91_VA_BASE_SYS          @ System peripherals (virt address)
+        .endm
+        .macro  senduart,rd,rx
+        strb    \rd, [\rx, #AT91_DBGU_THR]      @ Write to Transmitter Holding Register
+        .endm
+        .macro  waituart,rd,rx
+1001:   ldr     \rd, [\rx, #AT91_DBGU_SR]       @ Read Status Register
+        tst     \rd, #AT91_DBGU_TXRDY           @ DBGU_TXRDY = 1 when ready to transmit
+        beq     1001b
+        .endm
+        .macro  busyuart,rd,rx
+1001:   ldr     \rd, [\rx, #AT91_DBGU_SR]       @ Read Status Register
+        tst     \rd, #AT91_DBGU_TXEMPTY         @ DBGU_TXEMPTY = 1 when transmission complete
+        beq     1001b
+        .endm
diff --git a/include/asm-arm/arch-epxa10db/param.h b/include/asm-arm/arch-at91rm9200/dma.h
index 783dedd71c8f..22c1dfdd8da3 100644
--- a/include/asm-arm/arch-epxa10db/param.h
+++ b/include/asm-arm/arch-at91rm9200/dma.h
@@ -1,7 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10db/param.h
+ * include/asm-arm/arch-at91rm9200/dma.h
 *
- *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2003 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S
new file mode 100644
index 000000000000..61a326e94909
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/entry-macro.S
@@ -0,0 +1,25 @@
+/*
+ * include/asm-arm/arch-at91rm9200/entry-macro.S
+ *
+ *  Copyright (C) 2003-2005 SAN People
+ *
+ * Low-level IRQ helper macros for AT91RM9200 platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/hardware.h>
+        .macro  disable_fiq
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \base, =(AT91_VA_BASE_SYS)              @ base virtual address of SYS peripherals
+        ldr     \irqnr, [\base, #AT91_AIC_IVR]          @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
+        ldr     \irqstat, [\base, #AT91_AIC_ISR]        @ read interrupt source number
+        teq     \irqstat, #0                            @ ISR is 0 when no current interrupt, or spurious interrupt
+        streq   \tmp, [\base, #AT91_AIC_EOICR]          @ not going to be handled further, then ACK it now.
+        .endm
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
new file mode 100644
index 000000000000..0f0a61e2f129
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -0,0 +1,193 @@
+/*
+ * include/asm-arm/arch-at91rm9200/gpio.h
+ *
+ *  Copyright (C) 2005 HP Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
+#define __ASM_ARCH_AT91RM9200_GPIO_H
+#define PIN_BASE                NR_AIC_IRQS
+#define PQFP_GPIO_BANKS         3       /* PQFP package has 3 banks */
+#define BGA_GPIO_BANKS          4       /* BGA package has 4 banks */
+/* these pin numbers double as IRQ numbers, like AT91_ID_* values */
+#define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
+#define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
+#define AT91_PIN_PA2    (PIN_BASE + 0x00 + 2)
+#define AT91_PIN_PA3    (PIN_BASE + 0x00 + 3)
+#define AT91_PIN_PA4    (PIN_BASE + 0x00 + 4)
+#define AT91_PIN_PA5    (PIN_BASE + 0x00 + 5)
+#define AT91_PIN_PA6    (PIN_BASE + 0x00 + 6)
+#define AT91_PIN_PA7    (PIN_BASE + 0x00 + 7)
+#define AT91_PIN_PA8    (PIN_BASE + 0x00 + 8)
+#define AT91_PIN_PA9    (PIN_BASE + 0x00 + 9)
+#define AT91_PIN_PA10   (PIN_BASE + 0x00 + 10)
+#define AT91_PIN_PA11   (PIN_BASE + 0x00 + 11)
+#define AT91_PIN_PA12   (PIN_BASE + 0x00 + 12)
+#define AT91_PIN_PA13   (PIN_BASE + 0x00 + 13)
+#define AT91_PIN_PA14   (PIN_BASE + 0x00 + 14)
+#define AT91_PIN_PA15   (PIN_BASE + 0x00 + 15)
+#define AT91_PIN_PA16   (PIN_BASE + 0x00 + 16)
+#define AT91_PIN_PA17   (PIN_BASE + 0x00 + 17)
+#define AT91_PIN_PA18   (PIN_BASE + 0x00 + 18)
+#define AT91_PIN_PA19   (PIN_BASE + 0x00 + 19)
+#define AT91_PIN_PA20   (PIN_BASE + 0x00 + 20)
+#define AT91_PIN_PA21   (PIN_BASE + 0x00 + 21)
+#define AT91_PIN_PA22   (PIN_BASE + 0x00 + 22)
+#define AT91_PIN_PA23   (PIN_BASE + 0x00 + 23)
+#define AT91_PIN_PA24   (PIN_BASE + 0x00 + 24)
+#define AT91_PIN_PA25   (PIN_BASE + 0x00 + 25)
+#define AT91_PIN_PA26   (PIN_BASE + 0x00 + 26)
+#define AT91_PIN_PA27   (PIN_BASE + 0x00 + 27)
+#define AT91_PIN_PA28   (PIN_BASE + 0x00 + 28)
+#define AT91_PIN_PA29   (PIN_BASE + 0x00 + 29)
+#define AT91_PIN_PA30   (PIN_BASE + 0x00 + 30)
+#define AT91_PIN_PA31   (PIN_BASE + 0x00 + 31)
+#define AT91_PIN_PB0    (PIN_BASE + 0x20 + 0)
+#define AT91_PIN_PB1    (PIN_BASE + 0x20 + 1)
+#define AT91_PIN_PB2    (PIN_BASE + 0x20 + 2)
+#define AT91_PIN_PB3    (PIN_BASE + 0x20 + 3)
+#define AT91_PIN_PB4    (PIN_BASE + 0x20 + 4)
+#define AT91_PIN_PB5    (PIN_BASE + 0x20 + 5)
+#define AT91_PIN_PB6    (PIN_BASE + 0x20 + 6)
+#define AT91_PIN_PB7    (PIN_BASE + 0x20 + 7)
+#define AT91_PIN_PB8    (PIN_BASE + 0x20 + 8)
+#define AT91_PIN_PB9    (PIN_BASE + 0x20 + 9)
+#define AT91_PIN_PB10   (PIN_BASE + 0x20 + 10)
+#define AT91_PIN_PB11   (PIN_BASE + 0x20 + 11)
+#define AT91_PIN_PB12   (PIN_BASE + 0x20 + 12)
+#define AT91_PIN_PB13   (PIN_BASE + 0x20 + 13)
+#define AT91_PIN_PB14   (PIN_BASE + 0x20 + 14)
+#define AT91_PIN_PB15   (PIN_BASE + 0x20 + 15)
+#define AT91_PIN_PB16   (PIN_BASE + 0x20 + 16)
+#define AT91_PIN_PB17   (PIN_BASE + 0x20 + 17)
+#define AT91_PIN_PB18   (PIN_BASE + 0x20 + 18)
+#define AT91_PIN_PB19   (PIN_BASE + 0x20 + 19)
+#define AT91_PIN_PB20   (PIN_BASE + 0x20 + 20)
+#define AT91_PIN_PB21   (PIN_BASE + 0x20 + 21)
+#define AT91_PIN_PB22   (PIN_BASE + 0x20 + 22)
+#define AT91_PIN_PB23   (PIN_BASE + 0x20 + 23)
+#define AT91_PIN_PB24   (PIN_BASE + 0x20 + 24)
+#define AT91_PIN_PB25   (PIN_BASE + 0x20 + 25)
+#define AT91_PIN_PB26   (PIN_BASE + 0x20 + 26)
+#define AT91_PIN_PB27   (PIN_BASE + 0x20 + 27)
+#define AT91_PIN_PB28   (PIN_BASE + 0x20 + 28)
+#define AT91_PIN_PB29   (PIN_BASE + 0x20 + 29)
+#define AT91_PIN_PB30   (PIN_BASE + 0x20 + 30)
+#define AT91_PIN_PB31   (PIN_BASE + 0x20 + 31)
+#define AT91_PIN_PC0    (PIN_BASE + 0x40 + 0)
+#define AT91_PIN_PC1    (PIN_BASE + 0x40 + 1)
+#define AT91_PIN_PC2    (PIN_BASE + 0x40 + 2)
+#define AT91_PIN_PC3    (PIN_BASE + 0x40 + 3)
+#define AT91_PIN_PC4    (PIN_BASE + 0x40 + 4)
+#define AT91_PIN_PC5    (PIN_BASE + 0x40 + 5)
+#define AT91_PIN_PC6    (PIN_BASE + 0x40 + 6)
+#define AT91_PIN_PC7    (PIN_BASE + 0x40 + 7)
+#define AT91_PIN_PC8    (PIN_BASE + 0x40 + 8)
+#define AT91_PIN_PC9    (PIN_BASE + 0x40 + 9)
+#define AT91_PIN_PC10   (PIN_BASE + 0x40 + 10)
+#define AT91_PIN_PC11   (PIN_BASE + 0x40 + 11)
+#define AT91_PIN_PC12   (PIN_BASE + 0x40 + 12)
+#define AT91_PIN_PC13   (PIN_BASE + 0x40 + 13)
+#define AT91_PIN_PC14   (PIN_BASE + 0x40 + 14)
+#define AT91_PIN_PC15   (PIN_BASE + 0x40 + 15)
+#define AT91_PIN_PC16   (PIN_BASE + 0x40 + 16)
+#define AT91_PIN_PC17   (PIN_BASE + 0x40 + 17)
+#define AT91_PIN_PC18   (PIN_BASE + 0x40 + 18)
+#define AT91_PIN_PC19   (PIN_BASE + 0x40 + 19)
+#define AT91_PIN_PC20   (PIN_BASE + 0x40 + 20)
+#define AT91_PIN_PC21   (PIN_BASE + 0x40 + 21)
+#define AT91_PIN_PC22   (PIN_BASE + 0x40 + 22)
+#define AT91_PIN_PC23   (PIN_BASE + 0x40 + 23)
+#define AT91_PIN_PC24   (PIN_BASE + 0x40 + 24)
+#define AT91_PIN_PC25   (PIN_BASE + 0x40 + 25)
+#define AT91_PIN_PC26   (PIN_BASE + 0x40 + 26)
+#define AT91_PIN_PC27   (PIN_BASE + 0x40 + 27)
+#define AT91_PIN_PC28   (PIN_BASE + 0x40 + 28)
+#define AT91_PIN_PC29   (PIN_BASE + 0x40 + 29)
+#define AT91_PIN_PC30   (PIN_BASE + 0x40 + 30)
+#define AT91_PIN_PC31   (PIN_BASE + 0x40 + 31)
+#define AT91_PIN_PD0    (PIN_BASE + 0x60 + 0)
+#define AT91_PIN_PD1    (PIN_BASE + 0x60 + 1)
+#define AT91_PIN_PD2    (PIN_BASE + 0x60 + 2)
+#define AT91_PIN_PD3    (PIN_BASE + 0x60 + 3)
+#define AT91_PIN_PD4    (PIN_BASE + 0x60 + 4)
+#define AT91_PIN_PD5    (PIN_BASE + 0x60 + 5)
+#define AT91_PIN_PD6    (PIN_BASE + 0x60 + 6)
+#define AT91_PIN_PD7    (PIN_BASE + 0x60 + 7)
+#define AT91_PIN_PD8    (PIN_BASE + 0x60 + 8)
+#define AT91_PIN_PD9    (PIN_BASE + 0x60 + 9)
+#define AT91_PIN_PD10   (PIN_BASE + 0x60 + 10)
+#define AT91_PIN_PD11   (PIN_BASE + 0x60 + 11)
+#define AT91_PIN_PD12   (PIN_BASE + 0x60 + 12)
+#define AT91_PIN_PD13   (PIN_BASE + 0x60 + 13)
+#define AT91_PIN_PD14   (PIN_BASE + 0x60 + 14)
+#define AT91_PIN_PD15   (PIN_BASE + 0x60 + 15)
+#define AT91_PIN_PD16   (PIN_BASE + 0x60 + 16)
+#define AT91_PIN_PD17   (PIN_BASE + 0x60 + 17)
+#define AT91_PIN_PD18   (PIN_BASE + 0x60 + 18)
+#define AT91_PIN_PD19   (PIN_BASE + 0x60 + 19)
+#define AT91_PIN_PD20   (PIN_BASE + 0x60 + 20)
+#define AT91_PIN_PD21   (PIN_BASE + 0x60 + 21)
+#define AT91_PIN_PD22   (PIN_BASE + 0x60 + 22)
+#define AT91_PIN_PD23   (PIN_BASE + 0x60 + 23)
+#define AT91_PIN_PD24   (PIN_BASE + 0x60 + 24)
+#define AT91_PIN_PD25   (PIN_BASE + 0x60 + 25)
+#define AT91_PIN_PD26   (PIN_BASE + 0x60 + 26)
+#define AT91_PIN_PD27   (PIN_BASE + 0x60 + 27)
+#define AT91_PIN_PD28   (PIN_BASE + 0x60 + 28)
+#define AT91_PIN_PD29   (PIN_BASE + 0x60 + 29)
+#define AT91_PIN_PD30   (PIN_BASE + 0x60 + 30)
+#define AT91_PIN_PD31   (PIN_BASE + 0x60 + 31)
+#ifndef __ASSEMBLY__
+/* setup setup routines, called from board init or driver probe() */
+extern int at91_set_A_periph(unsigned pin, int use_pullup);
+extern int at91_set_B_periph(unsigned pin, int use_pullup);
+extern int at91_set_gpio_input(unsigned pin, int use_pullup);
+extern int at91_set_gpio_output(unsigned pin, int value);
+extern int at91_set_deglitch(unsigned pin, int is_on);
+/* callable at any time */
+extern int at91_set_gpio_value(unsigned pin, int value);
+extern int at91_get_gpio_value(unsigned pin);
+#endif
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
new file mode 100644
index 000000000000..2646c01f8e97
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -0,0 +1,92 @@
+/*
+ * include/asm-arm/arch-at91rm9200/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *  Copyright (C) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <asm/sizes.h>
+#include <asm/arch/at91rm9200.h>
+#include <asm/arch/at91rm9200_sys.h>
+/*
+ * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
+ * to 0xFEFA0000 .. 0xFF000000.  (384Kb)
+ */
+#define AT91_IO_PHYS_BASE       0xFFFA0000
+#define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
+#define AT91_IO_VIRT_BASE       (0xFF000000 - AT91_IO_SIZE)
+ /* Convert a physical IO address to virtual IO address */
+#define AT91_IO_P2V(x)  ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
+/*
+ * Virtual to Physical Address mapping for IO devices.
+ */
+#define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
+#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91_BASE_SPI)
+#define AT91_VA_BASE_SSC2       AT91_IO_P2V(AT91_BASE_SSC2)
+#define AT91_VA_BASE_SSC1       AT91_IO_P2V(AT91_BASE_SSC1)
+#define AT91_VA_BASE_SSC0       AT91_IO_P2V(AT91_BASE_SSC0)
+#define AT91_VA_BASE_US3        AT91_IO_P2V(AT91_BASE_US3)
+#define AT91_VA_BASE_US2        AT91_IO_P2V(AT91_BASE_US2)
+#define AT91_VA_BASE_US1        AT91_IO_P2V(AT91_BASE_US1)
+#define AT91_VA_BASE_US0        AT91_IO_P2V(AT91_BASE_US0)
+#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91_BASE_EMAC)
+#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91_BASE_TWI)
+#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91_BASE_MCI)
+#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91_BASE_UDP)
+#define AT91_VA_BASE_TCB1       AT91_IO_P2V(AT91_BASE_TCB1)
+#define AT91_VA_BASE_TCB0       AT91_IO_P2V(AT91_BASE_TCB0)
+/* Internal SRAM */
+#define AT91_BASE_SRAM          0x00200000      /* Internal SRAM base address */
+#define AT91_SRAM_SIZE          0x00004000      /* Internal SRAM SIZE (16Kb) */
+/* Serial ports */
+#define AT91_NR_UART            5               /* 4 USART3's and one DBGU port */
+/* FLASH */
+#define AT91_FLASH_BASE         0x10000000      /* NCS0: Flash physical base address */
+/* SDRAM */
+#define AT91_SDRAM_BASE         0x20000000      /* NCS1: SDRAM physical base address */
+/* SmartMedia */
+#define AT91_SMARTMEDIA_BASE    0x40000000      /* NCS3: Smartmedia physical base address */
+/* Multi-Master Memory controller */
+#define AT91_UHP_BASE           0x00300000      /* USB Host controller */
+/* Clocks */
+#define AT91_SLOW_CLOCK         32768           /* slow clock */
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+static inline unsigned int at91_sys_read(unsigned int reg_offset)
+{
+        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
+        return readl(addr + reg_offset);
+}
+static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
+{
+        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
+        writel(value, addr + reg_offset);
+}
+#endif
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/io.h b/include/asm-arm/arch-at91rm9200/io.h
new file mode 100644
index 000000000000..23e670d85c9d
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/io.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-at91rm9200/io.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+#include <asm/arch/at91rm9200.h>
+#include <asm/io.h>
+#define IO_SPACE_LIMIT          0xFFFFFFFF
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
new file mode 100644
index 000000000000..27b0497f1b36
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -0,0 +1,52 @@
+/*
+ * include/asm-arm/arch-at91rm9200/irqs.h
+ *
+ *  Copyright (C) 2004 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+#define NR_AIC_IRQS 32
+/*
+ * Acknowledge interrupt with AIC after interrupt has been handled.
+ *   (by kernel/irq.c)
+ */
+#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
+/*
+ * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h
+ * for IRQs handled directly through the AIC, or else the AT91_PIN_*
+ * symbols in gpio.h for ones handled indirectly as GPIOs.
+ * We make provision for 4 banks of GPIO.
+ */
+#include <asm/arch/gpio.h>
+#define NR_IRQS         (NR_AIC_IRQS + (4 * 32))
+#ifndef __ASSEMBLY__
+/*
+ * Initialize the IRQ controller.
+ */
+extern void at91rm9200_init_irq(unsigned int priority[]);
+#endif
+#endif
diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-at91rm9200/memory.h
index 999541b6a9f5..462f1f0ad67c 100644
--- a/include/asm-arm/arch-epxa10db/memory.h
+++ b/include/asm-arm/arch-at91rm9200/memory.h
@@ -1,7 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10/memory.h
+ * include/asm-arm/arch-at91rm9200/memory.h
 *
- *  Copyright (C) 2001 Altera Corporation
+ *  Copyright (C) 2004 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -17,13 +17,14 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-/*
+#include <asm/arch/hardware.h>
- * Physical DRAM offset.
- */
+#define PHYS_OFFSET     (AT91_SDRAM_BASE)
-#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
@@ -32,7 +33,9 @@
 * bus_to_virt: Used to convert an address for DMA operations
 *              to an address that the kernel can use.
 */
-#define __virt_to_bus(x)        (x - PAGE_OFFSET + /*SDRAM_BASE*/0)
+#define __virt_to_bus__is_a_macro
-#define __bus_to_virt(x)        (x - /*SDRAM_BASE*/0 + PAGE_OFFSET)
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) __phys_to_virt(x)
 #endif
diff --git a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-at91rm9200/param.h
index 546fb7d2b6ad..9480f8446852 100644
--- a/include/asm-arm/arch-epxa10db/vmalloc.h
+++ b/include/asm-arm/arch-at91rm9200/param.h
@@ -1,7 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10db/vmalloc.h
+ * include/asm-arm/arch-at91rm9200/param.h
 *
- *  Copyright (C) 2000 Russell King.
+ *  Copyright (C) 2003 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -17,4 +17,12 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+/*
+ * We use default params
+ */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/pio.h b/include/asm-arm/arch-at91rm9200/pio.h
new file mode 100644
index 000000000000..a89501b4a703
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/pio.h
@@ -0,0 +1,115 @@
+/*
+ * include/asm-arm/arch-at91rm9200/pio.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ASM_ARCH_PIO_H
+#define __ASM_ARCH_PIO_H
+#include <asm/arch/hardware.h>
+static inline void AT91_CfgPIO_USART0(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA17_TXD0 | AT91_PA18_RXD0 | AT91_PA20_CTS0);
+        /*
+         * Errata #39 - RTS0 is not internally connected to PA21.  We need to drive
+         *  the pin manually.  Default is off (RTS is active low).
+         */
+        at91_sys_write(AT91_PIOA + PIO_PER, AT91_PA21_RTS0);
+        at91_sys_write(AT91_PIOA + PIO_OER, AT91_PA21_RTS0);
+        at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
+}
+static inline void AT91_CfgPIO_USART1(void) {
+        at91_sys_write(AT91_PIOB + PIO_PDR, AT91_PB18_RI1 | AT91_PB19_DTR1
+                        | AT91_PB20_TXD1 | AT91_PB21_RXD1 | AT91_PB23_DCD1
+                        | AT91_PB24_CTS1 | AT91_PB25_DSR1 | AT91_PB26_RTS1);
+}
+static inline void AT91_CfgPIO_USART2(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA22_RXD2 | AT91_PA23_TXD2);
+}
+static inline void AT91_CfgPIO_USART3(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
+        at91_sys_write(AT91_PIOA + PIO_BSR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
+}
+static inline void AT91_CfgPIO_DBGU(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA31_DTXD | AT91_PA30_DRXD);
+}
+/*
+ * Enable the Two-Wire interface.
+ */
+static inline void AT91_CfgPIO_TWI(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA25_TWD | AT91_PA26_TWCK);
+        at91_sys_write(AT91_PIOA + PIO_ASR, AT91_PA25_TWD | AT91_PA26_TWCK);
+        at91_sys_write(AT91_PIOA + PIO_MDER, AT91_PA25_TWD | AT91_PA26_TWCK);           /* open drain */
+}
+/*
+ * Enable the Serial Peripheral Interface.
+ */
+static inline void AT91_CfgPIO_SPI(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA0_MISO | AT91_PA1_MOSI | AT91_PA2_SPCK);
+}
+static inline void AT91_CfgPIO_SPI_CS0(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA3_NPCS0);
+}
+static inline void AT91_CfgPIO_SPI_CS1(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA4_NPCS1);
+}
+static inline void AT91_CfgPIO_SPI_CS2(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_NPCS2);
+}
+static inline void AT91_CfgPIO_SPI_CS3(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA6_NPCS3);
+}
+/*
+ * Select the DataFlash card.
+ */
+static inline void AT91_CfgPIO_DataFlashCard(void) {
+        at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(7));
+        at91_sys_write(AT91_PIOB + PIO_OER, AT91_PIO_P(7));
+        at91_sys_write(AT91_PIOB + PIO_CODR, AT91_PIO_P(7));
+}
+/*
+ * Enable NAND Flash (SmartMedia) interface.
+ */
+static inline void AT91_CfgPIO_SmartMedia(void) {
+        /* enable PC0=SMCE, PC1=SMOE, PC3=SMWE, A21=CLE, A22=ALE */
+        at91_sys_write(AT91_PIOC + PIO_ASR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
+        at91_sys_write(AT91_PIOC + PIO_PDR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
+        /* Configure PC2 as input (signal READY of the SmartMedia) */
+        at91_sys_write(AT91_PIOC + PIO_PER, AT91_PC2_BFAVD);    /* enable direct output enable */
+        at91_sys_write(AT91_PIOC + PIO_ODR, AT91_PC2_BFAVD);    /* disable output */
+        /* Configure PB1 as input (signal Card Detect of the SmartMedia) */
+        at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(1));     /* enable direct output enable */
+        at91_sys_write(AT91_PIOB + PIO_ODR, AT91_PIO_P(1));     /* disable output */
+}
+static inline int AT91_PIO_SmartMedia_RDY(void) {
+        return (at91_sys_read(AT91_PIOC + PIO_PDSR) & AT91_PIO_P(2)) ? 1 : 0;
+}
+static inline int AT91_PIO_SmartMedia_CardDetect(void) {
+        return (at91_sys_read(AT91_PIOB + PIO_PDSR) & AT91_PIO_P(1)) ? 1 : 0;
+}
+#endif
diff --git a/include/asm-arm/arch-epxa10db/system.h b/include/asm-arm/arch-at91rm9200/system.h
index 345b092a1ed5..29c42655f05c 100644
--- a/include/asm-arm/arch-epxa10db/system.h
+++ b/include/asm-arm/arch-at91rm9200/system.h
@@ -1,9 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10db/system.h
+ * include/asm-arm/arch-at91rm9200/system.h
 *
- *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2003 SAN People
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2001 Altera Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -19,23 +17,35 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <asm/arch/platform.h>
+#include <asm/arch/hardware.h>
 static inline void arch_idle(void)
 {
        /*
-         * This should do all the clock switching
+         * Disable the processor clock.  The processor will be automatically
-         * and wait for interrupt tricks
+         * re-enabled by an interrupt or by a reset.
+         */
+//      at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+        /*
+         * Set the processor (CP15) into 'Wait for Interrupt' mode.
+         * Unlike disabling the processor clock via the PMC (above)
+         *  this allows the processor to be woken via JTAG.
         */
        cpu_do_idle();
 }
-extern __inline__ void arch_reset(char mode)
+static inline void arch_reset(char mode)
 {
-        /* Hmm... We can probably do something with the watchdog... */
+        /*
+         * Perform a hardware reset with the use of the Watchdog timer.
+         */
+        at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+        at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
 }
 #endif
diff --git a/include/asm-arm/arch-epxa10db/dma.h b/include/asm-arm/arch-at91rm9200/timex.h
index 5d97734d1077..3f112dd12587 100644
--- a/include/asm-arm/arch-epxa10db/dma.h
+++ b/include/asm-arm/arch-at91rm9200/timex.h
@@ -1,7 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-camelot/dma.h
+ * include/asm-arm/arch-at91rm9200/timex.h
 *
- *  Copyright (C) 1997,1998 Russell King
+ *  Copyright (C) 2003 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -17,12 +17,12 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
-#define MAX_DMA_CHANNELS        0
+#include <asm/arch/hardware.h>
-#endif /* _ASM_ARCH_DMA_H */
+#define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h
new file mode 100644
index 000000000000..b30dd5520713
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/uncompress.h
@@ -0,0 +1,55 @@
+/*
+ * include/asm-arm/arch-at91rm9200/uncompress.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+#include <asm/arch/hardware.h>
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        void __iomem *sys = (void __iomem *) AT91_BASE_SYS;     /* physical address */
+        while (*s) {
+                while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
+                __raw_writel(*s, sys + AT91_DBGU_THR);
+                if (*s == '\n') {
+                        while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
+                        __raw_writel('\r', sys + AT91_DBGU_THR);
+                }
+                s++;
+        }
+        /* wait for transmission to complete */
+        while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) { barrier(); }
+}
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+#endif
diff --git a/include/asm-arm/arch-epxa10db/timex.h b/include/asm-arm/arch-at91rm9200/vmalloc.h
index b87a75fc9589..34d9718feb90 100644
--- a/include/asm-arm/arch-epxa10db/timex.h
+++ b/include/asm-arm/arch-at91rm9200/vmalloc.h
@@ -1,9 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10db/timex.h
+ * include/asm-arm/arch-at91rm9200/vmalloc.h
 *
- *  Excalibur timex specifications
+ *  Copyright (C) 2003 SAN People
- *
- *  Copyright (C) 2001 Altera Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -20,7 +18,9 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-/*
+#ifndef __ASM_ARCH_VMALLOC_H
- * ??
+#define __ASM_ARCH_VMALLOC_H
- */
-#define CLOCK_TICK_RATE         (50000000 / 16)
+#define VMALLOC_END             (AT91_IO_VIRT_BASE & PGDIR_MASK)
+#endif
diff --git a/include/asm-arm/arch-cl7500/dma.h b/include/asm-arm/arch-cl7500/dma.h
index 1d6a8829d327..591ed2551892 100644
--- a/include/asm-arm/arch-cl7500/dma.h
+++ b/include/asm-arm/arch-cl7500/dma.h
@@ -15,7 +15,6 @@
 * bytes of RAM.
 */
 #define MAX_DMA_ADDRESS         0xd0000000
-#define MAX_DMA_CHANNELS        0
 #define DMA_S0                  0
diff --git a/include/asm-arm/arch-cl7500/entry-macro.S b/include/asm-arm/arch-cl7500/entry-macro.S
index 686f413f82d6..c9e5395e5106 100644
--- a/include/asm-arm/arch-cl7500/entry-macro.S
+++ b/include/asm-arm/arch-cl7500/entry-macro.S
@@ -1,3 +1,3 @@
+#include <asm/hardware.h>
 #include <asm/hardware/entry-macro-iomd.S>
diff --git a/include/asm-arm/arch-clps711x/dma.h b/include/asm-arm/arch-clps711x/dma.h
index 3c4c5c843252..610997938423 100644
--- a/include/asm-arm/arch-clps711x/dma.h
+++ b/include/asm-arm/arch-clps711x/dma.h
@@ -17,12 +17,3 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-#define MAX_DMA_CHANNELS        0
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-clps711x/entry-macro.S b/include/asm-arm/arch-clps711x/entry-macro.S
index b31079a1d4a9..21f6ee485819 100644
--- a/include/asm-arm/arch-clps711x/entry-macro.S
+++ b/include/asm-arm/arch-clps711x/entry-macro.S
@@ -7,6 +7,7 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware.h>
 #include <asm/hardware/clps7111.h>
                .macro  disable_fiq
diff --git a/include/asm-arm/arch-clps711x/system.h b/include/asm-arm/arch-clps711x/system.h
index 2ab981fee37f..11e1491535a8 100644
--- a/include/asm-arm/arch-clps711x/system.h
+++ b/include/asm-arm/arch-clps711x/system.h
@@ -20,7 +20,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
+#include <asm/hardware.h>
 #include <asm/hardware/clps7111.h>
+#include <asm/io.h>
 static inline void arch_idle(void)
 {
diff --git a/include/asm-arm/arch-ebsa110/dma.h b/include/asm-arm/arch-ebsa110/dma.h
index d491776ac1cc..c52f9e2ab0bb 100644
--- a/include/asm-arm/arch-ebsa110/dma.h
+++ b/include/asm-arm/arch-ebsa110/dma.h
@@ -9,11 +9,3 @@
 *
 *  EBSA110 DMA definitions
 */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-#define MAX_DMA_CHANNELS        0
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ebsa285/dma.h b/include/asm-arm/arch-ebsa285/dma.h
index c43046eb8bc7..0259ad45d33c 100644
--- a/include/asm-arm/arch-ebsa285/dma.h
+++ b/include/asm-arm/arch-ebsa285/dma.h
@@ -10,11 +10,6 @@
 #define __ASM_ARCH_DMA_H
 /*
- * This is the maximum DMA address that can be DMAd to.
- */
-#define MAX_DMA_ADDRESS         0xffffffff
-/*
 * The 21285 has two internal DMA channels; we call these 8 and 9.
 * On CATS hardware we have an additional eight ISA dma channels
 * numbered 0..7.
diff --git a/include/asm-arm/arch-ebsa285/entry-macro.S b/include/asm-arm/arch-ebsa285/entry-macro.S
index db5729ff6349..cf10ac96fdde 100644
--- a/include/asm-arm/arch-ebsa285/entry-macro.S
+++ b/include/asm-arm/arch-ebsa285/entry-macro.S
@@ -7,6 +7,8 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware.h>
+#include <asm/arch/irqs.h>
 #include <asm/hardware/dec21285.h>
                .macro  disable_fiq
diff --git a/include/asm-arm/arch-epxa10db/debug-macro.S b/include/asm-arm/arch-epxa10db/debug-macro.S
deleted file mode 100644
index 1d11c51f498f..000000000000
--- a/include/asm-arm/arch-epxa10db/debug-macro.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/* linux/include/asm-arm/arch-epxa10db/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-#include <asm/arch/excalibur.h>
-#define UART00_TYPE
-#include <asm/arch/uart00.h>
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldr     \rx, =EXC_UART00_BASE   @ physical base address
-                orrne   \rx, \rx, #0xff000000   @ virtual base
-                orrne   \rx, \rx, #0x00f00000
-                .endm
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #UART_TD(0)]
-                .endm
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #UART_TSR(0)]
-                and     \rd, \rd,  #UART_TSR_TX_LEVEL_MSK
-                cmp     \rd, #15
-                beq     1001b
-                .endm
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #UART_TSR(0)]
-                ands    \rd, \rd,  #UART_TSR_TX_LEVEL_MSK
-                bne     1001b
-                .endm
diff --git a/include/asm-arm/arch-epxa10db/entry-macro.S b/include/asm-arm/arch-epxa10db/entry-macro.S
deleted file mode 100644
index de6ae08334e2..000000000000
--- a/include/asm-arm/arch-epxa10db/entry-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * include/asm-arm/arch-epxa10db/entry-macro.S
- *
- * Low-level IRQ helper macros for epxa10db platform
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/platform.h>
-#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */
-#include <asm/arch/int_ctrl00.h>
-                .macro  disable_fiq
-                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE))
-                ldr     \irqnr,[\irqstat]
-                cmp     \irqnr,#0
-                subne   \irqnr,\irqnr,#1
-                .endm
diff --git a/include/asm-arm/arch-epxa10db/ether00.h b/include/asm-arm/arch-epxa10db/ether00.h
deleted file mode 100644
index b737b8aabe2f..000000000000
--- a/include/asm-arm/arch-epxa10db/ether00.h
+++ /dev/null
@@ -1,482 +0,0 @@
-#ifndef __ETHER00_H
-#define __ETHER00_H
-/*
- * Register definitions for the Ethernet MAC
- */
-/*
- * Copyright (c) Altera Corporation 2000.
- * All rights reserved.
- */
-/*
-*       Structures for the DMA controller
-*/
-typedef struct fda_desc
-        {
-        struct fda_desc *       FDNext;
-        long                            FDSystem;
-        long                            FDStat;
-        short                           FDLength;
-        short                           FDCtl;
-        }FDA_DESC;
-typedef struct buf_desc
-        {
-        char *  BuffData;
-        short   BuffLength;
-        char    BDStat;
-        char    BDCtl;
-        }BUF_DESC;
-/*
-*       Control masks for the DMA controller
-*/
-#define FDCTL_BDCOUNT_MSK                                               (0x1F)
-#define FDCTL_BDCOUNT_OFST                                              (0)
-#define FDCTL_FRMOPT_MSK                                                (0x7C00)
-#define FDCTL_FRMOPT_OFST                                               (10)
-#define FDCTL_COWNSFD_MSK                                               (0x8000)
-#define FDCTL_COWNSFD_OFST                                              (15)
-#define BDCTL_RXBDSEQN_MSK                                              (0x7F)
-#define BDCTL_RXBDSEQN_OFST                                             (0)
-#define BDCTL_COWNSBD_MSK                                               (0x80)
-#define BDCTL_COWNSBD_OFST                                              (7)
-#define FDNEXT_EOL_MSK                                                  (0x1)
-#define FDNEXT_EOL_OFST                                                 (0)
-#define FDNEXT_EOL_POINTER_MSK                                  (0xFFFFFFF0)
-#define FDNEXT_EOL_POINTER_OFST                                 (4)
-#define ETHER_ARC_SIZE         (21)
-/*
-*       Register definitions and masks
-*/
-#define ETHER_DMA_CTL(base)                                                     (ETHER00_TYPE (base + 0x100))
-#define ETHER_DMA_CTL_DMBURST_OFST                              (2)
-#define ETHER_DMA_CTL_DMBURST_MSK                               (0x1FC)
-#define ETHER_DMA_CTL_POWRMGMNT_OFST                    (11)
-#define ETHER_DMA_CTL_POWRMGMNT_MSK                             (0x1000)
-#define ETHER_DMA_CTL_TXBIGE_OFST                               (14)
-#define ETHER_DMA_CTL_TXBIGE_MSK                                (0x4000)
-#define ETHER_DMA_CTL_RXBIGE_OFST                               (15)
-#define ETHER_DMA_CTL_RXBIGE_MSK                                (0x8000)
-#define ETHER_DMA_CTL_TXWAKEUP_OFST                             (16)
-#define ETHER_DMA_CTL_TXWAKEUP_MSK                              (0x10000)
-#define ETHER_DMA_CTL_SWINTREQ_OFST                             (17)
-#define ETHER_DMA_CTL_SWINTREQ_MSK                              (0x20000)
-#define ETHER_DMA_CTL_INTMASK_OFST                              (18)
-#define ETHER_DMA_CTL_INTMASK_MSK                               (0x40000)
-#define ETHER_DMA_CTL_M66ENSTAT_OFST                    (19)
-#define ETHER_DMA_CTL_M66ENSTAT_MSK                             (0x80000)
-#define ETHER_DMA_CTL_RMTXINIT_OFST                             (20)
-#define ETHER_DMA_CTL_RMTXINIT_MSK                              (0x100000)
-#define ETHER_DMA_CTL_RMRXINIT_OFST                             (21)
-#define ETHER_DMA_CTL_RMRXINIT_MSK                              (0x200000)
-#define ETHER_DMA_CTL_RXALIGN_OFST                              (22)
-#define ETHER_DMA_CTL_RXALIGN_MSK                               (0xC00000)
-#define ETHER_DMA_CTL_RMSWRQ_OFST                               (24)
-#define ETHER_DMA_CTL_RMSWRQ_MSK                                (0x1000000)
-#define ETHER_DMA_CTL_RMEMBANK_OFST                             (25)
-#define ETHER_DMA_CTL_RMEMBANK_MSK                              (0x2000000)
-#define ETHER_TXFRMPTR(base)                                                    (ETHER00_TYPE (base + 0x104))
-#define ETHER_TXTHRSH(base)                                                     (ETHER00_TYPE (base + 0x308))
-#define ETHER_TXPOLLCTR(base)                                                   (ETHER00_TYPE (base + 0x30c))
-#define ETHER_BLFRMPTR(base)                                                    (ETHER00_TYPE (base + 0x110))
-#define ETHER_BLFFRMPTR_EOL_OFST                                (0)
-#define ETHER_BLFFRMPTR_EOL_MSK                                 (0x1)
-#define ETHER_BLFFRMPTR_ADDRESS_OFST                    (4)
-#define ETHER_BLFFRMPTR_ADDRESS_MSK                             (0xFFFFFFF0)
-#define ETHER_RXFRAGSIZE(base)                                          (ETHER00_TYPE (base + 0x114))
-#define ETHER_RXFRAGSIZE_MINFRAG_OFST                   (2)
-#define ETHER_RXFRAGSIZE_MINFRAG_MSK                    (0xFFC)
-#define ETHER_RXFRAGSIZE_ENPACK_OFST                    (15)
-#define ETHER_RXFRAGSIZE_ENPACK_MSK                             (0x8000)
-#define ETHER_INT_EN(base)                                                      (ETHER00_TYPE (base + 0x118))
-#define ETHER_INT_EN_FDAEXEN_OFST                               (0)
-#define ETHER_INT_EN_FDAEXEN_MSK                                (0x1)
-#define ETHER_INT_EN_BLEXEN_OFST                                (1)
-#define ETHER_INT_EN_BLEXN_MSK                                  (0x2)
-#define ETHER_INT_EN_STARGABTEN_OFST                    (2)
-#define ETHER_INT_EN_STARGABTEN_MSK                             (0x4)
-#define ETHER_INT_EN_RTARGABTEN_OFST                    (3)
-#define ETHER_INT_EN_RTARGABTEN_MSK                             (0x8)
-#define ETHER_INT_EN_RMASABTEN_OFST                             (4)
-#define ETHER_INT_EN_RMASABTEN_MSK                              (0x10)
-#define ETHER_INT_EN_SSYSERREN_OFST                             (5)
-#define ETHER_INT_EN_SSYSERREN_MSK                              (0x20)
-#define ETHER_INT_EN_DPARERREN_OFST                             (6)
-#define ETHER_INT_EN_DPARERREN_MSK                              (0x40)
-#define ETHER_INT_EN_EARNOTEN_OFST                              (7)
-#define ETHER_INT_EN_EARNOTEN_MSK                               (0x80)
-#define ETHER_INT_EN_DPARDEN_OFST                               (8)
-#define ETHER_INT_EN_DPARDEN_MSK                                (0x100)
-#define ETHER_INT_EN_DMPARERREN_OFST                    (9)
-#define ETHER_INT_EN_DMPARERREN_MSK                             (0x200)
-#define ETHER_INT_EN_TXCTLCMPEN_OFST                    (10)
-#define ETHER_INT_EN_TXCTLCMPEN_MSK                             (0x400)
-#define ETHER_INT_EN_NRABTEN_OFST                               (11)
-#define ETHER_INT_EN_NRABTEN_MSK                                (0x800)
-#define ETHER_FDA_BAS(base)                                                     (ETHER00_TYPE (base + 0x11C))
-#define ETHER_FDA_BAS_ADDRESS_OFST                              (4)
-#define ETHER_FDA_BAS_ADDRESS_MSK                               (0xFFFFFFF0)
-#define ETHER_FDA_LIM(base)                                                     (ETHER00_TYPE (base + 0x120))
-#define ETHER_FDA_LIM_COUNT_OFST                                (4)
-#define ETHER_FDA_LIM_COUNT_MSK                                 (0xFFF0)
-#define ETHER_INT_SRC(base)                                                     (ETHER00_TYPE (base + 0x124))
-#define ETHER_INT_SRC_INTMACTX_OFST                             (0)
-#define ETHER_INT_SRC_INTMACTX_MSK                              (0x1)
-#define ETHER_INT_SRC_INTMACRX_OFST                             (1)
-#define ETHER_INT_SRC_INTMACRX_MSK                              (0x2)
-#define ETHER_INT_SRC_INTSBUS_OFST                              (2)
-#define ETHER_INT_SRC_INTSBUS_MSK                               (0x4)
-#define ETHER_INT_SRC_INTFDAEX_OFST                             (3)
-#define ETHER_INT_SRC_INTFDAEX_MSK                              (0x8)
-#define ETHER_INT_SRC_INTBLEX_OFST                              (4)
-#define ETHER_INT_SRC_INTBLEX_MSK                               (0x10)
-#define ETHER_INT_SRC_SWINT_OFST                                (5)
-#define ETHER_INT_SRC_SWINT_MSK                                 (0x20)
-#define ETHER_INT_SRC_INTEARNOT_OFST                    (6)
-#define ETHER_INT_SRC_INTEARNOT_MSK                             (0x40)
-#define ETHER_INT_SRC_DMPARERR_OFST                             (7)
-#define ETHER_INT_SRC_DMPARERR_MSK                              (0x80)
-#define ETHER_INT_SRC_INTEXBD_OFST                              (8)
-#define ETHER_INT_SRC_INTEXBD_MSK                               (0x100)
-#define ETHER_INT_SRC_INTTXCTLCMP_OFST                  (9)
-#define ETHER_INT_SRC_INTTXCTLCMP_MSK                   (0x200)
-#define ETHER_INT_SRC_INTNRABT_OFST                             (10)
-#define ETHER_INT_SRC_INTNRABT_MSK                              (0x400)
-#define ETHER_INT_SRC_FDAEX_OFST                                (11)
-#define ETHER_INT_SRC_FDAEX_MSK                                 (0x800)
-#define ETHER_INT_SRC_BLEX_OFST                                 (12)
-#define ETHER_INT_SRC_BLEX_MSK                                  (0x1000)
-#define ETHER_INT_SRC_DMPARERRSTAT_OFST                 (13)
-#define ETHER_INT_SRC_DMPARERRSTAT_MSK                  (0x2000)
-#define ETHER_INT_SRC_NRABT_OFST                                (14)
-#define ETHER_INT_SRC_NRABT_MSK                                 (0x4000)
-#define ETHER_INT_SRC_INTLINK_OFST                              (15)
-#define ETHER_INT_SRC_INTLINK_MSK                               (0x8000)
-#define ETHER_INT_SRC_INTEXDEFER_OFST                   (16)
-#define ETHER_INT_SRC_INTEXDEFER_MSK                    (0x10000)
-#define ETHER_INT_SRC_INTRMON_OFST                              (17)
-#define ETHER_INT_SRC_INTRMON_MSK                               (0x20000)
-#define ETHER_INT_SRC_IRQ_MSK                                   (0x83FF)
-#define ETHER_PAUSECNT(base)                                                    (ETHER00_TYPE (base + 0x40))
-#define ETHER_PAUSECNT_COUNT_OFST                               (0)
-#define ETHER_PAUSECNT_COUNT_MSK                                (0xFFFF)
-#define ETHER_REMPAUCNT(base)                                                   (ETHER00_TYPE (base + 0x44))
-#define ETHER_REMPAUCNT_COUNT_OFST                              (0)
-#define ETHER_REMPAUCNT_COUNT_MSK                               (0xFFFF)
-#define ETHER_TXCONFRMSTAT(base)                                                (ETHER00_TYPE (base + 0x348))
-#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST   (0)
-#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK    (0x3FFFFF)
-#define ETHER_MAC_CTL(base)                                                     (ETHER00_TYPE (base + 0))
-#define ETHER_MAC_CTL_HALTREQ_OFST                              (0)
-#define ETHER_MAC_CTL_HALTREQ_MSK                               (0x1)
-#define ETHER_MAC_CTL_HALTIMM_OFST                              (1)
-#define ETHER_MAC_CTL_HALTIMM_MSK                               (0x2)
-#define ETHER_MAC_CTL_RESET_OFST                                (2)
-#define ETHER_MAC_CTL_RESET_MSK                                 (0x4)
-#define ETHER_MAC_CTL_FULLDUP_OFST                              (3)
-#define ETHER_MAC_CTL_FULLDUP_MSK                               (0x8)
-#define ETHER_MAC_CTL_MACLOOP_OFST                              (4)
-#define ETHER_MAC_CTL_MACLOOP_MSK                               (0x10)
-#define ETHER_MAC_CTL_CONN_OFST                                 (5)
-#define ETHER_MAC_CTL_CONN_MSK                                  (0x60)
-#define ETHER_MAC_CTL_LOOP10_OFST                               (7)
-#define ETHER_MAC_CTL_LOOP10_MSK                                (0x80)
-#define ETHER_MAC_CTL_LNKCHG_OFST                               (8)
-#define ETHER_MAC_CTL_LNKCHG_MSK                                (0x100)
-#define ETHER_MAC_CTL_MISSROLL_OFST                             (10)
-#define ETHER_MAC_CTL_MISSROLL_MSK                              (0x400)
-#define ETHER_MAC_CTL_ENMISSROLL_OFST                   (13)
-#define ETHER_MAC_CTL_ENMISSROLL_MSK                    (0x2000)
-#define ETHER_MAC_CTL_LINK10_OFST                               (15)
-#define ETHER_MAC_CTL_LINK10_MSK                                (0x8000)
-#define ETHER_ARC_CTL(base)                                                     (ETHER00_TYPE (base + 0x4))
-#define ETHER_ARC_CTL_STATIONACC_OFST                   (0)
-#define ETHER_ARC_CTL_STATIONACC_MSK                    (0x1)
-#define ETHER_ARC_CTL_GROUPACC_OFST                             (1)
-#define ETHER_ARC_CTL_GROUPACC_MSK                              (0x2)
-#define ETHER_ARC_CTL_BROADACC_OFST                             (2)
-#define ETHER_ARC_CTL_BROADACC_MSK                              (0x4)
-#define ETHER_ARC_CTL_NEGARC_OFST                               (3)
-#define ETHER_ARC_CTL_NEGARC_MSK                                (0x8)
-#define ETHER_ARC_CTL_COMPEN_OFST                               (4)
-#define ETHER_ARC_CTL_COMPEN_MSK                                (0x10)
-#define ETHER_TX_CTL(base)                                                      (ETHER00_TYPE (base + 0x8))
-#define ETHER_TX_CTL_TXEN_OFST                                  (0)
-#define ETHER_TX_CTL_TXEN_MSK                                   (0x1)
-#define ETHER_TX_CTL_TXHALT_OFST                                (1)
-#define ETHER_TX_CTL_TXHALT_MSK                                 (0x2)
-#define ETHER_TX_CTL_NOPAD_OFST                                 (2)
-#define ETHER_TX_CTL_NOPAD_MSK                                  (0x4)
-#define ETHER_TX_CTL_NOCRC_OFST                                 (3)
-#define ETHER_TX_CTL_NOCRC_MSK                                  (0x8)
-#define ETHER_TX_CTL_FBACK_OFST                                 (4)
-#define ETHER_TX_CTL_FBACK_MSK                                  (0x10)
-#define ETHER_TX_CTL_NOEXDEF_OFST                               (5)
-#define ETHER_TX_CTL_NOEXDEF_MSK                                (0x20)
-#define ETHER_TX_CTL_SDPAUSE_OFST                               (6)
-#define ETHER_TX_CTL_SDPAUSE_MSK                                (0x40)
-#define ETHER_TX_CTL_MII10_OFST                                 (7)
-#define ETHER_TX_CTL_MII10_MSK                                  (0x80)
-#define ETHER_TX_CTL_ENUNDER_OFST                               (8)
-#define ETHER_TX_CTL_ENUNDER_MSK                                (0x100)
-#define ETHER_TX_CTL_ENEXDEFER_OFST                             (9)
-#define ETHER_TX_CTL_ENEXDEFER_MSK                              (0x200)
-#define ETHER_TX_CTL_ENLCARR_OFST                               (10)
-#define ETHER_TX_CTL_ENLCARR_MSK                                (0x400)
-#define ETHER_TX_CTL_ENEXCOLL_OFST                              (11)
-#define ETHER_TX_CTL_ENEXCOLL_MSK                               (0x800)
-#define ETHER_TX_CTL_ENLATECOLL_OFST                            (12)
-#define ETHER_TX_CTL_ENLATECOLL_MSK                             (0x1000)
-#define ETHER_TX_CTL_ENTXPAR_OFST                               (13)
-#define ETHER_TX_CTL_ENTXPAR_MSK                                (0x2000)
-#define ETHER_TX_CTL_ENCOMP_OFST                                (14)
-#define ETHER_TX_CTL_ENCOMP_MSK                                 (0x4000)
-#define ETHER_TX_STAT(base)                                                     (ETHER00_TYPE (base + 0xc))
-#define ETHER_TX_STAT_TXCOLL_OFST                               (0)
-#define ETHER_TX_STAT_TXCOLL_MSK                                (0xF)
-#define ETHER_TX_STAT_EXCOLL_OFST                               (4)
-#define ETHER_TX_STAT_EXCOLL_MSK                                (0x10)
-#define ETHER_TX_STAT_TXDEFER_OFST                              (5)
-#define ETHER_TX_STAT_TXDEFER_MSK                               (0x20)
-#define ETHER_TX_STAT_PAUSED_OFST                               (6)
-#define ETHER_TX_STAT_PAUSED_MSK                                (0x40)
-#define ETHER_TX_STAT_INTTX_OFST                                (7)
-#define ETHER_TX_STAT_INTTX_MSK                                 (0x80)
-#define ETHER_TX_STAT_UNDER_OFST                                (8)
-#define ETHER_TX_STAT_UNDER_MSK                                 (0x100)
-#define ETHER_TX_STAT_EXDEFER_OFST                              (9)
-#define ETHER_TX_STAT_EXDEFER_MSK                               (0x200)
-#define ETHER_TX_STAT_LCARR_OFST                                (10)
-#define ETHER_TX_STAT_LCARR_MSK                                 (0x400)
-#define ETHER_TX_STAT_TX10STAT_OFST                             (11)
-#define ETHER_TX_STAT_TX10STAT_MSK                              (0x800)
-#define ETHER_TX_STAT_LATECOLL_OFST                             (12)
-#define ETHER_TX_STAT_LATECOLL_MSK                              (0x1000)
-#define ETHER_TX_STAT_TXPAR_OFST                                (13)
-#define ETHER_TX_STAT_TXPAR_MSK                                 (0x2000)
-#define ETHER_TX_STAT_COMP_OFST                                 (14)
-#define ETHER_TX_STAT_COMP_MSK                                  (0x4000)
-#define ETHER_TX_STAT_TXHALTED_OFST                             (15)
-#define ETHER_TX_STAT_TXHALTED_MSK                              (0x8000)
-#define ETHER_TX_STAT_SQERR_OFST                                (16)
-#define ETHER_TX_STAT_SQERR_MSK                                 (0x10000)
-#define ETHER_TX_STAT_TXMCAST_OFST                              (17)
-#define ETHER_TX_STAT_TXMCAST_MSK                               (0x20000)
-#define ETHER_TX_STAT_TXBCAST_OFST                              (18)
-#define ETHER_TX_STAT_TXBCAST_MSK                               (0x40000)
-#define ETHER_TX_STAT_VLAN_OFST                                 (19)
-#define ETHER_TX_STAT_VLAN_MSK                                  (0x80000)
-#define ETHER_TX_STAT_MACC_OFST                                 (20)
-#define ETHER_TX_STAT_MACC_MSK                                  (0x100000)
-#define ETHER_TX_STAT_TXPAUSE_OFST                              (21)
-#define ETHER_TX_STAT_TXPAUSE_MSK                               (0x200000)
-#define ETHER_RX_CTL(base)                                                      (ETHER00_TYPE (base + 0x10))
-#define ETHER_RX_CTL_RXEN_OFST                                  (0)
-#define ETHER_RX_CTL_RXEN_MSK                                   (0x1)
-#define ETHER_RX_CTL_RXHALT_OFST                                (1)
-#define ETHER_RX_CTL_RXHALT_MSK                                 (0x2)
-#define ETHER_RX_CTL_LONGEN_OFST                                (2)
-#define ETHER_RX_CTL_LONGEN_MSK                                 (0x4)
-#define ETHER_RX_CTL_SHORTEN_OFST                               (3)
-#define ETHER_RX_CTL_SHORTEN_MSK                                (0x8)
-#define ETHER_RX_CTL_STRIPCRC_OFST                              (4)
-#define ETHER_RX_CTL_STRIPCRC_MSK                               (0x10)
-#define ETHER_RX_CTL_PASSCTL_OFST                               (5)
-#define ETHER_RX_CTL_PASSCTL_MSK                                (0x20)
-#define ETHER_RX_CTL_IGNORECRC_OFST                             (6)
-#define ETHER_RX_CTL_IGNORECRC_MSK                              (0x40)
-#define ETHER_RX_CTL_ENALIGN_OFST                               (8)
-#define ETHER_RX_CTL_ENALIGN_MSK                                (0x100)
-#define ETHER_RX_CTL_ENCRCERR_OFST                              (9)
-#define ETHER_RX_CTL_ENCRCERR_MSK                               (0x200)
-#define ETHER_RX_CTL_ENOVER_OFST                                (10)
-#define ETHER_RX_CTL_ENOVER_MSK                                 (0x400)
-#define ETHER_RX_CTL_ENLONGERR_OFST                             (11)
-#define ETHER_RX_CTL_ENLONGERR_MSK                              (0x800)
-#define ETHER_RX_CTL_ENRXPAR_OFST                               (13)
-#define ETHER_RX_CTL_ENRXPAR_MSK                                (0x2000)
-#define ETHER_RX_CTL_ENGOOD_OFST                                (14)
-#define ETHER_RX_CTL_ENGOOD_MSK                                 (0x4000)
-#define ETHER_RX_STAT(base)                                                     (ETHER00_TYPE (base + 0x14))
-#define ETHER_RX_STAT_LENERR_OFST                               (4)
-#define ETHER_RX_STAT_LENERR_MSK                                (0x10)
-#define ETHER_RX_STAT_CTLRECD_OFST                              (5)
-#define ETHER_RX_STAT_CTLRECD_MSK                               (0x20)
-#define ETHER_RX_STAT_INTRX_OFST                                (6)
-#define ETHER_RX_STAT_INTRX_MSK                                 (0x40)
-#define ETHER_RX_STAT_RX10STAT_OFST                             (7)
-#define ETHER_RX_STAT_RX10STAT_MSK                              (0x80)
-#define ETHER_RX_STAT_ALIGNERR_OFST                             (8)
-#define ETHER_RX_STAT_ALIGNERR_MSK                              (0x100)
-#define ETHER_RX_STAT_CRCERR_OFST                               (9)
-#define ETHER_RX_STAT_CRCERR_MSK                                (0x200)
-#define ETHER_RX_STAT_OVERFLOW_OFST                             (10)
-#define ETHER_RX_STAT_OVERFLOW_MSK                              (0x400)
-#define ETHER_RX_STAT_LONGERR_OFST                              (11)
-#define ETHER_RX_STAT_LONGERR_MSK                               (0x800)
-#define ETHER_RX_STAT_RXPAR_OFST                                (13)
-#define ETHER_RX_STAT_RXPAR_MSK                                 (0x2000)
-#define ETHER_RX_STAT_GOOD_OFST                                 (14)
-#define ETHER_RX_STAT_GOOD_MSK                                  (0x4000)
-#define ETHER_RX_STAT_RXHALTED_OFST                             (15)
-#define ETHER_RX_STAT_RXHALTED_MSK                              (0x8000)
-#define ETHER_RX_STAT_RXMCAST_OFST                              (17)
-#define ETHER_RX_STAT_RXMCAST_MSK                               (0x10000)
-#define ETHER_RX_STAT_RXBCAST_OFST                              (18)
-#define ETHER_RX_STAT_RXBCAST_MSK                               (0x20000)
-#define ETHER_RX_STAT_RXVLAN_OFST                               (19)
-#define ETHER_RX_STAT_RXVLAN_MSK                                (0x40000)
-#define ETHER_RX_STAT_RXPAUSE_OFST                              (20)
-#define ETHER_RX_STAT_RXPAUSE_MSK                               (0x80000)
-#define ETHER_RX_STAT_ARCSTATUS_OFST                            (21)
-#define ETHER_RX_STAT_ARCSTATUS_MSK                             (0xF00000)
-#define ETHER_RX_STAT_ARCENT_OFST                               (25)
-#define ETHER_RX_STAT_ARCENT_MSK                                (0x1F000000)
-#define ETHER_MD_DATA(base)                                                     (ETHER00_TYPE (base + 0x18))
-#define ETHER_MD_CA(base)                                                               (ETHER00_TYPE (base + 0x1c))
-#define ETHER_MD_CA_ADDR_OFST                                   (0)
-#define ETHER_MD_CA_ADDR_MSK                                    (0x1F)
-#define ETHER_MD_CA_PHY_OFST                                    (5)
-#define ETHER_MD_CA_PHY_MSK                                     (0x3E0)
-#define ETHER_MD_CA_WR_OFST                                     (10)
-#define ETHER_MD_CA_WR_MSK                                      (0x400)
-#define ETHER_MD_CA_BUSY_OFST                                   (11)
-#define ETHER_MD_CA_BUSY_MSK                                    (0x800)
-#define ETHER_MD_CA_PRESUPP_OFST                                (12)
-#define ETHER_MD_CA_PRESUPP_MSK                                 (0x1000)
-#define ETHER_ARC_ADR(base)           (ETHER00_TYPE (base + 0x160))
-#define ETHER_ARC_ADR_ARC_LOC_OFST                              (2)
-#define ETHER_ARC_ADR_ARC_LOC_MSK                               (0xFFC)
-#define ETHER_ARC_DATA(base)  (ETHER00_TYPE (base + 0x364))
-#define ETHER_ARC_ENA(base)   (ETHER00_TYPE (base + 0x28))
-#define ETHER_ARC_ENA_MSK                                       (0x1FFFFF)
-#define ETHER_PROM_CTL(base)                                                    (ETHER00_TYPE (base + 0x2c))
-#define ETHER_PROM_CTL_PROM_ADDR_OFST                   (0)
-#define ETHER_PROM_CTL_PROM_ADDR_MSK                    (0x3F)
-#define ETHER_PROM_CTL_OPCODE_OFST                              (13)
-#define ETHER_PROM_CTL_OPCODE_MSK                               (0x6000)
-#define ETHER_PROM_CTL_OPCODE_READ_MSK                  (0x4000)
-#define ETHER_PROM_CTL_OPCODE_WRITE_MSK                 (0x2000)
-#define ETHER_PROM_CTL_OPCODE_ERASE_MSK                 (0x6000)
-#define ETHER_PROM_CTL_ENABLE_MSK                               (0x0030)
-#define ETHER_PROM_CTL_DISABLE_MSK                              (0x0000)
-#define ETHER_PROM_CTL_BUSY_OFST                                (15)
-#define ETHER_PROM_CTL_BUSY_MSK                                 (0x8000)
-#define ETHER_PROM_DATA(base)                                                   (ETHER00_TYPE (base + 0x30))
-#define ETHER_MISS_CNT(base)                                                    (ETHER00_TYPE (base + 0x3c))
-#define ETHER_MISS_CNT_COUNT_OFST                               (0)
-#define ETHER_MISS_CNT_COUNT_MSK                                (0xFFFF)
-#define ETHER_CNTDATA(base)                                                     (ETHER00_TYPE (base + 0x80))
-#define ETHER_CNTACC(base)                                                      (ETHER00_TYPE (base + 0x84))
-#define ETHER_CNTACC_ADDR_OFST                                  (0)
-#define ETHER_CNTACC_ADDR_MSK                                   (0xFF)
-#define ETHER_CNTACC_WRRDN_OFST                                 (8)
-#define ETHER_CNTACC_WRRDN_MSK                                  (0x100)
-#define ETHER_CNTACC_CLEAR_OFST                                 (9)
-#define ETHER_CNTACC_CLEAR_MSK                                  (0x200)
-#define ETHER_TXRMINTEN(base)                                                   (ETHER00_TYPE (base + 0x88))
-#define ETHER_TXRMINTEN_MSK                                             (0x3FFFFFFF)
-#define ETHER_RXRMINTEN(base)                                                   (ETHER00_TYPE (base + 0x8C))
-#define ETHER_RXRMINTEN_MSK                                             (0xFFFFFF)
-/*
-*       RMON Registers
-*/
-#define         RMON_COLLISION0                                         0x0
-#define         RMON_COLLISION1                                         0x1
-#define         RMON_COLLISION2                                         0x2
-#define         RMON_COLLISION3                                         0x3
-#define         RMON_COLLISION4                                         0x4
-#define         RMON_COLLISION5                                         0x5
-#define         RMON_COLLISION6                                         0x6
-#define         RMON_COLLISION7                                         0x7
-#define         RMON_COLLISION8                                         0x8
-#define         RMON_COLLISION9                                         0x9
-#define         RMON_COLLISION10                                        0xa
-#define         RMON_COLLISION11                                        0xb
-#define         RMON_COLLISION12                                        0xc
-#define         RMON_COLLISION13                                        0xd
-#define         RMON_COLLISION14                                        0xe
-#define         RMON_COLLISION15                                        0xf
-#define         RMON_COLLISION16                                        0x10
-#define         RMON_FRAMES_WITH_DEFERRED_XMISSIONS     0x11
-#define         RMON_LATE_COLLISIONS                            0x12
-#define         RMON_FRAMES_LOST_DUE_TO_MAC_XMIT        0x13
-#define         RMON_CARRIER_SENSE_ERRORS                       0x14
-#define         RMON_FRAMES_WITH_EXCESSIVE_DEFERAL      0x15
-#define         RMON_UNICAST_FRAMES_TRANSMITTED_OK      0x16
-#define         RMON_MULTICAST_FRAMES_XMITTED_OK        0x17
-#define         RMON_BROADCAST_FRAMES_XMITTED_OK        0x18
-#define         RMON_SQE_TEST_ERRORS                            0x19
-#define         RMON_PAUSE_MACCTRL_FRAMES_XMITTED       0x1A
-#define         RMON_MACCTRL_FRAMES_XMITTED                     0x1B
-#define         RMON_VLAN_FRAMES_XMITTED                        0x1C
-#define         RMON_OCTETS_XMITTED_OK                          0x1D
-#define         RMON_OCTETS_XMITTED_OK_HI                       0x1E
-#define         RMON_RX_PACKET_SIZES0                           0x40
-#define         RMON_RX_PACKET_SIZES1                           0x41
-#define         RMON_RX_PACKET_SIZES2                           0x42
-#define         RMON_RX_PACKET_SIZES3                           0x43
-#define         RMON_RX_PACKET_SIZES4                           0x44
-#define         RMON_RX_PACKET_SIZES5                           0x45
-#define         RMON_RX_PACKET_SIZES6                           0x46
-#define         RMON_RX_PACKET_SIZES7                           0x47
-#define         RMON_FRAME_CHECK_SEQUENCE_ERRORS        0x48
-#define         RMON_ALIGNMENT_ERRORS                           0x49
-#define         RMON_FRAGMENTS                                          0x4A
-#define         RMON_JABBERS                                            0x4B
-#define         RMON_FRAMES_LOST_TO_INTMACRCVERR        0x4C
-#define         RMON_UNICAST_FRAMES_RCVD_OK                     0x4D
-#define         RMON_MULTICAST_FRAMES_RCVD_OK           0x4E
-#define         RMON_BROADCAST_FRAMES_RCVD_OK           0x4F
-#define         RMON_IN_RANGE_LENGTH_ERRORS                     0x50
-#define         RMON_OUT_OF_RANGE_LENGTH_ERRORS         0x51
-#define         RMON_VLAN_FRAMES_RCVD                           0x52
-#define         RMON_PAUSE_MAC_CTRL_FRAMES_RCVD         0x53
-#define         RMON_MAC_CTRL_FRAMES_RCVD                       0x54
-#define         RMON_OCTETS_RCVD_OK                                     0x55
-#define         RMON_OCTETS_RCVD_OK_HI                          0x56
-#define         RMON_OCTETS_RCVD_OTHER                          0x57
-#define         RMON_OCTETS_RCVD_OTHER_HI                       0x58
-#endif /* __ETHER00_H */
diff --git a/include/asm-arm/arch-epxa10db/excalibur.h b/include/asm-arm/arch-epxa10db/excalibur.h
deleted file mode 100644
index 5c91dd6d7822..000000000000
--- a/include/asm-arm/arch-epxa10db/excalibur.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* megafunction wizard: %ARM-Based Excalibur%
-   GENERATION: STANDARD
-   VERSION: WM1.0
-   MODULE: ARM-Based Excalibur
-   PROJECT: excalibur
-   ============================================================
-   File Name: v:\embedded\linux\bootldr\excalibur.h
-   Megafunction Name(s): ARM-Based Excalibur
-   ============================================================
-   ************************************************************
-   THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-   ************************************************************/
-#ifndef EXCALIBUR_H_INCLUDED
-#define EXCALIBUR_H_INCLUDED
-#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN
-#define EXC_DEFINE_BOOT_FROM_FLASH
-#define EXC_INPUT_CLK_FREQUENCY (50000000)
-#define EXC_AHB1_CLK_FREQUENCY (150000000)
-#define EXC_AHB2_CLK_FREQUENCY (75000000)
-#define EXC_SDRAM_CLK_FREQUENCY (75000000)
-/* Registers Block */
-#define EXC_REGISTERS_BASE (0x7fffc000)
-#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000)
-#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040)
-#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080)
-#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140)
-#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200)
-#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00)
-#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300)
-#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00)
-#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280)
-#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380)
-#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400)
-#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800)
-#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
-#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
-#define EXC_REGISTERS_SIZE (0x00004000)
-/* EBI Block(s) */
-#define EXC_EBI_BLOCK0_BASE (0x40000000)
-#define EXC_EBI_BLOCK0_SIZE (0x00400000)
-#define EXC_EBI_BLOCK0_WIDTH (8)
-#define EXC_EBI_BLOCK0_NON_CACHEABLE
-#define EXC_EBI_BLOCK1_BASE (0x40400000)
-#define EXC_EBI_BLOCK1_SIZE (0x00400000)
-#define EXC_EBI_BLOCK1_WIDTH (16)
-#define EXC_EBI_BLOCK1_NON_CACHEABLE
-#define EXC_EBI_BLOCK2_BASE (0x40800000)
-#define EXC_EBI_BLOCK2_SIZE (0x00400000)
-#define EXC_EBI_BLOCK2_WIDTH (16)
-#define EXC_EBI_BLOCK2_NON_CACHEABLE
-#define EXC_EBI_BLOCK3_BASE (0x40c00000)
-#define EXC_EBI_BLOCK3_SIZE (0x00400000)
-#define EXC_EBI_BLOCK3_WIDTH (16)
-#define EXC_EBI_BLOCK3_NON_CACHEABLE
-/* SDRAM Block(s) */
-#define EXC_SDRAM_BLOCK0_BASE (0x00000000)
-#define EXC_SDRAM_BLOCK0_SIZE (0x04000000)
-#define EXC_SDRAM_BLOCK0_WIDTH (32)
-#define EXC_SDRAM_BLOCK1_BASE (0x04000000)
-#define EXC_SDRAM_BLOCK1_SIZE (0x04000000)
-#define EXC_SDRAM_BLOCK1_WIDTH (32)
-/* Single Port SRAM Block(s) */
-#define EXC_SPSRAM_BLOCK0_BASE (0x08000000)
-#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000)
-#define EXC_SPSRAM_BLOCK1_BASE (0x08020000)
-#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000)
-/* PLD Block(s) */
-#define EXC_PLD_BLOCK0_BASE (0x80000000)
-#define EXC_PLD_BLOCK0_SIZE (0x00004000)
-#define EXC_PLD_BLOCK0_NON_CACHEABLE
-#define EXC_PLD_BLOCK1_BASE (0xf000000)
-#define EXC_PLD_BLOCK1_SIZE (0x00004000)
-#define EXC_PLD_BLOCK1_NON_CACHEABLE
-#define EXC_PLD_BLOCK2_BASE (0x80008000)
-#define EXC_PLD_BLOCK2_SIZE (0x00004000)
-#define EXC_PLD_BLOCK2_NON_CACHEABLE
-#define EXC_PLD_BLOCK3_BASE (0x8000c000)
-#define EXC_PLD_BLOCK3_SIZE (0x00004000)
-#define EXC_PLD_BLOCK3_NON_CACHEABLE
-#endif
diff --git a/include/asm-arm/arch-epxa10db/hardware.h b/include/asm-arm/arch-epxa10db/hardware.h
deleted file mode 100644
index b992c2924a77..000000000000
--- a/include/asm-arm/arch-epxa10db/hardware.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-epxa10/hardware.h
- *
- *  This file contains the hardware definitions of the Integrator.
- *
- *  Copyright (C) 1999 ARM Limited.
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/arch/platform.h>
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define IO_BASE                 0xf0000000                 // VA of IO 
-#define IO_SIZE                 0x10000000                 // How much?
-#define IO_START                EXC_REGISTERS_BASE              // PA of IO
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x) ((x) | 0xf0000000) 
-#define FLASH_VBASE             0xFE000000
-#define FLASH_SIZE              0x01000000
-#define FLASH_START             EXC_EBI_BLOCK0_BASE
-#define FLASH_VADDR(x) ((x)|0xFE000000)
-/*
- * Similar to above, but for PCI addresses (memory, IO, Config and the
- * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
- */
-#if 0
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
-#define PCIO_BASE               PCI_IO_VADDR
-#define PCIMEM_BASE             PCI_MEMORY_VADDR
-#define pcibios_assign_all_busses()     1
-#define PCIBIOS_MIN_IO          0x6000
-#define PCIBIOS_MIN_MEM         0x00100000
-#endif
-#endif
diff --git a/include/asm-arm/arch-epxa10db/int_ctrl00.h b/include/asm-arm/arch-epxa10db/int_ctrl00.h
deleted file mode 100644
index 23ec864c40bb..000000000000
--- a/include/asm-arm/arch-epxa10db/int_ctrl00.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- *  
- *  This file contains the register definitions for the Excalibur
- *  Timer TIMER00.
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __INT_CTRL00_H
-#define __INT_CTRL00_H
-#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x00 ))
-#define INT_MS_FC_MSK (0x10000)
-#define INT_MS_FC_OFST (16)
-#define INT_MS_M1_MSK (0x8000)
-#define INT_MS_M1_OFST (15)
-#define INT_MS_M0_MSK (0x4000)
-#define INT_MS_M0_OFST (14)
-#define INT_MS_AE_MSK (0x2000)
-#define INT_MS_AE_OFST (13)
-#define INT_MS_PE_MSK (0x1000)
-#define INT_MS_PE_OFST (12)
-#define INT_MS_EE_MSK (0x0800)
-#define INT_MS_EE_OFST (11)
-#define INT_MS_PS_MSK (0x0400)
-#define INT_MS_PS_OFST (10)
-#define INT_MS_T1_MSK (0x0200)
-#define INT_MS_T1_OFST (9)
-#define INT_MS_T0_MSK (0x0100)
-#define INT_MS_T0_OFST (8)
-#define INT_MS_UA_MSK (0x0080)
-#define INT_MS_UA_OFST (7)
-#define INT_MS_IP_MSK (0x0040)
-#define INT_MS_IP_OFST (6)
-#define INT_MS_P5_MSK (0x0020)
-#define INT_MS_P5_OFST (5)
-#define INT_MS_P4_MSK (0x0010)
-#define INT_MS_P4_OFST (4)
-#define INT_MS_P3_MSK (0x0008)
-#define INT_MS_P3_OFST (3)
-#define INT_MS_P2_MSK (0x0004)
-#define INT_MS_P2_OFST (2)
-#define INT_MS_P1_MSK (0x0002)
-#define INT_MS_P1_OFST (1)
-#define INT_MS_P0_MSK (0x0001)
-#define INT_MS_P0_OFST (0)
-#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x04 ))
-#define INT_MC_FC_MSK (0x10000)
-#define INT_MC_FC_OFST (16)
-#define INT_MC_M1_MSK (0x8000)
-#define INT_MC_M1_OFST (15)
-#define INT_MC_M0_MSK (0x4000)
-#define INT_MC_M0_OFST (14)
-#define INT_MC_AE_MSK (0x2000)
-#define INT_MC_AE_OFST (13)
-#define INT_MC_PE_MSK (0x1000)
-#define INT_MC_PE_OFST (12)
-#define INT_MC_EE_MSK (0x0800)
-#define INT_MC_EE_OFST (11)
-#define INT_MC_PS_MSK (0x0400)
-#define INT_MC_PS_OFST (10)
-#define INT_MC_T1_MSK (0x0200)
-#define INT_MC_T1_OFST (9)
-#define INT_MC_T0_MSK (0x0100)
-#define INT_MC_T0_OFST (8)
-#define INT_MC_UA_MSK (0x0080)
-#define INT_MC_UA_OFST (7)
-#define INT_MC_IP_MSK (0x0040)
-#define INT_MC_IP_OFST (6)
-#define INT_MC_P5_MSK (0x0020)
-#define INT_MC_P5_OFST (5)
-#define INT_MC_P4_MSK (0x0010)
-#define INT_MC_P4_OFST (4)
-#define INT_MC_P3_MSK (0x0008)
-#define INT_MC_P3_OFST (3)
-#define INT_MC_P2_MSK (0x0004)
-#define INT_MC_P2_OFST (2)
-#define INT_MC_P1_MSK (0x0002)
-#define INT_MC_P1_OFST (1)
-#define INT_MC_P0_MSK (0x0001)
-#define INT_MC_P0_OFST (0)
-#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x08 ))
-#define INT_SS_FC_SSK (0x8000)
-#define INT_SS_FC_OFST (15)
-#define INT_SS_M1_SSK (0x8000)
-#define INT_SS_M1_OFST (15)
-#define INT_SS_M0_SSK (0x4000)
-#define INT_SS_M0_OFST (14)
-#define INT_SS_AE_SSK (0x2000)
-#define INT_SS_AE_OFST (13)
-#define INT_SS_PE_SSK (0x1000)
-#define INT_SS_PE_OFST (12)
-#define INT_SS_EE_SSK (0x0800)
-#define INT_SS_EE_OFST (11)
-#define INT_SS_PS_SSK (0x0400)
-#define INT_SS_PS_OFST (10)
-#define INT_SS_T1_SSK (0x0200)
-#define INT_SS_T1_OFST (9)
-#define INT_SS_T0_SSK (0x0100)
-#define INT_SS_T0_OFST (8)
-#define INT_SS_UA_SSK (0x0080)
-#define INT_SS_UA_OFST (7)
-#define INT_SS_IP_SSK (0x0040)
-#define INT_SS_IP_OFST (6)
-#define INT_SS_P5_SSK (0x0020)
-#define INT_SS_P5_OFST (5)
-#define INT_SS_P4_SSK (0x0010)
-#define INT_SS_P4_OFST (4)
-#define INT_SS_P3_SSK (0x0008)
-#define INT_SS_P3_OFST (3)
-#define INT_SS_P2_SSK (0x0004)
-#define INT_SS_P2_OFST (2)
-#define INT_SS_P1_SSK (0x0002)
-#define INT_SS_P1_OFST (1)
-#define INT_SS_P0_SSK (0x0001)
-#define INT_SS_P0_OFST (0)
-#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x0C ))
-#define INT_RS_FC_RSK (0x10000)
-#define INT_RS_FC_OFST (16)
-#define INT_RS_M1_RSK (0x8000)
-#define INT_RS_M1_OFST (15)
-#define INT_RS_M0_RSK (0x4000)
-#define INT_RS_M0_OFST (14)
-#define INT_RS_AE_RSK (0x2000)
-#define INT_RS_AE_OFST (13)
-#define INT_RS_PE_RSK (0x1000)
-#define INT_RS_PE_OFST (12)
-#define INT_RS_EE_RSK (0x0800)
-#define INT_RS_EE_OFST (11)
-#define INT_RS_PS_RSK (0x0400)
-#define INT_RS_PS_OFST (10)
-#define INT_RS_T1_RSK (0x0200)
-#define INT_RS_T1_OFST (9)
-#define INT_RS_T0_RSK (0x0100)
-#define INT_RS_T0_OFST (8)
-#define INT_RS_UA_RSK (0x0080)
-#define INT_RS_UA_OFST (7)
-#define INT_RS_IP_RSK (0x0040)
-#define INT_RS_IP_OFST (6)
-#define INT_RS_P5_RSK (0x0020)
-#define INT_RS_P5_OFST (5)
-#define INT_RS_P4_RSK (0x0010)
-#define INT_RS_P4_OFST (4)
-#define INT_RS_P3_RSK (0x0008)
-#define INT_RS_P3_OFST (3)
-#define INT_RS_P2_RSK (0x0004)
-#define INT_RS_P2_OFST (2)
-#define INT_RS_P1_RSK (0x0002)
-#define INT_RS_P1_OFST (1)
-#define INT_RS_P0_RSK (0x0001)
-#define INT_RS_P0_OFST (0)
-#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x10 ))
-#define INT_ID_ID_MSK (0x3F)
-#define INT_ID_ID_OFST (0)
-#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x14 ))
-#define INT_PLD_PRIORITY_PRI_MSK (0x3F)
-#define INT_PLD_PRIORITY_PRI_OFST (0)
-#define INT_PLD_PRIORITY_GA_MSK (0x40)
-#define INT_PLD_PRIORITY_GA_OFST (6)
-#define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x18 ))
-#define INT_MODE_MODE_MSK (0x3)
-#define INT_MODE_MODE_OFST (0)
-#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x80 ))
-#define INT_PRIORITY_P0_PRI_MSK (0x3F)
-#define INT_PRIORITY_P0_PRI_OFST (0)
-#define INT_PRIORITY_P0_FQ_MSK (0x40)
-#define INT_PRIORITY_P0_FQ_OFST (6)
-#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x84 ))
-#define INT_PRIORITY_P1_PRI_MSK (0x3F)
-#define INT_PRIORITY_P1_PRI_OFST (0)
-#define INT_PRIORITY_P1_FQ_MSK (0x40)
-#define INT_PRIORITY_P1_FQ_OFST (6)
-#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x88 ))
-#define INT_PRIORITY_P2_PRI_MSK (0x3F)
-#define INT_PRIORITY_P2_PRI_OFST (0)
-#define INT_PRIORITY_P2_FQ_MSK (0x40)
-#define INT_PRIORITY_P2_FQ_OFST (6)
-#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x8C ))
-#define INT_PRIORITY_P3_PRI_MSK (0x3F)
-#define INT_PRIORITY_P3_PRI_OFST (0)
-#define INT_PRIORITY_P3_FQ_MSK (0x40)
-#define INT_PRIORITY_P3_FQ_OFST (6)
-#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x90 ))
-#define INT_PRIORITY_P4_PRI_MSK (0x3F)
-#define INT_PRIORITY_P4_PRI_OFST (0)
-#define INT_PRIORITY_P4_FQ_MSK (0x40)
-#define INT_PRIORITY_P4_FQ_OFST (6)
-#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x94 ))
-#define INT_PRIORITY_P5_PRI_MSK (0x3F)
-#define INT_PRIORITY_P5_PRI_OFST (0)
-#define INT_PRIORITY_P5_FQ_MSK (0x40)
-#define INT_PRIORITY_P5_FQ_OFST (6)
-#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x94 ))
-#define INT_PRIORITY_IP_PRI_MSK (0x3F)
-#define INT_PRIORITY_IP_PRI_OFST (0)
-#define INT_PRIORITY_IP_FQ_MSK (0x40)
-#define INT_PRIORITY_IP_FQ_OFST (6)
-#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x9C ))
-#define INT_PRIORITY_UA_PRI_MSK (0x3F)
-#define INT_PRIORITY_UA_PRI_OFST (0)
-#define INT_PRIORITY_UA_FQ_MSK (0x40)
-#define INT_PRIORITY_UA_FQ_OFST (6)
-#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xA0 ))
-#define INT_PRIORITY_T0_PRI_MSK (0x3F)
-#define INT_PRIORITY_T0_PRI_OFST (0)
-#define INT_PRIORITY_T0_FQ_MSK (0x40)
-#define INT_PRIORITY_T0_FQ_OFST (6)
-#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xA4 ))
-#define INT_PRIORITY_T1_PRI_MSK (0x3F)
-#define INT_PRIORITY_T1_PRI_OFST (0)
-#define INT_PRIORITY_T1_FQ_MSK (0x40)
-#define INT_PRIORITY_T1_FQ_OFST (6)
-#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xA8 ))
-#define INT_PRIORITY_PS_PRI_MSK (0x3F)
-#define INT_PRIORITY_PS_PRI_OFST (0)
-#define INT_PRIORITY_PS_FQ_MSK (0x40)
-#define INT_PRIORITY_PS_FQ_OFST (6)
-#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xAC ))
-#define INT_PRIORITY_EE_PRI_MSK (0x3F)
-#define INT_PRIORITY_EE_PRI_OFST (0)
-#define INT_PRIORITY_EE_FQ_MSK (0x40)
-#define INT_PRIORITY_EE_FQ_OFST (6)
-#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xB0 ))
-#define INT_PRIORITY_PE_PRI_MSK (0x3F)
-#define INT_PRIORITY_PE_PRI_OFST (0)
-#define INT_PRIORITY_PE_FQ_MSK (0x40)
-#define INT_PRIORITY_PE_FQ_OFST (6)
-#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xB4 ))
-#define INT_PRIORITY_AE_PRI_MSK (0x3F)
-#define INT_PRIORITY_AE_PRI_OFST (0)
-#define INT_PRIORITY_AE_FQ_MSK (0x40)
-#define INT_PRIORITY_AE_FQ_OFST (6)
-#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xB8 ))
-#define INT_PRIORITY_M0_PRI_MSK (0x3F)
-#define INT_PRIORITY_M0_PRI_OFST (0)
-#define INT_PRIORITY_M0_FQ_MSK (0x40)
-#define INT_PRIORITY_M0_FQ_OFST (6)
-#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xBC ))
-#define INT_PRIORITY_M1_PRI_MSK (0x3F)
-#define INT_PRIORITY_M1_PRI_OFST (0)
-#define INT_PRIORITY_M1_FQ_MSK (0x40)
-#define INT_PRIORITY_M1_FQ_OFST (6)
-#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xC0 ))
-#define INT_PRIORITY_FC_PRI_MSK (0x3F)
-#define INT_PRIORITY_FC_PRI_OFST (0)
-#define INT_PRIORITY_FC_FQ_MSK (0x40)
-#define INT_PRIORITY_FC_FQ_OFST (6)
-#endif /* __INT_CTRL00_H */
diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h
deleted file mode 100644
index 9fe100c9d6be..000000000000
--- a/include/asm-arm/arch-epxa10db/io.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-epxa10db/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-#include <asm/hardware.h>
-#define IO_SPACE_LIMIT 0xffff
-/*
- * Generic virtual read/write
- */
-/*#define outsw   __arch_writesw
-#define outsl   __arch_writesl
-#define outsb   __arch_writesb
-#define insb    __arch_readsb
-#define insw    __arch_readsw
-#define insl    __arch_readsl*/
-#define __io(a)                 ((void __iomem *)(a))
-#define __mem_pci(a)            (a) 
-#endif
diff --git a/include/asm-arm/arch-epxa10db/irqs.h b/include/asm-arm/arch-epxa10db/irqs.h
deleted file mode 100644
index c3758a3b5d9d..000000000000
--- a/include/asm-arm/arch-epxa10db/irqs.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-camelot/irqs.h
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* Use the Excalibur chip definitions */
-#define INT_CTRL00_TYPE
-#include "asm/arch/int_ctrl00.h"
-#define IRQ_PLD0                     INT_MS_P0_OFST
-#define IRQ_PLD1                     INT_MS_P1_OFST
-#define IRQ_PLD2                     INT_MS_P2_OFST
-#define IRQ_PLD3                     INT_MS_P3_OFST
-#define IRQ_PLD4                     INT_MS_P4_OFST
-#define IRQ_PLD5                     INT_MS_P5_OFST
-#define IRQ_EXT                      INT_MS_IP_OFST
-#define IRQ_UART                     INT_MS_UA_OFST
-#define IRQ_TIMER0                   INT_MS_T0_OFST
-#define IRQ_TIMER1                   INT_MS_T1_OFST
-#define IRQ_PLL                      INT_MS_PLL_OFST
-#define IRQ_EBI                      INT_MS_EBI_OFST
-#define IRQ_STRIPE_BRIDGE            INT_MS_PLL_OFST
-#define IRQ_AHB_BRIDGE               INT_MS_PLL_OFST
-#define IRQ_COMMRX                   INT_MS_CR_OFST
-#define IRQ_COMMTX                   INT_MS_CT_OFST
-#define IRQ_FAST_COMM                INT_MS_FC_OFST
-#define NR_IRQS                         (INT_MS_FC_OFST + 1)
diff --git a/include/asm-arm/arch-epxa10db/mode_ctrl00.h b/include/asm-arm/arch-epxa10db/mode_ctrl00.h
deleted file mode 100644
index d8a7efa12e19..000000000000
--- a/include/asm-arm/arch-epxa10db/mode_ctrl00.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef __MODE_CTRL00_H
-#define __MODE_CTRL00_H
-/*
- * Register definitions for the reset and mode control
- */
-/*
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  ))
-#define BOOT_CR_BF_MSK (0x1)
-#define BOOT_CR_BF_OFST (0)
-#define BOOT_CR_HM_MSK (0x2)
-#define BOOT_CR_HM_OFST (1)
-#define BOOT_CR_RE_MSK (0x4)
-#define BOOT_CR_RE_OFST (2)
-#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x4 ))
-#define RESET_SR_WR_MSK (0x1)
-#define RESET_SR_WR_OFST (0)
-#define RESET_SR_CR_MSK (0x2)
-#define RESET_SR_CR_OFST (1)
-#define RESET_SR_JT_MSK (0x4)
-#define RESET_SR_JT_OFST (2)
-#define RESET_SR_ER_MSK (0x8)
-#define RESET_SR_ER_OFST (3)
-#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x08 ))
-#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x20 ))
-#define SRAM0_SR_SIZE_MSK (0xFFFFF000)
-#define SRAM0_SR_SIZE_OFST (12)
-#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x24 ))
-#define SRAM1_SR_SIZE_MSK (0xFFFFF000)
-#define SRAM1_SR_SIZE_OFST (12)
-#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x30 ))
-#define DPSRAM0_SR_MODE_MSK (0xF)
-#define DPSRAM0_SR_MODE_OFST (0)
-#define DPSRAM0_SR_GLBL_MSK (0x30)
-#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000)
-#define DPSRAM0_SR_SIZE_OFST (12)
-#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x34 ))
-#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0)
-#define DPSRAM0_LCR_LCKADDR_OFST (4)
-#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x38 ))
-#define DPSRAM1_SR_MODE_MSK (0xF)
-#define DPSRAM1_SR_MODE_OFST (0)
-#define DPSRAM1_SR_GLBL_MSK (0x30)
-#define DPSRAM1_SR_GLBL_OFST (4)
-#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000)
-#define DPSRAM1_SR_SIZE_OFST (12)
-#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x3C ))
-#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0)
-#define DPSRAM1_LCR_LCKADDR_OFST (4)
-#endif /* __MODE_CTRL00_H */
diff --git a/include/asm-arm/arch-epxa10db/platform.h b/include/asm-arm/arch-epxa10db/platform.h
deleted file mode 100644
index 129bb0f212a0..000000000000
--- a/include/asm-arm/arch-epxa10db/platform.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef PLATFORM_H
-#define PLATFORM_H
-#include "excalibur.h"
-#define MAXIRQNUM 15 
-#endif
diff --git a/include/asm-arm/arch-epxa10db/pld_conf00.h b/include/asm-arm/arch-epxa10db/pld_conf00.h
deleted file mode 100644
index 7af2c38dacc6..000000000000
--- a/include/asm-arm/arch-epxa10db/pld_conf00.h
+++ /dev/null
@@ -1,73 +0,0 @@
-#ifndef __PLD_CONF00_H
-#define __PLD_CONF00_H
-/*
- * Register definitions for the PLD Configuration Logic
- */
-/*
- *  
- *  This file contains the register definitions for the Excalibur
- *  Interrupt controller INT_CTRL00.
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
- 
-#define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR))  
-#define CONFIG_CONTROL_LK_MSK (0x1)
-#define CONFIG_CONTROL_LK_OFST (0)
-#define CONFIG_CONTROL_CO_MSK (0x2)
-#define CONFIG_CONTROL_CO_OFST (1)
-#define CONFIG_CONTROL_B_MSK  (0x4)
-#define CONFIG_CONTROL_B_OFST (2)
-#define CONFIG_CONTROL_PC_MSK (0x8)
-#define CONFIG_CONTROL_PC_OFST (3)
-#define CONFIG_CONTROL_E_MSK (0x10)
-#define CONFIG_CONTROL_E_OFST (4)
-#define CONFIG_CONTROL_ES_MSK (0xE0)
-#define CONFIG_CONTROL_ES_OFST (5)
-#define CONFIG_CONTROL_ES_0_MSK (0x20)
-#define CONFIG_CONTROL_ES_1_MSK (0x40)
-#define CONFIG_CONTROL_ES_2_MSK (0x80)
-#define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0x4 ))
-#define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF)
-#define CONFIG_CONTROL_CLOCK_RATIO_OFST (0)
-#define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0x8 ))
-#define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF)
-#define CONFIG_CONTROL_DATA_OFST (0)
-#define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0xC )) 
-#define CONFIG_UNLOCK_MSK (0xFFFFFFFF)
-#define CONFIG_UNLOCK_OFST (0)
-#define CONFIG_UNLOCK_MAGIC (0x554E4C4B)
-#endif /* __PLD_CONF00_H */
diff --git a/include/asm-arm/arch-epxa10db/tdkphy.h b/include/asm-arm/arch-epxa10db/tdkphy.h
deleted file mode 100644
index 5e107bd4e109..000000000000
--- a/include/asm-arm/arch-epxa10db/tdkphy.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- *  linux/drivers/tdkphy.h
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __TDKPHY_H
-#define __TDKPHY_H
-/*
- * Register definitions for the TDK 78Q2120 PHY 
- * which is on the Camelot board
- */
-/*
- * Copyright (c) Altera Corporation 2000.
- * All rights reserved.
- */
-#define PHY_CONTROL                                                                                     (0)
-#define PHY_CONTROL_COLT_MSK                                                            (0x80)
-#define PHY_CONTROL_COLT_OFST                                                           (7)
-#define PHY_CONTROL_DUPLEX_MSK                                                          (0x100)
-#define PHY_CONTROL_DUPLEX_OFST                                                         (8)
-#define PHY_CONTROL_RANEG_MSK                                                           (0x200)
-#define PHY_CONTROL_RANEG_OFST                                                          (9)
-#define PHY_CONTROL_ISO_MSK                                                                     (0x400)
-#define PHY_CONTROL_ISO_OFST                                                            (10)
-#define PHY_CONTROL_PWRDN_MSK                                                           (0x800)
-#define PHY_CONTROL_PWRDN_OFST                                                          (11)
-#define PHY_CONTROL_ANEGEN_MSK                                                          (0x1000)
-#define PHY_CONTROL_ANEGEN_OFST                                                         (12)
-#define PHY_CONTROL_SPEEDSL_MSK                                                         (0x2000)
-#define PHY_CONTROL_SPEEDSL_OFST                                                        (13)
-#define PHY_CONTROL_LOOPBK_MSK                                                          (0x4000)
-#define PHY_CONTROL_LOOPBK_OFST                                                         (14)
-#define PHY_CONTROL_RESET_MSK                                                           (0x8000)
-#define PHY_CONTROL_RESET_OFST                                                          (15)
-#define PHY_STATUS                                                                                      (1)
-#define PHY_STATUS_ETXD_MSK                                                                     (0x1)
-#define PHY_STATUS_EXTD_OFST                                                            (0)
-#define PHY_STATUS_JAB_MSK                                                                      (0x2)
-#define PHY_STATUS_JAB_OFST                                                                     (1)
-#define PHY_STATUS_LINK_MSK                                                                     (0x4)
-#define PHY_STATUS_LINK_OFST                                                            (2)
-#define PHY_STATUS_ANEGA_MSK                                                            (0x8)
-#define PHY_STATUS_ANEGA_OFST                                                           (3)
-#define PHY_STATUS_RFAULT_MSK                                                           (0x10)
-#define PHY_STATUS_RFAULT_OFST                                                          (4)
-#define PHY_STATUS_ANEGC_MSK                                                            (0x20)
-#define PHY_STATUS_ANEGC_OFST                                                           (5)
-#define PHY_STATUS_10T_H_MSK                                                            (0x800)
-#define PHY_STATUS_10T_H_OFST                                                           (11)
-#define PHY_STATUS_10T_F_MSK                                                            (0x1000)
-#define PHY_STATUS_10T_F_OFST                                                           (12)
-#define PHY_STATUS_100_X_H_MSK                                                          (0x2000)
-#define PHY_STATUS_100_X_H_OFST                                                         (13)
-#define PHY_STATUS_100_X_F_MSK                                                          (0x4000)
-#define PHY_STATUS_100_X_F_OFST                                                         (14)
-#define PHY_STATUS_100T4_MSK                                                            (0x8000)
-#define PHY_STATUS_100T4_OFST                                                           (15)
-#define PHY_ID1                                                                                         (2)
-#define PHY_ID1_OUI_MSK                                                                         (0xFFFF)
-#define PHY_ID1_OUI_OFST                                                                        (0)
-#define PHY_ID2                                                                                         (3)
-#define PHY_ID2_RN_MSK                                                                          (0xF)
-#define PHY_ID2_RN_OFST                                                                         (0)
-#define PHY_ID2_MN_MSK                                                                          (0x3F0)
-#define PHY_ID2_MN_OFST                                                                         (4)
-#define PHY_ID2_OUI_MSK                                                                         (0xFC00)
-#define PHY_ID2_OUI_OFST                                                                        (10)
-#define PHY_AUTO_NEG_ADVERTISEMENT                                                      (4)
-#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK                         (0x1F)
-#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST                        (0)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK                                       (0x20)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST                                      (5)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK                                       (0x40)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST                                      (6)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK                                       (0x80)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST                                      (7)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK                                       (0x100)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST                                      (8)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK                                       (0x200)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST                                      (9)
-#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK                                      (0x1FE0)
-#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST                                     (5)
-#define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK                                       (0x2000)
-#define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST                                      (13)
-#define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK                                     (0x4000)
-#define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST                            (14)
-#define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK                                       (0x8000)
-#define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST                                      (15)
-#define PHY_AUTO_NEG_LINK_PARTNER                                                       (5)
-#define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK                                        (0x1F)
-#define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST                                       (0)
-#define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK                                        (0x1FE0)
-#define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST                                       (5)
-#define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK                                        (0x2000)
-#define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST                                       (13)
-#define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK                                       (0x4000)
-#define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST                                      (14)
-#define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK                                        (0x8000)
-#define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST                                       (15)
-#define PHY_AUTO_NEG_EXPANSION                                                          (6)
-#define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK                                      (0x1)
-#define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST                                     (0)
-#define PHY_AUTO_NEG_EXPANSION_PRX_MSK                                          (0x2)
-#define PHY_AUTO_NEG_EXPANSION_PRX_OFST                                         (1)
-#define PHY_AUTO_NEG_EXPANSION_NPA_MSK                                          (0x4)
-#define PHY_AUTO_NEG_EXPANSION_NPA_OFST                                         (2)
-#define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK                                        (0x8)
-#define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST                                       (3)
-#define PHY_AUTO_NEG_EXPANSION_PDF_MSK                                          (0x10)
-#define PHY_AUTO_NEG_EXPANSION_PDF_OFST                                         (4)
-#define PHY_VENDOR_SPECIFIC                                                                     (16)
-#define PHY_VENDOR_SPECIFIC_RXCC_MSK                                            (0x1)
-#define PHY_VENDOR_SPECIFIC_RXCC_OFST                                           (0)
-#define PHY_VENDOR_SPECIFIC_PCSBP_MSK                                           (0x2)
-#define PHY_VENDOR_SPECIFIC_PCSBP_OFST                                          (1)
-#define PHY_VENDOR_SPECIFIC_RVSPOL_MSK                                          (0x10)
-#define PHY_VENDOR_SPECIFIC_RVSPOL_OFST                                         (4)
-#define PHY_VENDOR_SPECIFIC_APOL_MSK                                            (0x20)  
-#define PHY_VENDOR_SPECIFIC_APOL_OFST                                           (5)
-#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK                                       (0x40)
-#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST                                      (6)
-#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK                                       (0x80)
-#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST                                      (7)
-#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK                                       (0x100)
-#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST                                      (8)
-#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK                                       (0x200)
-#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST                                      (9)
-#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK       (0x400)
-#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST      (10)
-#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK           (0x800)
-#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST          (11)
-#define PHY_VENDOR_SPECIFIC_TXHIM_MSK                                           (0x1000)
-#define PHY_VENDOR_SPECIFIC_TXHIM_OFST                                          (12)
-#define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK                                       (0x4000)
-#define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST                                      (14)
-#define PHY_VENDOR_SPECIFIC_RPTR_MSK                                            (0x8000)
-#define PHY_VENDOR_SPECIFIC_RPTR_OFST                                           (15)
-#define PHY_IRQ_CONTROL                                                                         (17)
-#define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK                                       (0x1)
-#define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST                                      (0)
-#define PHY_IRQ_CONTROL_RFAULT_INT_MSK                                          (0x2)
-#define PHY_IRQ_CONTROL_RFAULT_INT_OFST                                         (1)
-#define PHY_IRQ_CONTROL_LS_CHG_INT_MSK                                          (0x4)
-#define PHY_IRQ_CONTROL_LS_CHG_INT_OFST                                         (2)
-#define PHY_IRQ_CONTROL_LP_ACK_INT_MSK                                          (0x8)
-#define PHY_IRQ_CONTROL_LP_ACK_INT_OFST                                         (3)
-#define PHY_IRQ_CONTROL_PDF_INT_MSK                                                     (0x10)
-#define PHY_IRQ_CONTROL_PDF_INT_OFST                                            (4)
-#define PHY_IRQ_CONTROL_PRX_INT_MSK                                                     (0x20)
-#define PHY_IRQ_CONTROL_PRX_INT_OFST                                            (5)
-#define PHY_IRQ_CONTROL_RXER_INT_MSK                                            (0x40)
-#define PHY_IRQ_CONTROL_RXER_INT_OFST                                           (6)
-#define PHY_IRQ_CONTROL_JABBER_INT_MSK                                          (0x80)
-#define PHY_IRQ_CONTROL_JABBER_INT_OFST                                         (7)
-#define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK                                        (0x100)
-#define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST                                       (8)
-#define PHY_IRQ_CONTROL_RFAULT_IE_MSK                                           (0x200)
-#define PHY_IRQ_CONTROL_RFAULT_IE_OFST                                          (9)
-#define PHY_IRQ_CONTROL_LS_CHG_IE_MSK                                           (0x400)
-#define PHY_IRQ_CONTROL_LS_CHG_IE_OFST                                          (10)
-#define PHY_IRQ_CONTROL_LP_ACK_IE_MSK                                           (0x800)
-#define PHY_IRQ_CONTROL_LP_ACK_IE_OFST                                          (11)
-#define PHY_IRQ_CONTROL_PDF_IE_MSK                                                      (0x1000)
-#define PHY_IRQ_CONTROL_PDF_IE_OFST                                                     (12)
-#define PHY_IRQ_CONTROL_PRX_IE_MSK                                                      (0x2000)
-#define PHY_IRQ_CONTROL_PRX_IE_OFST                                                     (13)
-#define PHY_IRQ_CONTROL_RXER_IE_MSK                                                     (0x4000)
-#define PHY_IRQ_CONTROL_RXER_IE_OFST                                            (14)
-#define PHY_IRQ_CONTROL_JABBER_IE_MSK                                           (0x8000)
-#define PHY_IRQ_CONTROL_JABBER_IE_OFST                                          (15)
-#define PHY_DIAGNOSTIC                                                                          (18)
-#define PHY_DIAGNOSTIC_RX_LOCK_MSK                                                      (0x100)
-#define PHY_DIAGNOSTIC_RX_LOCK_OFST                                                     (8)
-#define PHY_DIAGNOSTIC_RX_PASS_MSK                                                      (0x200)
-#define PHY_DIAGNOSTIC_RX_PASS_OFST                                                     (9)
-#define PHY_DIAGNOSTIC_RATE_MSK                                                         (0x400)
-#define PHY_DIAGNOSTIC_RATE_OFST                                                        (10)
-#define PHY_DIAGNOSTIC_DPLX_MSK                                                         (0x800)
-#define PHY_DIAGNOSTIC_DPLX_OFST                                                        (11)
-#define PHY_DIAGNOSTIC_ANEGF_MSK                                                        (0x1000)
-#define PHY_DIAGNOSTIC_ANEGF_OFST                                                       (12)
-#endif /* __TDKPHY_H */
diff --git a/include/asm-arm/arch-epxa10db/timer00.h b/include/asm-arm/arch-epxa10db/timer00.h
deleted file mode 100644
index 52a3fb58b59d..000000000000
--- a/include/asm-arm/arch-epxa10db/timer00.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- *  
- *  This file contains the register definitions for the Excalibur
- *  Timer TIMER00.
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __TIMER00_H
-#define __TIMER00_H
-/*
- * Register definitions for the timers
- */
-#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x00 ))
-#define TIMER0_CR_B_MSK (0x20)
-#define TIMER0_CR_B_OFST (0x5)
-#define TIMER0_CR_S_MSK  (0x10)
-#define TIMER0_CR_S_OFST (0x4)
-#define TIMER0_CR_CI_MSK (0x08)
-#define TIMER0_CR_CI_OFST (0x3)
-#define TIMER0_CR_IE_MSK (0x04)
-#define TIMER0_CR_IE_OFST (0x2)
-#define TIMER0_CR_MODE_MSK (0x3)
-#define TIMER0_CR_MODE_OFST (0)
-#define TIMER0_CR_MODE_FREE (0)
-#define TIMER0_CR_MODE_ONE  (1)
-#define TIMER0_CR_MODE_INTVL (2)
-#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x00 ))
-#define TIMER0_SR_B_MSK (0x20)
-#define TIMER0_SR_B_OFST (0x5)
-#define TIMER0_SR_S_MSK  (0x10)
-#define TIMER0_SR_S_OFST (0x4)
-#define TIMER0_SR_CI_MSK (0x08)
-#define TIMER0_SR_CI_OFST (0x3)
-#define TIMER0_SR_IE_MSK (0x04)
-#define TIMER0_SR_IE_OFST (0x2)
-#define TIMER0_SR_MODE_MSK (0x3)
-#define TIMER0_SR_MODE_OFST (0)
-#define TIMER0_SR_MODE_FREE (0)
-#define TIMER0_SR_MODE_ONE  (1)
-#define TIMER0_SR_MODE_INTVL (2)
-#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x010 ))
-#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x020 ))
-#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x030 ))
-#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x40 ))
-#define TIMER1_CR_B_MSK (0x20)
-#define TIMER1_CR_B_OFST (0x5)
-#define TIMER1_CR_S_MSK  (0x10)
-#define TIMER1_CR_S_OFST (0x4)
-#define TIMER1_CR_CI_MSK (0x08)
-#define TIMER1_CR_CI_OFST (0x3)
-#define TIMER1_CR_IE_MSK (0x04)
-#define TIMER1_CR_IE_OFST (0x2)
-#define TIMER1_CR_MODE_MSK (0x3)
-#define TIMER1_CR_MODE_OFST (0)
-#define TIMER1_CR_MODE_FREE (0)
-#define TIMER1_CR_MODE_ONE  (1)
-#define TIMER1_CR_MODE_INTVL (2)
-#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x40 ))
-#define TIMER1_SR_B_MSK (0x20)
-#define TIMER1_SR_B_OFST (0x5)
-#define TIMER1_SR_S_MSK  (0x10)
-#define TIMER1_SR_S_OFST (0x4)
-#define TIMER1_SR_CI_MSK (0x08)
-#define TIMER1_SR_CI_OFST (0x3)
-#define TIMER1_SR_IE_MSK (0x04)
-#define TIMER1_SR_IE_OFST (0x2)
-#define TIMER1_SR_MODE_MSK (0x3)
-#define TIMER1_SR_MODE_OFST (0)
-#define TIMER1_SR_MODE_FREE (0)
-#define TIMER1_SR_MODE_ONE  (1)
-#define TIMER1_SR_MODE_INTVL (2)
-#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x050 ))
-#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x060 ))
-#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x070 ))
-#endif /* __TIMER00_H */
diff --git a/include/asm-arm/arch-epxa10db/uart00.h b/include/asm-arm/arch-epxa10db/uart00.h
deleted file mode 100644
index 5abd8914d68b..000000000000
--- a/include/asm-arm/arch-epxa10db/uart00.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __UART00_H
-#define __UART00_H
-/*
- * Register definitions for the UART
- */
-#define UART_TX_FIFO_SIZE      (15)
-#define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x00 ))
-#define UART_RSR_RX_LEVEL_MSK (0x1f)
-#define UART_RSR_RX_LEVEL_OFST (0)
-#define UART_RSR_RE_MSK (0x80)
-#define UART_RSR_RE_OFST (7)
-#define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x04 ))
-#define UART_RDS_BI_MSK (0x8)
-#define UART_RDS_BI_OFST (4)
-#define UART_RDS_FE_MSK (0x4)
-#define UART_RDS_FE_OFST (2)
-#define UART_RDS_PE_MSK (0x2)
-#define UART_RDS_PE_OFST (1)
-#define UART_RDS_OE_MSK (0x1)
-#define UART_RDS_OE_OFST (0)
-#define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x08 ))
-#define UART_RD_RX_DATA_MSK (0xff)
-#define UART_RD_RX_DATA_OFST (0)
-#define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x0c ))
-#define UART_TSR_TX_LEVEL_MSK (0x1f)
-#define UART_TSR_TX_LEVEL_OFST (0)
-#define UART_TSR_TXI_MSK (0x80)
-#define UART_TSR_TXI_OFST (7)
-#define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x10 ))
-#define UART_TD_TX_DATA_MSK (0xff)
-#define UART_TD_TX_DATA_OFST (0)
-#define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x14 ))
-#define UART_FCR_RX_THR_MSK (0xd0)
-#define UART_FCR_RX_THR_OFST (5)
-#define UART_FCR_RX_THR_1 (0x00)
-#define UART_FCR_RX_THR_2 (0x20)
-#define UART_FCR_RX_THR_4 (0x40)
-#define UART_FCR_RX_THR_6 (0x60)
-#define UART_FCR_RX_THR_8 (0x80)
-#define UART_FCR_RX_THR_10 (0xa0)
-#define UART_FCR_RX_THR_12 (0xc0)
-#define UART_FCR_RX_THR_14 (0xd0)
-#define UART_FCR_TX_THR_MSK (0x1c)
-#define UART_FCR_TX_THR_OFST (2)
-#define UART_FCR_TX_THR_0 (0x00)
-#define UART_FCR_TX_THR_2 (0x04)
-#define UART_FCR_TX_THR_4 (0x08)
-#define UART_FCR_TX_THR_8 (0x0c)
-#define UART_FCR_TX_THR_10 (0x10)
-#define UART_FCR_TX_THR_12 (0x14)
-#define UART_FCR_TX_THR_14 (0x18)
-#define UART_FCR_TX_THR_15 (0x1c)
-#define UART_FCR_RC_MSK (0x02)
-#define UART_FCR_RC_OFST (1)
-#define UART_FCR_TC_MSK (0x01)
-#define UART_FCR_TC_OFST (0)
-#define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x18 ))
-#define UART_IES_ME_MSK (0x8)
-#define UART_IES_ME_OFST (3)
-#define UART_IES_TIE_MSK (0x4)
-#define UART_IES_TIE_OFST (2)
-#define UART_IES_TE_MSK (0x2)
-#define UART_IES_TE_OFST (1)
-#define UART_IES_RE_MSK (0x1)
-#define UART_IES_RE_OFST (0)
-#define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x1c ))
-#define UART_IEC_ME_MSK (0x8)
-#define UART_IEC_ME_OFST (3)
-#define UART_IEC_TIE_MSK (0x4)
-#define UART_IEC_TIE_OFST (2)
-#define UART_IEC_TE_MSK (0x2)
-#define UART_IEC_TE_OFST (1)
-#define UART_IEC_RE_MSK (0x1)
-#define UART_IEC_RE_OFST (0)
-#define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x20 ))
-#define UART_ISR_MI_MSK (0x8)
-#define UART_ISR_MI_OFST (3)
-#define UART_ISR_TII_MSK (0x4)
-#define UART_ISR_TII_OFST (2)
-#define UART_ISR_TI_MSK (0x2)
-#define UART_ISR_TI_OFST (1)
-#define UART_ISR_RI_MSK (0x1)
-#define UART_ISR_RI_OFST (0)
-#define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x24 ))
-#define UART_IID_IID_MSK (0x7)
-#define UART_IID_IID_OFST (0)
-#define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x28 ))
-#define UART_MC_OE_MSK (0x40)
-#define UART_MC_OE_OFST (6)
-#define UART_MC_SP_MSK (0x20)
-#define UART_MC_SP_OFST (5)
-#define UART_MC_EP_MSK (0x10)
-#define UART_MC_EP_OFST (4)
-#define UART_MC_PE_MSK (0x08)
-#define UART_MC_PE_OFST (3)
-#define UART_MC_ST_MSK (0x04)
-#define UART_MC_ST_ONE (0x0)
-#define UART_MC_ST_TWO (0x04)
-#define UART_MC_ST_OFST (2)
-#define UART_MC_CLS_MSK (0x03)
-#define UART_MC_CLS_OFST (0)
-#define UART_MC_CLS_CHARLEN_5 (0)
-#define UART_MC_CLS_CHARLEN_6 (1)
-#define UART_MC_CLS_CHARLEN_7 (2)
-#define UART_MC_CLS_CHARLEN_8 (3)
-#define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x2c ))
-#define UART_MCR_AC_MSK (0x80)
-#define UART_MCR_AC_OFST (7)
-#define UART_MCR_AR_MSK (0x40)
-#define UART_MCR_AR_OFST (6)
-#define UART_MCR_BR_MSK (0x20)
-#define UART_MCR_BR_OFST (5)
-#define UART_MCR_LB_MSK (0x10)
-#define UART_MCR_LB_OFST (4)
-#define UART_MCR_DCD_MSK (0x08)
-#define UART_MCR_DCD_OFST (3)
-#define UART_MCR_RI_MSK (0x04)
-#define UART_MCR_RI_OFST (2)
-#define UART_MCR_DTR_MSK (0x02)
-#define UART_MCR_DTR_OFST (1)
-#define UART_MCR_RTS_MSK (0x01)
-#define UART_MCR_RTS_OFST (0)
-#define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x30 ))
-#define UART_MSR_DCD_MSK (0x80)
-#define UART_MSR_DCD_OFST (7)
-#define UART_MSR_RI_MSK (0x40)
-#define UART_MSR_RI_OFST (6)
-#define UART_MSR_DSR_MSK (0x20)
-#define UART_MSR_DSR_OFST (5)
-#define UART_MSR_CTS_MSK (0x10)
-#define UART_MSR_CTS_OFST (4)
-#define UART_MSR_DDCD_MSK (0x08)
-#define UART_MSR_DDCD_OFST (3)
-#define UART_MSR_TERI_MSK (0x04)
-#define UART_MSR_TERI_OFST (2)
-#define UART_MSR_DDSR_MSK (0x02)
-#define UART_MSR_DDSR_OFST (1)
-#define UART_MSR_DCTS_MSK (0x01)
-#define UART_MSR_DCTS_OFST (0)
-#define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x34 ))
-#define UART_DIV_LO_DIV_MSK (0xff)
-#define UART_DIV_LO_DIV_OFST (0)
-#define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x38 ))
-#define UART_DIV_HI_DIV_MSK (0xff)
-#define UART_DIV_HI_DIV_OFST (0)
-#endif /* __UART00_H */
diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h
deleted file mode 100644
index fdfe0e6848f8..000000000000
--- a/include/asm-arm/arch-epxa10db/uncompress.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-epxa10db/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include "asm/arch/platform.h"
-#include "asm/hardware.h"
-#define UART00_TYPE (volatile unsigned int*)
-#include "asm/arch/uart00.h"
-/*
- * This does not append a newline
- */
-static void putstr(const char *s)
-{
-        while (*s) {
-                while ((*UART_TSR(EXC_UART00_BASE) &
-                       UART_TSR_TX_LEVEL_MSK)==15)
-                        barrier();
-                *UART_TD(EXC_UART00_BASE) = *s;
-                if (*s == '\n') {
-                        while ((*UART_TSR(EXC_UART00_BASE) &
-                               UART_TSR_TX_LEVEL_MSK)==15)
-                                barrier();
-                        *UART_TD(EXC_UART00_BASE) = '\r';
-                }
-                s++;
-        }
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-imx/dma.h b/include/asm-arm/arch-imx/dma.h
index dbdc01780413..b45fa367d71e 100644
--- a/include/asm-arm/arch-imx/dma.h
+++ b/include/asm-arm/arch-imx/dma.h
@@ -20,10 +20,6 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-#define MAX_DMA_CHANNELS        0
 /*
 * DMA registration
 */
diff --git a/include/asm-arm/arch-imx/entry-macro.S b/include/asm-arm/arch-imx/entry-macro.S
index b40ea7cf88ec..3b9ef6914627 100644
--- a/include/asm-arm/arch-imx/entry-macro.S
+++ b/include/asm-arm/arch-imx/entry-macro.S
@@ -7,6 +7,8 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware.h>
                .macro  disable_fiq
                .endm
 #define AITC_NIVECSR   0x40
diff --git a/include/asm-arm/arch-integrator/debug-macro.S b/include/asm-arm/arch-integrator/debug-macro.S
index 484a1aa47098..031d30941791 100644
--- a/include/asm-arm/arch-integrator/debug-macro.S
+++ b/include/asm-arm/arch-integrator/debug-macro.S
@@ -11,7 +11,7 @@
 *
 */
-#include <asm/hardware/amba_serial.h>
+#include <linux/amba/serial.h>
                .macro  addruart,rx
                mrc     p15, 0, \rx, c1, c0
diff --git a/include/asm-arm/arch-integrator/dma.h b/include/asm-arm/arch-integrator/dma.h
index 7171792290bd..83fd6bbaf9d3 100644
--- a/include/asm-arm/arch-integrator/dma.h
+++ b/include/asm-arm/arch-integrator/dma.h
@@ -17,12 +17,3 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-#define MAX_DMA_CHANNELS        0
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-integrator/entry-macro.S b/include/asm-arm/arch-integrator/entry-macro.S
index 44f7ee613194..69838d04f90b 100644
--- a/include/asm-arm/arch-integrator/entry-macro.S
+++ b/include/asm-arm/arch-integrator/entry-macro.S
@@ -7,6 +7,8 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware.h>
+#include <asm/arch/irqs.h>
                .macro  disable_fiq
                .endm
diff --git a/include/asm-arm/arch-iop3xx/dma.h b/include/asm-arm/arch-iop3xx/dma.h
index 797f9e6fc745..1e808db8af2a 100644
--- a/include/asm-arm/arch-iop3xx/dma.h
+++ b/include/asm-arm/arch-iop3xx/dma.h
@@ -7,10 +7,3 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#ifndef _IOP3XX_DMA_H_P
-#define _IOP3XX_DMA_H_P
-#define MAX_DMA_ADDRESS         0xffffffff
-#endif /* _ASM_ARCH_DMA_H_P */
diff --git a/include/asm-arm/arch-iop3xx/entry-macro.S b/include/asm-arm/arch-iop3xx/entry-macro.S
index e2ce7f5467c8..926668c098a5 100644
--- a/include/asm-arm/arch-iop3xx/entry-macro.S
+++ b/include/asm-arm/arch-iop3xx/entry-macro.S
@@ -7,6 +7,7 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/arch/irqs.h>
 #if defined(CONFIG_ARCH_IOP321)
                .macro  disable_fiq
diff --git a/include/asm-arm/arch-ixp2000/dma.h b/include/asm-arm/arch-ixp2000/dma.h
index 0fb3568a98dd..548d8dc507eb 100644
--- a/include/asm-arm/arch-ixp2000/dma.h
+++ b/include/asm-arm/arch-ixp2000/dma.h
@@ -7,12 +7,3 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-/* No DMA */
-#define MAX_DMA_CHANNELS        0
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h
index 95128d9f5026..42f3c28dc5c4 100644
--- a/include/asm-arm/arch-ixp2000/enp2611.h
+++ b/include/asm-arm/arch-ixp2000/enp2611.h
@@ -36,5 +36,11 @@
 #define ENP2611_GPIO_SCL                7
 #define ENP2611_GPIO_SDA                6
+#define IRQ_ENP2611_THERMAL             IRQ_IXP2000_GPIO4
+#define IRQ_ENP2611_OPTION_BOARD        IRQ_IXP2000_GPIO3
+#define IRQ_ENP2611_CALEB               IRQ_IXP2000_GPIO2
+#define IRQ_ENP2611_PM3386_1            IRQ_IXP2000_GPIO1
+#define IRQ_ENP2611_PM3386_0            IRQ_IXP2000_GPIO0
 #endif
diff --git a/include/asm-arm/arch-ixp2000/entry-macro.S b/include/asm-arm/arch-ixp2000/entry-macro.S
index e3a4e4121298..16e1e6124b31 100644
--- a/include/asm-arm/arch-ixp2000/entry-macro.S
+++ b/include/asm-arm/arch-ixp2000/entry-macro.S
@@ -7,6 +7,7 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/arch/irqs.h>
                .macro  disable_fiq
                .endm
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index 7fbcdf9931ee..c0ff2c6c66e7 100644
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -131,102 +131,4 @@
 #endif
-#ifdef CONFIG_ARCH_IXDP2X01
-/*
- * This is an ugly hack but the CS8900 on the 2x01's does not sit in any sort
- * of "I/O space" and is just direct mapped into a 32-bit-only addressable
- * bus. The address space for this bus is such that we can't really easily
- * make it contiguous to the PCI I/O address range, and it also does not
- * need swapping like PCI addresses do (IXDP2x01 is a BE platform).
- * B/C of this we can't use the standard in/out functions and need to
- * runtime check if the incoming address is a PCI address or for
- * the CS89x0.
- */
-#undef inw
-#undef outw
-#undef insw
-#undef outsw
-#include <asm/mach-types.h>
-static inline void insw(u32 ptr, void *buf, int length)
-{
-        register volatile u32 *port = (volatile u32 *)ptr;
-        /*
-         * Is this cycle meant for the CS8900?
-         */
-        if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
-                (((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
-                 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
-                u8 *buf8 = (u8*)buf;
-                register u32 tmp32;
-                do {
-                        tmp32 = *port;
-                        *buf8++ = (u8)tmp32;
-                        *buf8++ = (u8)(tmp32 >> 8);
-                } while(--length);
-                return;
-        }
-        __raw_readsw(alignw(___io(ptr)),buf,length);
-}
-static inline void outsw(u32 ptr, void *buf, int length)
-{
-        register volatile u32 *port = (volatile u32 *)ptr;
-        /*
-         * Is this cycle meant for the CS8900?
-         */
-        if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
-                (((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
-                 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
-                register u32 tmp32;
-                u8 *buf8 = (u8*)buf;
-                do {
-                        tmp32 = *buf8++;
-                        tmp32 |= (*buf8++) << 8;
-                        *port = tmp32;
-                } while(--length);
-                return;
-        }
-        __raw_writesw(alignw(___io(ptr)),buf,length);
-}
-static inline u16 inw(u32 ptr)
-{
-        register volatile u32 *port = (volatile u32 *)ptr;
-        /*
-         * Is this cycle meant for the CS8900?
-         */
-        if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
-                (((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
-                 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
-                return (u16)(*port);  
-        }
-        return __raw_readw(alignw(___io(ptr)));
-}
-static inline void outw(u16 value, u32 ptr)
-{
-        register volatile u32 *port = (volatile u32 *)ptr;
-        if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
-                (((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
-                 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
-                *port = value;  
-                return;
-        }
-        __raw_writew((value),alignw(___io(ptr)));
-}
-#endif  /* IXDP2x01 */
 #endif
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index fc5ac6aec4f2..2b57f91b4ebd 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -26,6 +26,8 @@
 * fc000000     da000000        16M             PCI CFG0
 * fd000000     d8000000        16M             PCI I/O
 * fe[0-7]00000                 8M              per-platform mappings
+ * fe900000     80000000        1M              SRAM #0 (first MB)
+ * fea00000     cb400000        1M              SCRATCH ring get/put
 * feb00000     c8000000        1M              MSF
 * fec00000     df000000        1M              PCI CSRs
 * fed00000     de000000        1M              PCI CREG
@@ -91,6 +93,14 @@
 #define IXP2000_MSF_VIRT_BASE           0xfeb00000
 #define IXP2000_MSF_SIZE                0x00100000
+#define IXP2000_SCRATCH_RING_PHYS_BASE  0xcb400000
+#define IXP2000_SCRATCH_RING_VIRT_BASE  0xfea00000
+#define IXP2000_SCRATCH_RING_SIZE       0x00100000
+#define IXP2000_SRAM0_PHYS_BASE         0x80000000
+#define IXP2000_SRAM0_VIRT_BASE         0xfe900000
+#define IXP2000_SRAM0_SIZE              0x00100000
 #define IXP2000_PCI_IO_PHYS_BASE        0xd8000000
 #define IXP2000_PCI_IO_VIRT_BASE        0xfd000000
 #define IXP2000_PCI_IO_SIZE             0x01000000
@@ -156,6 +166,14 @@
 #define IXP2000_IRQ_THD_RAW_STATUS_B_1  IXP2000_INTCTL_REG(0x84)
 #define IXP2000_IRQ_THD_RAW_STATUS_B_2  IXP2000_INTCTL_REG(0x88)
 #define IXP2000_IRQ_THD_RAW_STATUS_B_3  IXP2000_INTCTL_REG(0x8c)
+#define IXP2000_IRQ_THD_STATUS_A_0      IXP2000_INTCTL_REG(0xe0)
+#define IXP2000_IRQ_THD_STATUS_A_1      IXP2000_INTCTL_REG(0xe4)
+#define IXP2000_IRQ_THD_STATUS_A_2      IXP2000_INTCTL_REG(0xe8)
+#define IXP2000_IRQ_THD_STATUS_A_3      IXP2000_INTCTL_REG(0xec)
+#define IXP2000_IRQ_THD_STATUS_B_0      IXP2000_INTCTL_REG(0x100)
+#define IXP2000_IRQ_THD_STATUS_B_1      IXP2000_INTCTL_REG(0x104)
+#define IXP2000_IRQ_THD_STATUS_B_2      IXP2000_INTCTL_REG(0x108)
+#define IXP2000_IRQ_THD_STATUS_B_3      IXP2000_INTCTL_REG(0x10c)
 #define IXP2000_IRQ_THD_ENABLE_SET_A_0  IXP2000_INTCTL_REG(0x160)
 #define IXP2000_IRQ_THD_ENABLE_SET_A_1  IXP2000_INTCTL_REG(0x164)
 #define IXP2000_IRQ_THD_ENABLE_SET_A_2  IXP2000_INTCTL_REG(0x168)
diff --git a/include/asm-arm/arch-ixp4xx/coyote.h b/include/asm-arm/arch-ixp4xx/coyote.h
index dd0c2d2d8503..7ac9ba2c035c 100644
--- a/include/asm-arm/arch-ixp4xx/coyote.h
+++ b/include/asm-arm/arch-ixp4xx/coyote.h
@@ -16,9 +16,6 @@
 #error "Do not include this directly, instead #include <asm/hardware.h>"
 #endif
-#define COYOTE_FLASH_BASE       IXP4XX_EXP_BUS_CS0_BASE_PHYS
-#define COYOTE_FLASH_SIZE       IXP4XX_EXP_BUS_CSX_REGION_SIZE * 2
 /* PCI controller GPIO to IRQ pin mappings */
 #define COYOTE_PCI_SLOT0_PIN    6
 #define COYOTE_PCI_SLOT1_PIN    11
@@ -26,7 +23,7 @@
 #define COYOTE_PCI_SLOT0_DEVID  14
 #define COYOTE_PCI_SLOT1_DEVID  15
-#define COYOTE_IDE_BASE_PHYS    IXP4XX_EXP_BUS_CS3_BASE_PHYS
+#define COYOTE_IDE_BASE_PHYS    IXP4XX_EXP_BUS_BASE(3)
 #define COYOTE_IDE_BASE_VIRT    0xFFFE1000
 #define COYOTE_IDE_REGION_SIZE  0x1000
diff --git a/include/asm-arm/arch-ixp4xx/dma.h b/include/asm-arm/arch-ixp4xx/dma.h
index 312065dc0e7a..b1a071ecebc8 100644
--- a/include/asm-arm/arch-ixp4xx/dma.h
+++ b/include/asm-arm/arch-ixp4xx/dma.h
@@ -20,7 +20,4 @@
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_64M)
-/* No DMA */
-#define MAX_DMA_CHANNELS        0
 #endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S
index 323b0bc4a39c..27e124132e4c 100644
--- a/include/asm-arm/arch-ixp4xx/entry-macro.S
+++ b/include/asm-arm/arch-ixp4xx/entry-macro.S
@@ -7,6 +7,7 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware.h>
                .macro  disable_fiq
                .endm
diff --git a/include/asm-arm/arch-ixp4xx/gtwx5715.h b/include/asm-arm/arch-ixp4xx/gtwx5715.h
index fc460af70627..c3069d67c00e 100644
--- a/include/asm-arm/arch-ixp4xx/gtwx5715.h
+++ b/include/asm-arm/arch-ixp4xx/gtwx5715.h
@@ -57,10 +57,6 @@
 #define GTWX5715_GPIO13_IRQ             IRQ_IXP4XX_SW_INT1
 #define GTWX5715_GPIO14_IRQ             IRQ_IXP4XX_SW_INT2
-#define GTWX5715_FLASH_BASE     IXP4XX_EXP_BUS_CS0_BASE_PHYS
-#define GTWX5715_FLASH_SIZE     (0x00800000)
 /* PCI controller GPIO to IRQ pin mappings
                        INTA    INTB
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index cfb413c845f7..6acb69c95ef9 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -45,5 +45,6 @@ extern unsigned int processor_id;
 #include "coyote.h"
 #include "prpmc1100.h"
 #include "nslu2.h"
+#include "nas100d.h"
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
index 2cf4930372bc..f24b763ca18e 100644
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -100,4 +100,13 @@
 #define        IRQ_NSLU2_PCI_INTB      IRQ_IXP4XX_GPIO10
 #define        IRQ_NSLU2_PCI_INTC      IRQ_IXP4XX_GPIO9
+/*
+ * NAS100D board IRQs
+ */
+#define        IRQ_NAS100D_PCI_INTA    IRQ_IXP4XX_GPIO11
+#define        IRQ_NAS100D_PCI_INTB    IRQ_IXP4XX_GPIO10
+#define        IRQ_NAS100D_PCI_INTC    IRQ_IXP4XX_GPIO9
+#define        IRQ_NAS100D_PCI_INTD    IRQ_IXP4XX_GPIO8
+#define        IRQ_NAS100D_PCI_INTE    IRQ_IXP4XX_GPIO7
 #endif
diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h
index 7d21bf941379..3d3820d7ba09 100644
--- a/include/asm-arm/arch-ixp4xx/ixdp425.h
+++ b/include/asm-arm/arch-ixp4xx/ixdp425.h
@@ -16,9 +16,6 @@
 #error "Do not include this directly, instead #include <asm/hardware.h>"
 #endif
-#define IXDP425_FLASH_BASE      IXP4XX_EXP_BUS_CS0_BASE_PHYS
-#define IXDP425_FLASH_SIZE      IXP4XX_EXP_BUS_CSX_REGION_SIZE
 #define IXDP425_SDA_PIN         7
 #define IXDP425_SCL_PIN         6
diff --git a/include/asm-arm/arch-ixp4xx/memory.h b/include/asm-arm/arch-ixp4xx/memory.h
index e024d0a1a669..ee211d28a3ef 100644
--- a/include/asm-arm/arch-ixp4xx/memory.h
+++ b/include/asm-arm/arch-ixp4xx/memory.h
@@ -16,31 +16,10 @@
 #ifndef __ASSEMBLY__
-/*
+void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
- * Only first 64MB of memory can be accessed via PCI.
- * We use GFP_DMA to allocate safe buffers to do map/unmap.
- * This is really ugly and we need a better way of specifying
- * DMA-capable regions of memory.
- */
-static inline void __arch_adjust_zones(int node, unsigned long *zone_size, 
-        unsigned long *zhole_size) 
-{
-        unsigned int sz = SZ_64M >> PAGE_SHIFT;
-        /*
-         * Only adjust if > 64M on current system
-         */
-        if (node || (zone_size[0] <= sz))
-                return;
-        zone_size[1] = zone_size[0] - sz;
-        zone_size[0] = sz;
-        zhole_size[1] = zhole_size[0];
-        zhole_size[0] = 0;
-}
 #define arch_adjust_zones(node, size, holes) \
-        __arch_adjust_zones(node, size, holes)
+        ixp4xx_adjust_zones(node, size, holes)
 #define ISA_DMA_THRESHOLD (SZ_64M - 1)
diff --git a/include/asm-arm/arch-ixp4xx/nas100d.h b/include/asm-arm/arch-ixp4xx/nas100d.h
new file mode 100644
index 000000000000..51ac0180427c
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/nas100d.h
@@ -0,0 +1,72 @@
+/*
+ * include/asm-arm/arch-ixp4xx/nas100d.h
+ *
+ * NAS100D platform specific definitions
+ *
+ * Copyright (c) 2005 Tower Technologies
+ *
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * based on ixdp425.h:
+ *      Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+#define NAS100D_SDA_PIN         6
+#define NAS100D_SCL_PIN         5
+/*
+ * NAS100D PCI IRQs
+ */
+#define NAS100D_PCI_MAX_DEV     3
+#define NAS100D_PCI_IRQ_LINES   3
+/* PCI controller GPIO to IRQ pin mappings */
+#define NAS100D_PCI_INTA_PIN    11
+#define NAS100D_PCI_INTB_PIN    10
+#define NAS100D_PCI_INTC_PIN    9
+#define NAS100D_PCI_INTD_PIN    8
+#define NAS100D_PCI_INTE_PIN    7
+/* GPIO */
+#define NAS100D_GPIO0           0
+#define NAS100D_GPIO1           1
+#define NAS100D_GPIO2           2
+#define NAS100D_GPIO3           3
+#define NAS100D_GPIO4           4
+#define NAS100D_GPIO5           5
+#define NAS100D_GPIO6           6
+#define NAS100D_GPIO7           7
+#define NAS100D_GPIO8           8
+#define NAS100D_GPIO9           9
+#define NAS100D_GPIO10          10
+#define NAS100D_GPIO11          11
+#define NAS100D_GPIO12          12
+#define NAS100D_GPIO13          13
+#define NAS100D_GPIO14          14
+#define NAS100D_GPIO15          15
+/* Buttons */
+#define NAS100D_PB_GPIO         NAS100D_GPIO14
+#define NAS100D_RB_GPIO         NAS100D_GPIO4
+#define NAS100D_PO_GPIO         NAS100D_GPIO12   /* power off */
+#define NAS100D_PB_IRQ          IRQ_IXP4XX_GPIO14
+#define NAS100D_RB_IRQ          IRQ_IXP4XX_GPIO4
+/*
+#define NAS100D_PB_BM           (1L << NAS100D_PB_GPIO)
+#define NAS100D_PO_BM           (1L << NAS100D_PO_GPIO)
+#define NAS100D_RB_BM           (1L << NAS100D_RB_GPIO)
+*/
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
index b8b347a559c7..4281838873ef 100644
--- a/include/asm-arm/arch-ixp4xx/nslu2.h
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -18,9 +18,6 @@
 #error "Do not include this directly, instead #include <asm/hardware.h>"
 #endif
-#define NSLU2_FLASH_BASE        IXP4XX_EXP_BUS_CS0_BASE_PHYS
-#define NSLU2_FLASH_SIZE        IXP4XX_EXP_BUS_CSX_REGION_SIZE
 #define NSLU2_SDA_PIN           7
 #define NSLU2_SCL_PIN           6
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index f14ed63590c3..daf9790645ca 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -26,16 +26,17 @@
 */
 #define IXP4XX_EXP_BUS_BASE_PHYS        (0x50000000)
-#define IXP4XX_EXP_BUS_CSX_REGION_SIZE  (0x01000000)
+/*
+ * The expansion bus on the IXP4xx can be configured for either 16 or
+ * 32MB windows and the CS offset for each region changes based on the
+ * current configuration. This means that we cannot simply hardcode
+ * each offset. ixp4xx_sys_init() looks at the expansion bus configuration
+ * as setup by the bootloader to determine our window size.
+ */
+extern unsigned long ixp4xx_exp_bus_size;
-#define IXP4XX_EXP_BUS_CS0_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x00000000)
+#define IXP4XX_EXP_BUS_BASE(region)\
-#define IXP4XX_EXP_BUS_CS1_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x01000000)
+                (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size))
-#define IXP4XX_EXP_BUS_CS2_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x02000000)
-#define IXP4XX_EXP_BUS_CS3_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x03000000)
-#define IXP4XX_EXP_BUS_CS4_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x04000000)
-#define IXP4XX_EXP_BUS_CS5_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x05000000)
-#define IXP4XX_EXP_BUS_CS6_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x06000000)
-#define IXP4XX_EXP_BUS_CS7_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x07000000)
 #define IXP4XX_FLASH_WRITABLE   (0x2)
 #define IXP4XX_FLASH_DEFAULT    (0xbcd23c40)
@@ -112,10 +113,5 @@ static inline void gpio_line_set(u8 line, int value)
            *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
 }
-static inline void gpio_line_isr_clear(u8 line)
-{
-        *IXP4XX_GPIO_GPISR = (1 << line);
-}
 #endif // __ASSEMBLY__
diff --git a/include/asm-arm/arch-l7200/dma.h b/include/asm-arm/arch-l7200/dma.h
index 6595b386cfc9..4c7eca63f035 100644
--- a/include/asm-arm/arch-l7200/dma.h
+++ b/include/asm-arm/arch-l7200/dma.h
@@ -17,7 +17,6 @@
 * bytes of RAM.
 */
 #define MAX_DMA_ADDRESS         0xd0000000
-#define MAX_DMA_CHANNELS        0
 #define DMA_S0                  0
diff --git a/include/asm-arm/arch-l7200/system.h b/include/asm-arm/arch-l7200/system.h
index cb4ff29059b8..18825cf071ba 100644
--- a/include/asm-arm/arch-l7200/system.h
+++ b/include/asm-arm/arch-l7200/system.h
@@ -12,6 +12,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
+#include <asm/hardware.h>
 static inline void arch_idle(void)
 {
        *(unsigned long *)(IO_BASE + 0x50004) = 1;      /* idle mode */
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h
index 5797f01e1844..15492e3253f6 100644
--- a/include/asm-arm/arch-lh7a40x/dma.h
+++ b/include/asm-arm/arch-lh7a40x/dma.h
@@ -7,11 +7,3 @@
 *  version 2 as published by the Free Software Foundation.
 *
 */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-#define MAX_DMA_CHANNELS        0 /* All DMA is internal to CPU */
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S
index 865f396aa63c..a2f67c06d9c9 100644
--- a/include/asm-arm/arch-lh7a40x/entry-macro.S
+++ b/include/asm-arm/arch-lh7a40x/entry-macro.S
@@ -7,6 +7,8 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware.h>
+#include <asm/arch/irqs.h>
 # if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
 #  error "LH7A400 and LH7A404 are mutually exclusive"
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index 740c297eb11c..46a0402696de 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -38,8 +38,6 @@ struct clk {
 struct clk_functions {
        int             (*clk_enable)(struct clk *clk);
        void            (*clk_disable)(struct clk *clk);
-        int             (*clk_use)(struct clk *clk);
-        void            (*clk_unuse)(struct clk *clk);
        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index ccbcb580a5c1..d4e73efcb816 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -21,9 +21,6 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS                 0xffffffff
-#define MAX_DMA_CHANNELS                0
 /* Hardware registers for omap1 */
 #define OMAP_DMA_BASE                   (0xfffed800)
 #define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
index f8814a84910e..0ffb1185f1ac 100644
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -7,6 +7,8 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware.h>
+#include <asm/arch/irqs.h>
 #if defined(CONFIG_ARCH_OMAP1)
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
index 9af415d2944a..6724a81bd10b 100644
--- a/include/asm-arm/arch-omap/system.h
+++ b/include/asm-arm/arch-omap/system.h
@@ -5,8 +5,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 #include <linux/config.h>
+#include <linux/clk.h>
 #include <asm/mach-types.h>
-#include <asm/hardware/clock.h>
 #include <asm/hardware.h>
 #include <asm/arch/prcm.h>
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
index 56db3d49bfc8..3e88a2a02a0f 100644
--- a/include/asm-arm/arch-pxa/dma.h
+++ b/include/asm-arm/arch-pxa/dma.h
@@ -12,11 +12,6 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-/* No DMA as the rest of the world see it */
-#define MAX_DMA_CHANNELS        0
 /*
 * Descriptor structure for PXA's DMA engine
 * Note: this structure must always be aligned to a 16-byte boundary.
diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S
index 2abfc8bb3ee5..4985e33afc12 100644
--- a/include/asm-arm/arch-pxa/entry-macro.S
+++ b/include/asm-arm/arch-pxa/entry-macro.S
@@ -7,6 +7,8 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware.h>
+#include <asm/arch/irqs.h>
                .macro  disable_fiq
                .endm
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index a75a2470f4f5..1409c5bd703f 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -108,6 +108,7 @@
 #define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
 #define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
+#define DALGN           __REG(0x400000a0)  /* DMA Alignment Register */
 #define DINT            __REG(0x400000f0)  /* DMA Interrupt Register */
 #define DRCMR(n)        __REG2(0x40000100, (n)<<2)
@@ -1614,8 +1615,21 @@
 #define SSCR0_National  (0x2 << 4)      /* National Microwire */
 #define SSCR0_ECS       (1 << 6)        /* External clock select */
 #define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
+#if defined(CONFIG_PXA25x)
 #define SSCR0_SCR       (0x0000ff00)    /* Serial Clock Rate (mask) */
 #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
+#elif defined(CONFIG_PXA27x)
+#define SSCR0_SCR       (0x000fff00)    /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
+#define SSCR0_EDSS      (1 << 20)       /* Extended data size select */
+#define SSCR0_NCS       (1 << 21)       /* Network clock select */
+#define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
+#define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
+#define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
+#define SSCR0_SlotsPerFrm(c) ((x) - 1)  /* Time slots per frame [1..8] */
+#define SSCR0_ADC       (1 << 30)       /* Audio clock select */
+#define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
+#endif
 #define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
 #define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
@@ -2042,6 +2056,18 @@
 #ifdef CONFIG_PXA27x
+#define ARB_CNTRL       __REG(0x48000048)  /* Arbiter Control Register */
+#define ARB_DMA_SLV_PARK        (1<<31)    /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK             (1<<30)    /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK         (1<<29)    /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK        (1<<28)    /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK            (1<<27)    /* Be parked with USB when idle */
+#define ARB_LCD_PARK            (1<<26)    /* Be parked with LCD when idle */
+#define ARB_DMA_PARK            (1<<25)    /* Be parked with DMA when idle */
+#define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
+#define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
 /*
 * Keypad
 */
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S
index ed28bd012236..017ad996848d 100644
--- a/include/asm-arm/arch-realview/debug-macro.S
+++ b/include/asm-arm/arch-realview/debug-macro.S
@@ -11,7 +11,7 @@
 *
 */
-#include <asm/hardware/amba_serial.h>
+#include <linux/amba/serial.h>
                .macro  addruart,rx
                mrc     p15, 0, \rx, c1, c0
diff --git a/include/asm-arm/arch-realview/dma.h b/include/asm-arm/arch-realview/dma.h
index 744491a74bd9..8342e3f9d6ec 100644
--- a/include/asm-arm/arch-realview/dma.h
+++ b/include/asm-arm/arch-realview/dma.h
@@ -18,10 +18,3 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-#define MAX_DMA_CHANNELS        0
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 6288fad0dc41..1a6eec86bd47 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -7,7 +7,7 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/hardware.h>
 #include <asm/hardware/gic.h>
                .macro  disable_fiq
diff --git a/include/asm-arm/arch-rpc/entry-macro.S b/include/asm-arm/arch-rpc/entry-macro.S
index 686f413f82d6..c9e5395e5106 100644
--- a/include/asm-arm/arch-rpc/entry-macro.S
+++ b/include/asm-arm/arch-rpc/entry-macro.S
@@ -1,3 +1,3 @@
+#include <asm/hardware.h>
 #include <asm/hardware/entry-macro-iomd.S>
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index e830a40e573a..b011e14f3bc6 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -31,14 +31,6 @@
 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
-/* according to the samsung port, we cannot use the regular
- * dma channels... we must therefore provide our own interface
- * for DMA, and allow our drivers to use that.
- */
-#define MAX_DMA_CHANNELS        0
 /* we have 4 dma channels */
 #define S3C2410_DMA_CHANNELS        (4)
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S
index b7d4d7f4422d..cc06b1bd37b2 100644
--- a/include/asm-arm/arch-s3c2410/entry-macro.S
+++ b/include/asm-arm/arch-s3c2410/entry-macro.S
@@ -10,6 +10,8 @@
 * Modifications:
 *     10-Mar-2005 LCVR  Changed S3C2410_VA to S3C24XX_VA
 */
+#include <asm/hardware.h>
+#include <asm/arch/irqs.h>
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
diff --git a/include/asm-arm/arch-sa1100/dma.h b/include/asm-arm/arch-sa1100/dma.h
index 3d60ed9f8c34..02575d72ac6b 100644
--- a/include/asm-arm/arch-sa1100/dma.h
+++ b/include/asm-arm/arch-sa1100/dma.h
@@ -15,20 +15,6 @@
 /*
- * This is the maximum DMA address that can be DMAd to.
- */
-#define MAX_DMA_ADDRESS         0xffffffff
-/*
- * The regular generic DMA interface is inappropriate for the
- * SA1100 DMA model.  None of the SA1100 specific drivers using
- * DMA are portable anyway so it's pointless to try to twist the
- * regular DMA API to accommodate them.
- */
-#define MAX_DMA_CHANNELS        0
-/*
 * The SA1100 has six internal DMA channels.
 */
 #define SA1100_DMA_CHANNELS     6
diff --git a/include/asm-arm/arch-versatile/debug-macro.S b/include/asm-arm/arch-versatile/debug-macro.S
index 89e38ac1444e..ef6167116dbb 100644
--- a/include/asm-arm/arch-versatile/debug-macro.S
+++ b/include/asm-arm/arch-versatile/debug-macro.S
@@ -11,7 +11,7 @@
 *
 */
-#include <asm/hardware/amba_serial.h>
+#include <linux/amba/serial.h>
                .macro  addruart,rx
                mrc     p15, 0, \rx, c1, c0
diff --git a/include/asm-arm/arch-versatile/dma.h b/include/asm-arm/arch-versatile/dma.h
index dcc8ac26eac0..642577348623 100644
--- a/include/asm-arm/arch-versatile/dma.h
+++ b/include/asm-arm/arch-versatile/dma.h
@@ -18,10 +18,3 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#define MAX_DMA_ADDRESS         0xffffffff
-#define MAX_DMA_CHANNELS        0
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S
index 90e4e970d253..feff771c0a0a 100644
--- a/include/asm-arm/arch-versatile/entry-macro.S
+++ b/include/asm-arm/arch-versatile/entry-macro.S
@@ -7,7 +7,10 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-                        .macro  disable_fiq
+#include <asm/hardware.h>
+#include <asm/hardware/vic.h>
+                .macro  disable_fiq
                .endm
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
diff --git a/include/asm-arm/arch-versatile/platform.h b/include/asm-arm/arch-versatile/platform.h
index cbdd9fb96332..72ef874567d5 100644
--- a/include/asm-arm/arch-versatile/platform.h
+++ b/include/asm-arm/arch-versatile/platform.h
@@ -293,26 +293,7 @@
 *      VERSATILE_SYS_IC 
 * 
 */
-#define VIC_IRQ_STATUS                  0
+/* VIC definitions in include/asm-arm/hardware/vic.h */
-#define VIC_FIQ_STATUS                  0x04
-#define VIC_IRQ_RAW_STATUS              0x08
-#define VIC_INT_SELECT                  0x0C    /* 1 = FIQ, 0 = IRQ */
-#define VIC_IRQ_ENABLE                  0x10    /* 1 = enable, 0 = disable */
-#define VIC_IRQ_ENABLE_CLEAR            0x14
-#define VIC_IRQ_SOFT                    0x18
-#define VIC_IRQ_SOFT_CLEAR              0x1C
-#define VIC_PROTECT                     0x20
-#define VIC_VECT_ADDR                   0x30
-#define VIC_DEF_VECT_ADDR               0x34
-#define VIC_VECT_ADDR0                  0x100   /* 0 to 15 */
-#define VIC_VECT_CNTL0                  0x200   /* 0 to 15 */
-#define VIC_ITCR                        0x300   /* VIC test control register */
-#define VIC_FIQ_RAW_STATUS              0x08
-#define VIC_FIQ_ENABLE                  0x10    /* 1 = enable, 0 = disable */
-#define VIC_FIQ_ENABLE_CLEAR            0x14
-#define VIC_FIQ_SOFT                    0x18
-#define VIC_FIQ_SOFT_CLEAR              0x1C
 #define SIC_IRQ_STATUS                  0
 #define SIC_IRQ_RAW_STATUS              0x04
@@ -325,8 +306,6 @@
 #define SIC_INT_PIC_ENABLES             0x20    /* set interrupt pass through bits */
 #define SIC_INT_PIC_ENABLEC             0x24    /* Clear interrupt pass through bits */
-#define VICVectCntl_Enable              (1 << 5)
 /* ------------------------------------------------------------------------
 *  Interrupts - bit assignment (primary)
 * ------------------------------------------------------------------------
diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
index f72b63309bc5..3d7283d84405 100644
--- a/include/asm-arm/atomic.h
+++ b/include/asm-arm/atomic.h
@@ -175,6 +175,8 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 #endif /* __LINUX_ARM_ARCH__ */
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 static inline int atomic_add_unless(atomic_t *v, int a, int u)
 {
        int c, old;
diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h
index d648a1915c33..17eaf8bdf092 100644
--- a/include/asm-arm/byteorder.h
+++ b/include/asm-arm/byteorder.h
@@ -15,9 +15,32 @@
 #ifndef __ASM_ARM_BYTEORDER_H
 #define __ASM_ARM_BYTEORDER_H
+#include <linux/compiler.h>
 #include <asm/types.h>
+static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+        __u32 t;
+        if (__builtin_constant_p(x)) {
+                t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
+        } else {
+                /*
+                 * The compiler needs a bit of a hint here to always do the
+                 * right thing and not screw it up to different degrees
+                 * depending on the gcc version.
+                 */
+                asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x));
+        }
+        x = (x << 24) | (x >> 8);               /* mov r0,r0,ror #8      */
+        t &= ~0x00FF0000;                       /* bic r1,r1,#0x00FF0000 */
+        x ^= (t >> 8);                          /* eor r0,r0,r1,lsr #8   */
+        return x;
+}
+#define __arch__swab32(x) ___arch__swab32(x)
 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
 #  define __BYTEORDER_HAS_U64__
 #  define __SWAB_64_THRU_32__
diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h
index 8d161f7c87ff..31332c8ac04e 100644
--- a/include/asm-arm/cache.h
+++ b/include/asm-arm/cache.h
@@ -7,9 +7,4 @@
 #define L1_CACHE_SHIFT          5
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX      5
 #endif
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index e81baff4f54b..09e19a783a51 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -14,7 +14,6 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
-#include <asm/mman.h>
 #include <asm/glue.h>
 #include <asm/shmparam.h>
diff --git a/include/asm-arm/dma.h b/include/asm-arm/dma.h
index ef41df43a584..49c01e2bf7c8 100644
--- a/include/asm-arm/dma.h
+++ b/include/asm-arm/dma.h
@@ -10,6 +10,13 @@ typedef unsigned int dmach_t;
 #include <asm/arch/dma.h>
 /*
+ * This is the maximum virtual address which can be DMA'd from.
+ */
+#ifndef MAX_DMA_ADDRESS
+#define MAX_DMA_ADDRESS 0xffffffff
+#endif
+/*
 * DMA modes
 */
 typedef unsigned int dmamode_t;
@@ -91,7 +98,9 @@ extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg);
 * especially since some DMA architectures don't update the
 * DMA address immediately, but defer it to the enable_dma().
 */
-extern void set_dma_addr(dmach_t channel, unsigned long physaddr);
+extern void __set_dma_addr(dmach_t channel, void *addr);
+#define set_dma_addr(channel, addr)                             \
+        __set_dma_addr(channel, bus_to_virt(addr))
 /* Set the DMA byte count for this channel
 *
diff --git a/include/asm-arm/futex.h b/include/asm-arm/futex.h
index 9feff4ce1424..6a332a9f099c 100644
--- a/include/asm-arm/futex.h
+++ b/include/asm-arm/futex.h
@@ -1,53 +1,6 @@
 #ifndef _ASM_FUTEX_H
 #define _ASM_FUTEX_H
-#ifdef __KERNEL__
+#include <asm-generic/futex.h>
-#include <linux/futex.h>
-#include <asm/errno.h>
-#include <asm/uaccess.h>
-static inline int
-futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
-{
-        int op = (encoded_op >> 28) & 7;
-        int cmp = (encoded_op >> 24) & 15;
-        int oparg = (encoded_op << 8) >> 20;
-        int cmparg = (encoded_op << 20) >> 20;
-        int oldval = 0, ret;
-        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
-                oparg = 1 << oparg;
-        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
-                return -EFAULT;
-        inc_preempt_count();
-        switch (op) {
-        case FUTEX_OP_SET:
-        case FUTEX_OP_ADD:
-        case FUTEX_OP_OR:
-        case FUTEX_OP_ANDN:
-        case FUTEX_OP_XOR:
-        default:
-                ret = -ENOSYS;
-        }
-        dec_preempt_count();
-        if (!ret) {
-                switch (cmp) {
-                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
-                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
-                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
-                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
-                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
-                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
-                default: ret = -ENOSYS;
-                }
-        }
-        return ret;
-}
-#endif
 #endif
diff --git a/include/asm-arm/hardware/amba.h b/include/asm-arm/hardware/amba.h
deleted file mode 100644
index 51e6e54b2aa1..000000000000
--- a/include/asm-arm/hardware/amba.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- *  linux/include/asm-arm/hardware/amba.h
- *
- *  Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_AMBA_H
-#define ASMARM_AMBA_H
-#define AMBA_NR_IRQS    2
-struct amba_device {
-        struct device           dev;
-        struct resource         res;
-        u64                     dma_mask;
-        unsigned int            periphid;
-        unsigned int            irq[AMBA_NR_IRQS];
-};
-struct amba_id {
-        unsigned int            id;
-        unsigned int            mask;
-        void                    *data;
-};
-struct amba_driver {
-        struct device_driver    drv;
-        int                     (*probe)(struct amba_device *, void *);
-        int                     (*remove)(struct amba_device *);
-        void                    (*shutdown)(struct amba_device *);
-        int                     (*suspend)(struct amba_device *, pm_message_t);
-        int                     (*resume)(struct amba_device *);
-        struct amba_id          *id_table;
-};
-#define amba_get_drvdata(d)     dev_get_drvdata(&d->dev)
-#define amba_set_drvdata(d,p)   dev_set_drvdata(&d->dev, p)
-int amba_driver_register(struct amba_driver *);
-void amba_driver_unregister(struct amba_driver *);
-int amba_device_register(struct amba_device *, struct resource *);
-void amba_device_unregister(struct amba_device *);
-struct amba_device *amba_find_device(const char *, struct device *, unsigned int, unsigned int);
-int amba_request_regions(struct amba_device *, const char *);
-void amba_release_regions(struct amba_device *);
-#define amba_config(d)  (((d)->periphid >> 24) & 0xff)
-#define amba_rev(d)     (((d)->periphid >> 20) & 0x0f)
-#define amba_manf(d)    (((d)->periphid >> 12) & 0xff)
-#define amba_part(d)    ((d)->periphid & 0xfff)
-#endif
diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h
deleted file mode 100644
index 6b8d73dc1ab0..000000000000
--- a/include/asm-arm/hardware/amba_clcd.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
- *
- * David A Rusling
- *
- * Copyright (C) 2001 ARM Limited
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-#include <linux/config.h>
-#include <linux/fb.h>
-/*
- * CLCD Controller Internal Register addresses
- */
-#define CLCD_TIM0               0x00000000
-#define CLCD_TIM1               0x00000004
-#define CLCD_TIM2               0x00000008
-#define CLCD_TIM3               0x0000000c
-#define CLCD_UBAS               0x00000010
-#define CLCD_LBAS               0x00000014
-#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
-#define CLCD_IENB               0x00000018
-#define CLCD_CNTL               0x0000001c
-#else
-/*
- * Someone rearranged these two registers on the Versatile
- * platform...
- */
-#define CLCD_IENB               0x0000001c
-#define CLCD_CNTL               0x00000018
-#endif
-#define CLCD_STAT               0x00000020
-#define CLCD_INTR               0x00000024
-#define CLCD_UCUR               0x00000028
-#define CLCD_LCUR               0x0000002C
-#define CLCD_PALL               0x00000200
-#define CLCD_PALETTE            0x00000200
-#define TIM2_CLKSEL             (1 << 5)
-#define TIM2_IVS                (1 << 11)
-#define TIM2_IHS                (1 << 12)
-#define TIM2_IPC                (1 << 13)
-#define TIM2_IOE                (1 << 14)
-#define TIM2_BCD                (1 << 26)
-#define CNTL_LCDEN              (1 << 0)
-#define CNTL_LCDBPP1            (0 << 1)
-#define CNTL_LCDBPP2            (1 << 1)
-#define CNTL_LCDBPP4            (2 << 1)
-#define CNTL_LCDBPP8            (3 << 1)
-#define CNTL_LCDBPP16           (4 << 1)
-#define CNTL_LCDBPP24           (5 << 1)
-#define CNTL_LCDBW              (1 << 4)
-#define CNTL_LCDTFT             (1 << 5)
-#define CNTL_LCDMONO8           (1 << 6)
-#define CNTL_LCDDUAL            (1 << 7)
-#define CNTL_BGR                (1 << 8)
-#define CNTL_BEBO               (1 << 9)
-#define CNTL_BEPO               (1 << 10)
-#define CNTL_LCDPWR             (1 << 11)
-#define CNTL_LCDVCOMP(x)        ((x) << 12)
-#define CNTL_LDMAFIFOTIME       (1 << 15)
-#define CNTL_WATERMARK          (1 << 16)
-struct clcd_panel {
-        struct fb_videomode     mode;
-        signed short            width;  /* width in mm */
-        signed short            height; /* height in mm */
-        u32                     tim2;
-        u32                     tim3;
-        u32                     cntl;
-        unsigned int            bpp:8,
-                                fixedtimings:1,
-                                grayscale:1;
-        unsigned int            connector;
-};
-struct clcd_regs {
-        u32                     tim0;
-        u32                     tim1;
-        u32                     tim2;
-        u32                     tim3;
-        u32                     cntl;
-        unsigned long           pixclock;
-};
-struct clcd_fb;
-/*
- * the board-type specific routines
- */
-struct clcd_board {
-        const char *name;
-        /*
-         * Optional.  Check whether the var structure is acceptable
-         * for this display.
-         */
-        int     (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
-        /*
-         * Compulsary.  Decode fb->fb.var into regs->*.  In the case of
-         * fixed timing, set regs->* to the register values required.
-         */
-        void    (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
-        /*
-         * Optional.  Disable any extra display hardware.
-         */
-        void    (*disable)(struct clcd_fb *);
-        /*
-         * Optional.  Enable any extra display hardware.
-         */
-        void    (*enable)(struct clcd_fb *);
-        /*
-         * Setup platform specific parts of CLCD driver
-         */
-        int     (*setup)(struct clcd_fb *);
-        /*
-         * mmap the framebuffer memory
-         */
-        int     (*mmap)(struct clcd_fb *, struct vm_area_struct *);
-        /*
-         * Remove platform specific parts of CLCD driver
-         */
-        void    (*remove)(struct clcd_fb *);
-};
-struct amba_device;
-struct clk;
-/* this data structure describes each frame buffer device we find */
-struct clcd_fb {
-        struct fb_info          fb;
-        struct amba_device      *dev;
-        struct clk              *clk;
-        struct clcd_panel       *panel;
-        struct clcd_board       *board;
-        void                    *board_data;
-        void __iomem            *regs;
-        u32                     clcd_cntl;
-        u32                     cmap[16];
-};
-static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
-{
-        u32 val, cpl;
-        /*
-         * Program the CLCD controller registers and start the CLCD
-         */
-        val = ((fb->fb.var.xres / 16) - 1) << 2;
-        val |= (fb->fb.var.hsync_len - 1) << 8;
-        val |= (fb->fb.var.right_margin - 1) << 16;
-        val |= (fb->fb.var.left_margin - 1) << 24;
-        regs->tim0 = val;
-        val = fb->fb.var.yres;
-        if (fb->panel->cntl & CNTL_LCDDUAL)
-                val /= 2;
-        val -= 1;
-        val |= (fb->fb.var.vsync_len - 1) << 10;
-        val |= fb->fb.var.lower_margin << 16;
-        val |= fb->fb.var.upper_margin << 24;
-        regs->tim1 = val;
-        val = fb->panel->tim2;
-        val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT  ? 0 : TIM2_IHS;
-        val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
-        cpl = fb->fb.var.xres_virtual;
-        if (fb->panel->cntl & CNTL_LCDTFT)        /* TFT */
-                /* / 1 */;
-        else if (!fb->fb.var.grayscale)           /* STN color */
-                cpl = cpl * 8 / 3;
-        else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
-                cpl /= 8;
-        else                                      /* STN monochrome, 4bit */
-                cpl /= 4;
-        regs->tim2 = val | ((cpl - 1) << 16);
-        regs->tim3 = fb->panel->tim3;
-        val = fb->panel->cntl;
-        if (fb->fb.var.grayscale)
-                val |= CNTL_LCDBW;
-        switch (fb->fb.var.bits_per_pixel) {
-        case 1:
-                val |= CNTL_LCDBPP1;
-                break;
-        case 2:
-                val |= CNTL_LCDBPP2;
-                break;
-        case 4:
-                val |= CNTL_LCDBPP4;
-                break;
-        case 8:
-                val |= CNTL_LCDBPP8;
-                break;
-        case 16:
-                val |= CNTL_LCDBPP16;
-                break;
-        case 32:
-                val |= CNTL_LCDBPP24;
-                break;
-        }
-        regs->cntl = val;
-        regs->pixclock = fb->fb.var.pixclock;
-}
-static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
-{
-        var->xres_virtual = var->xres = (var->xres + 15) & ~15;
-        var->yres_virtual = var->yres = (var->yres + 1) & ~1;
-#define CHECK(e,l,h) (var->e < l || var->e > h)
-        if (CHECK(right_margin, (5+1), 256) ||  /* back porch */
-            CHECK(left_margin, (5+1), 256) ||   /* front porch */
-            CHECK(hsync_len, (5+1), 256) ||
-            var->xres > 4096 ||
-            var->lower_margin > 255 ||          /* back porch */
-            var->upper_margin > 255 ||          /* front porch */
-            var->vsync_len > 32 ||
-            var->yres > 1024)
-                return -EINVAL;
-#undef CHECK
-        /* single panel mode: PCD = max(PCD, 1) */
-        /* dual panel mode: PCD = max(PCD, 5) */
-        /*
-         * You can't change the grayscale setting, and
-         * we can only do non-interlaced video.
-         */
-        if (var->grayscale != fb->fb.var.grayscale ||
-            (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
-                return -EINVAL;
-#define CHECK(e) (var->e != fb->fb.var.e)
-        if (fb->panel->fixedtimings &&
-            (CHECK(xres)                ||
-             CHECK(yres)                ||
-             CHECK(bits_per_pixel)      ||
-             CHECK(pixclock)            ||
-             CHECK(left_margin)         ||
-             CHECK(right_margin)        ||
-             CHECK(upper_margin)        ||
-             CHECK(lower_margin)        ||
-             CHECK(hsync_len)           ||
-             CHECK(vsync_len)           ||
-             CHECK(sync)))
-                return -EINVAL;
-#undef CHECK
-        var->nonstd = 0;
-        var->accel_flags = 0;
-        return 0;
-}
diff --git a/include/asm-arm/hardware/amba_kmi.h b/include/asm-arm/hardware/amba_kmi.h
deleted file mode 100644
index a39e5be751b3..000000000000
--- a/include/asm-arm/hardware/amba_kmi.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *  linux/include/asm-arm/hardware/amba_kmi.h
- *
- *  Internal header file for AMBA KMI ports
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- *
- * ---------------------------------------------------------------------------
- *  From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
- *  Reference Manual - ARM DDI 0143B - see http://www.arm.com/
- * ---------------------------------------------------------------------------
- */
-#ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
-#define ASM_ARM_HARDWARE_AMBA_KMI_H
-/*
- * KMI control register:
- *  KMICR_TYPE       0 = PS2/AT mode, 1 = No line control bit mode
- *  KMICR_RXINTREN   1 = enable RX interrupts
- *  KMICR_TXINTREN   1 = enable TX interrupts
- *  KMICR_EN         1 = enable KMI
- *  KMICR_FD         1 = force KMI data low
- *  KMICR_FC         1 = force KMI clock low
- */
-#define KMICR           (KMI_BASE + 0x00)
-#define KMICR_TYPE              (1 << 5)
-#define KMICR_RXINTREN          (1 << 4)
-#define KMICR_TXINTREN          (1 << 3)
-#define KMICR_EN                (1 << 2)
-#define KMICR_FD                (1 << 1)
-#define KMICR_FC                (1 << 0)
-/*
- * KMI status register:
- *  KMISTAT_TXEMPTY  1 = transmitter register empty
- *  KMISTAT_TXBUSY   1 = currently sending data
- *  KMISTAT_RXFULL   1 = receiver register ready to be read
- *  KMISTAT_RXBUSY   1 = currently receiving data
- *  KMISTAT_RXPARITY parity of last databyte received
- *  KMISTAT_IC       current level of KMI clock input
- *  KMISTAT_ID       current level of KMI data input
- */
-#define KMISTAT         (KMI_BASE + 0x04)
-#define KMISTAT_TXEMPTY         (1 << 6)
-#define KMISTAT_TXBUSY          (1 << 5)
-#define KMISTAT_RXFULL          (1 << 4)
-#define KMISTAT_RXBUSY          (1 << 3)
-#define KMISTAT_RXPARITY        (1 << 2)
-#define KMISTAT_IC              (1 << 1)
-#define KMISTAT_ID              (1 << 0)
-/*
- * KMI data register
- */
-#define KMIDATA         (KMI_BASE + 0x08)
-/*
- * KMI clock divisor: to generate 8MHz internal clock
- *  div = (ref / 8MHz) - 1; 0 <= div <= 15
- */
-#define KMICLKDIV       (KMI_BASE + 0x0c)
-/*
- * KMI interrupt register:
- *  KMIIR_TXINTR     1 = transmit interrupt asserted
- *  KMIIR_RXINTR     1 = receive interrupt asserted
- */
-#define KMIIR           (KMI_BASE + 0x10)
-#define KMIIR_TXINTR            (1 << 1)
-#define KMIIR_RXINTR            (1 << 0)
-/*
- * The size of the KMI primecell
- */
-#define KMI_SIZE        (0x100)
-#endif
diff --git a/include/asm-arm/hardware/amba_serial.h b/include/asm-arm/hardware/amba_serial.h
deleted file mode 100644
index dc726ffccebd..000000000000
--- a/include/asm-arm/hardware/amba_serial.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- *  linux/include/asm-arm/hardware/serial_amba.h
- *
- *  Internal header file for AMBA serial ports
- *
- *  Copyright (C) ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
-#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
-/* -------------------------------------------------------------------------------
- *  From AMBA UART (PL010) Block Specification
- * -------------------------------------------------------------------------------
- *  UART Register Offsets.
- */
-#define UART01x_DR              0x00    /* Data read or written from the interface. */
-#define UART01x_RSR             0x04    /* Receive status register (Read). */
-#define UART01x_ECR             0x04    /* Error clear register (Write). */
-#define UART010_LCRH            0x08    /* Line control register, high byte. */
-#define UART010_LCRM            0x0C    /* Line control register, middle byte. */
-#define UART010_LCRL            0x10    /* Line control register, low byte. */
-#define UART010_CR              0x14    /* Control register. */
-#define UART01x_FR              0x18    /* Flag register (Read only). */
-#define UART010_IIR             0x1C    /* Interrupt indentification register (Read). */
-#define UART010_ICR             0x1C    /* Interrupt clear register (Write). */
-#define UART01x_ILPR            0x20    /* IrDA low power counter register. */
-#define UART011_IBRD            0x24    /* Integer baud rate divisor register. */
-#define UART011_FBRD            0x28    /* Fractional baud rate divisor register. */
-#define UART011_LCRH            0x2c    /* Line control register. */
-#define UART011_CR              0x30    /* Control register. */
-#define UART011_IFLS            0x34    /* Interrupt fifo level select. */
-#define UART011_IMSC            0x38    /* Interrupt mask. */
-#define UART011_RIS             0x3c    /* Raw interrupt status. */
-#define UART011_MIS             0x40    /* Masked interrupt status. */
-#define UART011_ICR             0x44    /* Interrupt clear register. */
-#define UART011_DMACR           0x48    /* DMA control register. */
-#define UART011_DR_OE           (1 << 11)
-#define UART011_DR_BE           (1 << 10)
-#define UART011_DR_PE           (1 << 9)
-#define UART011_DR_FE           (1 << 8)
-#define UART01x_RSR_OE          0x08
-#define UART01x_RSR_BE          0x04
-#define UART01x_RSR_PE          0x02
-#define UART01x_RSR_FE          0x01
-#define UART011_FR_RI           0x100
-#define UART011_FR_TXFE         0x080
-#define UART011_FR_RXFF         0x040
-#define UART01x_FR_TXFF         0x020
-#define UART01x_FR_RXFE         0x010
-#define UART01x_FR_BUSY         0x008
-#define UART01x_FR_DCD          0x004
-#define UART01x_FR_DSR          0x002
-#define UART01x_FR_CTS          0x001
-#define UART01x_FR_TMSK         (UART01x_FR_TXFF + UART01x_FR_BUSY)
-#define UART011_CR_CTSEN        0x8000  /* CTS hardware flow control */
-#define UART011_CR_RTSEN        0x4000  /* RTS hardware flow control */
-#define UART011_CR_OUT2         0x2000  /* OUT2 */
-#define UART011_CR_OUT1         0x1000  /* OUT1 */
-#define UART011_CR_RTS          0x0800  /* RTS */
-#define UART011_CR_DTR          0x0400  /* DTR */
-#define UART011_CR_RXE          0x0200  /* receive enable */
-#define UART011_CR_TXE          0x0100  /* transmit enable */
-#define UART011_CR_LBE          0x0080  /* loopback enable */
-#define UART010_CR_RTIE         0x0040
-#define UART010_CR_TIE          0x0020
-#define UART010_CR_RIE          0x0010
-#define UART010_CR_MSIE         0x0008
-#define UART01x_CR_IIRLP        0x0004  /* SIR low power mode */
-#define UART01x_CR_SIREN        0x0002  /* SIR enable */
-#define UART01x_CR_UARTEN       0x0001  /* UART enable */
- 
-#define UART011_LCRH_SPS        0x80
-#define UART01x_LCRH_WLEN_8     0x60
-#define UART01x_LCRH_WLEN_7     0x40
-#define UART01x_LCRH_WLEN_6     0x20
-#define UART01x_LCRH_WLEN_5     0x00
-#define UART01x_LCRH_FEN        0x10
-#define UART01x_LCRH_STP2       0x08
-#define UART01x_LCRH_EPS        0x04
-#define UART01x_LCRH_PEN        0x02
-#define UART01x_LCRH_BRK        0x01
-#define UART010_IIR_RTIS        0x08
-#define UART010_IIR_TIS         0x04
-#define UART010_IIR_RIS         0x02
-#define UART010_IIR_MIS         0x01
-#define UART011_IFLS_RX1_8      (0 << 3)
-#define UART011_IFLS_RX2_8      (1 << 3)
-#define UART011_IFLS_RX4_8      (2 << 3)
-#define UART011_IFLS_RX6_8      (3 << 3)
-#define UART011_IFLS_RX7_8      (4 << 3)
-#define UART011_IFLS_TX1_8      (0 << 0)
-#define UART011_IFLS_TX2_8      (1 << 0)
-#define UART011_IFLS_TX4_8      (2 << 0)
-#define UART011_IFLS_TX6_8      (3 << 0)
-#define UART011_IFLS_TX7_8      (4 << 0)
-#define UART011_OEIM            (1 << 10)       /* overrun error interrupt mask */
-#define UART011_BEIM            (1 << 9)        /* break error interrupt mask */
-#define UART011_PEIM            (1 << 8)        /* parity error interrupt mask */
-#define UART011_FEIM            (1 << 7)        /* framing error interrupt mask */
-#define UART011_RTIM            (1 << 6)        /* receive timeout interrupt mask */
-#define UART011_TXIM            (1 << 5)        /* transmit interrupt mask */
-#define UART011_RXIM            (1 << 4)        /* receive interrupt mask */
-#define UART011_DSRMIM          (1 << 3)        /* DSR interrupt mask */
-#define UART011_DCDMIM          (1 << 2)        /* DCD interrupt mask */
-#define UART011_CTSMIM          (1 << 1)        /* CTS interrupt mask */
-#define UART011_RIMIM           (1 << 0)        /* RI interrupt mask */
-#define UART011_OEIS            (1 << 10)       /* overrun error interrupt status */
-#define UART011_BEIS            (1 << 9)        /* break error interrupt status */
-#define UART011_PEIS            (1 << 8)        /* parity error interrupt status */
-#define UART011_FEIS            (1 << 7)        /* framing error interrupt status */
-#define UART011_RTIS            (1 << 6)        /* receive timeout interrupt status */
-#define UART011_TXIS            (1 << 5)        /* transmit interrupt status */
-#define UART011_RXIS            (1 << 4)        /* receive interrupt status */
-#define UART011_DSRMIS          (1 << 3)        /* DSR interrupt status */
-#define UART011_DCDMIS          (1 << 2)        /* DCD interrupt status */
-#define UART011_CTSMIS          (1 << 1)        /* CTS interrupt status */
-#define UART011_RIMIS           (1 << 0)        /* RI interrupt status */
-#define UART011_OEIC            (1 << 10)       /* overrun error interrupt clear */
-#define UART011_BEIC            (1 << 9)        /* break error interrupt clear */
-#define UART011_PEIC            (1 << 8)        /* parity error interrupt clear */
-#define UART011_FEIC            (1 << 7)        /* framing error interrupt clear */
-#define UART011_RTIC            (1 << 6)        /* receive timeout interrupt clear */
-#define UART011_TXIC            (1 << 5)        /* transmit interrupt clear */
-#define UART011_RXIC            (1 << 4)        /* receive interrupt clear */
-#define UART011_DSRMIC          (1 << 3)        /* DSR interrupt clear */
-#define UART011_DCDMIC          (1 << 2)        /* DCD interrupt clear */
-#define UART011_CTSMIC          (1 << 1)        /* CTS interrupt clear */
-#define UART011_RIMIC           (1 << 0)        /* RI interrupt clear */
-#define UART011_DMAONERR        (1 << 2)        /* disable dma on error */
-#define UART011_TXDMAE          (1 << 1)        /* enable transmit dma */
-#define UART011_RXDMAE          (1 << 0)        /* enable receive dma */
-#define UART01x_RSR_ANY         (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
-#define UART01x_FR_MODEM_ANY    (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
-#endif
diff --git a/include/asm-arm/hardware/clock.h b/include/asm-arm/hardware/clock.h
deleted file mode 100644
index 19da861e523d..000000000000
--- a/include/asm-arm/hardware/clock.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- *  linux/include/asm-arm/hardware/clock.h
- *
- *  Copyright (C) 2004 ARM Limited.
- *  Written by Deep Blue Solutions Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_CLOCK_H
-#define ASMARM_CLOCK_H
-struct device;
-/*
- * The base API.
- */
-/*
- * struct clk - an machine class defined object / cookie.
- */
-struct clk;
-/**
- * clk_get - lookup and obtain a reference to a clock producer.
- * @dev: device for clock "consumer"
- * @id: clock comsumer ID
- *
- * Returns a struct clk corresponding to the clock producer, or
- * valid IS_ERR() condition containing errno.  The implementation
- * uses @dev and @id to determine the clock consumer, and thereby
- * the clock producer.  (IOW, @id may be identical strings, but
- * clk_get may return different clock producers depending on @dev.)
- */
-struct clk *clk_get(struct device *dev, const char *id);
-/**
- * clk_enable - inform the system when the clock source should be running.
- * @clk: clock source
- *
- * If the clock can not be enabled/disabled, this should return success.
- *
- * Returns success (0) or negative errno.
- */
-int clk_enable(struct clk *clk);
-/**
- * clk_disable - inform the system when the clock source is no longer required.
- * @clk: clock source
- */
-void clk_disable(struct clk *clk);
-/**
- * clk_use - increment the use count
- * @clk: clock source
- *
- * Returns success (0) or negative errno.
- */
-int clk_use(struct clk *clk);
-/**
- * clk_unuse - decrement the use count
- * @clk: clock source
- */
-void clk_unuse(struct clk *clk);
-/**
- * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
- *                This is only valid once the clock source has been enabled.
- * @clk: clock source
- */
-unsigned long clk_get_rate(struct clk *clk);
-/**
- * clk_put      - "free" the clock source
- * @clk: clock source
- */
-void clk_put(struct clk *clk);
-/*
- * The remaining APIs are optional for machine class support.
- */
-/**
- * clk_round_rate - adjust a rate to the exact rate a clock can provide
- * @clk: clock source
- * @rate: desired clock rate in Hz
- *
- * Returns rounded clock rate in Hz, or negative errno.
- */
-long clk_round_rate(struct clk *clk, unsigned long rate);
- 
-/**
- * clk_set_rate - set the clock rate for a clock source
- * @clk: clock source
- * @rate: desired clock rate in Hz
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_rate(struct clk *clk, unsigned long rate);
- 
-/**
- * clk_set_parent - set the parent clock source for this clock
- * @clk: clock source
- * @parent: parent clock source
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_parent(struct clk *clk, struct clk *parent);
-/**
- * clk_get_parent - get the parent clock source for this clock
- * @clk: clock source
- *
- * Returns struct clk corresponding to parent clock source, or
- * valid IS_ERR() condition containing errno.
- */
-struct clk *clk_get_parent(struct clk *clk);
-#endif
diff --git a/include/asm-arm/hardware/sharpsl_pm.h b/include/asm-arm/hardware/sharpsl_pm.h
new file mode 100644
index 000000000000..36983e5f3665
--- /dev/null
+++ b/include/asm-arm/hardware/sharpsl_pm.h
@@ -0,0 +1,94 @@
+/*
+ * SharpSL Battery/PM Driver
+ *
+ * Copyright (c) 2004-2005 Richard Purdie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/interrupt.h>
+struct sharpsl_charger_machinfo {
+        void (*init)(void);
+        void (*exit)(void);
+        int gpio_acin;
+        int gpio_batfull;
+        int gpio_batlock;
+        int gpio_fatal;
+        void (*discharge)(int);
+        void (*discharge1)(int);
+        void (*charge)(int);
+        void (*measure_temp)(int);
+        void (*presuspend)(void);
+        void (*postsuspend)(void);
+        unsigned long (*read_devdata)(int);
+#define SHARPSL_BATT_VOLT       1
+#define SHARPSL_BATT_TEMP       2
+#define SHARPSL_ACIN_VOLT       3
+#define SHARPSL_STATUS_ACIN     4
+#define SHARPSL_STATUS_LOCK     5
+#define SHARPSL_STATUS_CHRGFULL 6
+#define SHARPSL_STATUS_FATAL    7
+        unsigned long (*charger_wakeup)(void);
+        int (*should_wakeup)(unsigned int resume_on_alarm);
+        int bat_levels;
+        struct battery_thresh *bat_levels_noac;
+        struct battery_thresh *bat_levels_acin;
+        int status_high_acin;
+        int status_low_acin;
+        int status_high_noac;
+        int status_low_noac;
+};
+struct battery_thresh {
+        int voltage;
+        int percentage;
+};
+struct battery_stat {
+        int ac_status;         /* APM AC Present/Not Present */
+        int mainbat_status;    /* APM Main Battery Status */
+        int mainbat_percent;   /* Main Battery Percentage Charge */
+        int mainbat_voltage;   /* Main Battery Voltage */
+};
+struct sharpsl_pm_status {
+        struct device *dev;
+        struct timer_list ac_timer;
+        struct timer_list chrg_full_timer;
+        int charge_mode;
+#define CHRG_ERROR    (-1)
+#define CHRG_OFF      (0)
+#define CHRG_ON       (1)
+#define CHRG_DONE     (2)
+        unsigned int flags;
+#define SHARPSL_SUSPENDED       (1 << 0)  /* Device is Suspended */
+#define SHARPSL_ALARM_ACTIVE    (1 << 1)  /* Alarm is for charging event (not user) */
+#define SHARPSL_BL_LIMIT        (1 << 2)  /* Backlight Intensity Limited */
+#define SHARPSL_APM_QUEUED      (1 << 3)  /* APM Event Queued */
+#define SHARPSL_DO_OFFLINE_CHRG (1 << 4)  /* Trigger the offline charger */
+        int full_count;
+        unsigned long charge_start_time;
+        struct sharpsl_charger_machinfo *machinfo;
+        struct battery_stat battstat;
+};
+extern struct sharpsl_pm_status sharpsl_pm;
+#define SHARPSL_LED_ERROR  2
+#define SHARPSL_LED_ON     1
+#define SHARPSL_LED_OFF    0
+void sharpsl_battery_kick(void);
+void sharpsl_pm_led(int val);
+irqreturn_t sharpsl_ac_isr(int irq, void *dev_id, struct pt_regs *fp);
+irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id, struct pt_regs *fp);
+irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id, struct pt_regs *fp);
diff --git a/include/asm-arm/hardware/vic.h b/include/asm-arm/hardware/vic.h
new file mode 100644
index 000000000000..81825eb54c9e
--- /dev/null
+++ b/include/asm-arm/hardware/vic.h
@@ -0,0 +1,45 @@
+/*
+ *  linux/include/asm-arm/hardware/vic.h
+ *
+ *  Copyright (c) ARM Limited 2003.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_HARDWARE_VIC_H
+#define __ASM_ARM_HARDWARE_VIC_H
+#define VIC_IRQ_STATUS                  0x00
+#define VIC_FIQ_STATUS                  0x04
+#define VIC_RAW_STATUS                  0x08
+#define VIC_INT_SELECT                  0x0c    /* 1 = FIQ, 0 = IRQ */
+#define VIC_INT_ENABLE                  0x10    /* 1 = enable, 0 = disable */
+#define VIC_INT_ENABLE_CLEAR            0x14
+#define VIC_INT_SOFT                    0x18
+#define VIC_INT_SOFT_CLEAR              0x1c
+#define VIC_PROTECT                     0x20
+#define VIC_VECT_ADDR                   0x30
+#define VIC_DEF_VECT_ADDR               0x34
+#define VIC_VECT_ADDR0                  0x100   /* 0 to 15 */
+#define VIC_VECT_CNTL0                  0x200   /* 0 to 15 */
+#define VIC_ITCR                        0x300   /* VIC test control register */
+#define VIC_VECT_CNTL_ENABLE            (1 << 5)
+#ifndef __ASSEMBLY__
+void vic_init(void __iomem *base, u32 vic_sources);
+#endif
+#endif
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 0cf4d4f99600..fd0147e52dbb 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -56,7 +56,12 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 /*
 * Architecture ioremap implementation.
+ *
+ * __ioremap takes CPU physical address.
+ *
+ * __ioremap_pfn takes a Page Frame Number and an offset into that page
 */
+extern void __iomem * __ioremap_pfn(unsigned long, unsigned long, size_t, unsigned long);
 extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
 extern void __iounmap(void __iomem *addr);
@@ -261,6 +266,7 @@ out:
 *
 * ioremap takes a PCI memory address, as specified in
 * Documentation/IO-mapping.txt.
+ *
 */
 #ifndef __arch_ioremap
 #define ioremap(cookie,size)            __ioremap(cookie,size,0)
diff --git a/include/asm-arm/ioctl.h b/include/asm-arm/ioctl.h
index 2cbb7d0e9dc6..b279fe06dfe5 100644
--- a/include/asm-arm/ioctl.h
+++ b/include/asm-arm/ioctl.h
@@ -1,74 +1 @@
-/*
+#include <asm-generic/ioctl.h>
- * linux/ioctl.h for Linux by H.H. Bergman.
- */
-#ifndef _ASMARM_IOCTL_H
-#define _ASMARM_IOCTL_H
-/* ioctl command encoding: 32 bits total, command in lower 16 bits,
- * size of the parameter structure in the lower 14 bits of the
- * upper 16 bits.
- * Encoding the size of the parameter structure in the ioctl request
- * is useful for catching programs compiled with old versions
- * and to avoid overwriting user space outside the user buffer area.
- * The highest 2 bits are reserved for indicating the ``access mode''.
- * NOTE: This limits the max parameter size to 16kB -1 !
- */
-/*
- * The following is for compatibility across the various Linux
- * platforms.  The i386 ioctl numbering scheme doesn't really enforce
- * a type field.  De facto, however, the top 8 bits of the lower 16
- * bits are indeed used as a type field, so we might just as well make
- * this explicit here.  Please be sure to use the decoding macros
- * below from now on.
- */
-#define _IOC_NRBITS     8
-#define _IOC_TYPEBITS   8
-#define _IOC_SIZEBITS   14
-#define _IOC_DIRBITS    2
-#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
-#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
-#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
-#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
-#define _IOC_NRSHIFT    0
-#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
-#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
-#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
-/*
- * Direction bits.
- */
-#define _IOC_NONE       0U
-#define _IOC_WRITE      1U
-#define _IOC_READ       2U
-#define _IOC(dir,type,nr,size) \
-        (((dir)  << _IOC_DIRSHIFT) | \
-         ((type) << _IOC_TYPESHIFT) | \
-         ((nr)   << _IOC_NRSHIFT) | \
-         ((size) << _IOC_SIZESHIFT))
-/* used to create numbers */
-#define _IO(type,nr)            _IOC(_IOC_NONE,(type),(nr),0)
-#define _IOR(type,nr,size)      _IOC(_IOC_READ,(type),(nr),sizeof(size))
-#define _IOW(type,nr,size)      _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
-#define _IOWR(type,nr,size)     _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
-/* used to decode ioctl numbers.. */
-#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
-#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
-#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
-#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
-/* ...and for the drivers/sound files... */
-#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
-#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
-#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
-#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
-#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
-#endif /* _ASMARM_IOCTL_H */
diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h
index 59975ee43cf1..7772432d3fd7 100644
--- a/include/asm-arm/irq.h
+++ b/include/asm-arm/irq.h
@@ -25,10 +25,14 @@ extern void disable_irq_nosync(unsigned int);
 extern void disable_irq(unsigned int);
 extern void enable_irq(unsigned int);
-#define __IRQT_FALEDGE  (1 << 0)
+/*
-#define __IRQT_RISEDGE  (1 << 1)
+ * These correspond with the SA_TRIGGER_* defines, and therefore the
-#define __IRQT_LOWLVL   (1 << 2)
+ * IRQRESOURCE_IRQ_* defines.
-#define __IRQT_HIGHLVL  (1 << 3)
+ */
+#define __IRQT_RISEDGE  (1 << 0)
+#define __IRQT_FALEDGE  (1 << 1)
+#define __IRQT_HIGHLVL  (1 << 2)
+#define __IRQT_LOWLVL   (1 << 3)
 #define IRQT_NOEDGE     (0)
 #define IRQT_RISING     (__IRQT_RISEDGE)
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
index eb262e078c46..2cd57b4d64d9 100644
--- a/include/asm-arm/mach/arch.h
+++ b/include/asm-arm/mach/arch.h
@@ -10,6 +10,8 @@
 #ifndef __ASSEMBLY__
+#include <linux/compiler.h>
 struct tag;
 struct meminfo;
 struct sys_timer;
@@ -20,7 +22,7 @@ struct machine_desc {
         * by assembler code in head-armv.S
         */
        unsigned int            nr;             /* architecture number  */
-        unsigned int            phys_ram;       /* start of physical ram */
+        unsigned int __deprecated phys_ram;     /* start of physical ram */
        unsigned int            phys_io;        /* start of physical io */
        unsigned int            io_pg_offst;    /* byte offset for io 
                                                 * page tabe entry      */
diff --git a/include/asm-arm/mach/dma.h b/include/asm-arm/mach/dma.h
index 31bf716106ee..e7c4a20aad53 100644
--- a/include/asm-arm/mach/dma.h
+++ b/include/asm-arm/mach/dma.h
@@ -25,13 +25,15 @@ struct dma_ops {
 };
 struct dma_struct {
+        void            *addr;          /* single DMA address           */
+        unsigned long   count;          /* single DMA size              */
        struct scatterlist buf;         /* single DMA                   */
        int             sgcount;        /* number of DMA SG             */
        struct scatterlist *sg;         /* DMA Scatter-Gather List      */
        unsigned int    active:1;       /* Transfer active              */
        unsigned int    invalid:1;      /* Address/Count changed        */
-        unsigned int    using_sg:1;     /* using scatter list?          */
        dmamode_t       dma_mode;       /* DMA mode                     */
        int             speed;          /* DMA speed                    */
diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h
index b338936bde4f..3351b77fab36 100644
--- a/include/asm-arm/mach/map.h
+++ b/include/asm-arm/mach/map.h
@@ -27,9 +27,6 @@ struct meminfo;
 #define MT_ROM                  6
 #define MT_IXP2000_DEVICE       7
-#define __phys_to_pfn(paddr)    ((paddr) >> PAGE_SHIFT)
-#define __pfn_to_phys(pfn)      ((pfn) << PAGE_SHIFT)
 extern void create_memmap_holes(struct meminfo *);
 extern void memtable_init(struct meminfo *);
 extern void iotable_init(struct map_desc *, int);
diff --git a/include/asm-arm/mach/serial_at91rm9200.h b/include/asm-arm/mach/serial_at91rm9200.h
new file mode 100644
index 000000000000..98f4b0cb883c
--- /dev/null
+++ b/include/asm-arm/mach/serial_at91rm9200.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/mach/serial_at91rm9200.h
+ *
+ *  Based on serial_sa1100.h  by Nicolas Pitre
+ *
+ *  Copyright (C) 2002 ATMEL Rousset
+ *
+ *  Low level machine dependent UART functions.
+ */
+#include <linux/config.h>
+struct uart_port;
+/*
+ * This is a temporary structure for registering these
+ * functions; it is intended to be discarded after boot.
+ */
+struct at91rm9200_port_fns {
+        void    (*set_mctrl)(struct uart_port *, u_int);
+        u_int   (*get_mctrl)(struct uart_port *);
+        void    (*enable_ms)(struct uart_port *);
+        void    (*pm)(struct uart_port *, u_int, u_int);
+        int     (*set_wake)(struct uart_port *, u_int);
+        int     (*open)(struct uart_port *);
+        void    (*close)(struct uart_port *);
+};
+#if defined(CONFIG_SERIAL_AT91)
+void at91_register_uart_fns(struct at91rm9200_port_fns *fns);
+void at91_register_uart(int idx, int port);
+#else
+#define at91_register_uart_fns(fns) do { } while (0)
+#define at91_register_uart(idx,port) do { } while (0)
+#endif
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index 3e572364ee73..b4e1146ab682 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -25,6 +25,7 @@
 #include <linux/config.h>
 #include <linux/compiler.h>
 #include <asm/arch/memory.h>
+#include <asm/sizes.h>
 #ifndef TASK_SIZE
 /*
@@ -48,6 +49,14 @@
 #endif
 /*
+ * Size of DMA-consistent memory region.  Must be multiple of 2M,
+ * between 2MB and 14MB inclusive.
+ */
+#ifndef CONSISTENT_DMA_SIZE
+#define CONSISTENT_DMA_SIZE SZ_2M
+#endif
+/*
 * Physical vs virtual RAM address space conversion.  These are
 * private definitions which should NOT be used outside memory.h
 * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
@@ -58,6 +67,12 @@
 #endif
 /*
+ * Convert a physical address to a Page Frame Number and back
+ */
+#define __phys_to_pfn(paddr)    ((paddr) >> PAGE_SHIFT)
+#define __pfn_to_phys(pfn)      ((pfn) << PAGE_SHIFT)
+/*
 * The module space lives between the addresses given by TASK_SIZE
 * and PAGE_OFFSET - it must be within 32MB of the kernel text.
 */
diff --git a/include/asm-arm/mutex.h b/include/asm-arm/mutex.h
new file mode 100644
index 000000000000..6caa59f1f595
--- /dev/null
+++ b/include/asm-arm/mutex.h
@@ -0,0 +1,128 @@
+/*
+ * include/asm-arm/mutex.h
+ *
+ * ARM optimized mutex locking primitives
+ *
+ * Please look into asm-generic/mutex-xchg.h for a formal definition.
+ */
+#ifndef _ASM_MUTEX_H
+#define _ASM_MUTEX_H
+#if __LINUX_ARM_ARCH__ < 6
+/* On pre-ARMv6 hardware the swp based implementation is the most efficient. */
+# include <asm-generic/mutex-xchg.h>
+#else
+/*
+ * Attempting to lock a mutex on ARMv6+ can be done with a bastardized
+ * atomic decrement (it is not a reliable atomic decrement but it satisfies
+ * the defined semantics for our purpose, while being smaller and faster
+ * than a real atomic decrement or atomic swap.  The idea is to attempt
+ * decrementing the lock value only once.  If once decremented it isn't zero,
+ * or if its store-back fails due to a dispute on the exclusive store, we
+ * simply bail out immediately through the slow path where the lock will be
+ * reattempted until it succeeds.
+ */
+#define __mutex_fastpath_lock(count, fail_fn)                           \
+do {                                                                    \
+        int __ex_flag, __res;                                           \
+                                                                        \
+        typecheck(atomic_t *, count);                                   \
+        typecheck_fn(fastcall void (*)(atomic_t *), fail_fn);           \
+                                                                        \
+        __asm__ (                                                       \
+                "ldrex  %0, [%2]        \n"                             \
+                "sub    %0, %0, #1      \n"                             \
+                "strex  %1, %0, [%2]    \n"                             \
+                                                                        \
+                : "=&r" (__res), "=&r" (__ex_flag)                      \
+                : "r" (&(count)->counter)                               \
+                : "cc","memory" );                                      \
+                                                                        \
+        if (unlikely(__res || __ex_flag))                               \
+                fail_fn(count);                                         \
+} while (0)
+#define __mutex_fastpath_lock_retval(count, fail_fn)                    \
+({                                                                      \
+        int __ex_flag, __res;                                           \
+                                                                        \
+        typecheck(atomic_t *, count);                                   \
+        typecheck_fn(fastcall int (*)(atomic_t *), fail_fn);            \
+                                                                        \
+        __asm__ (                                                       \
+                "ldrex  %0, [%2]        \n"                             \
+                "sub    %0, %0, #1      \n"                             \
+                "strex  %1, %0, [%2]    \n"                             \
+                                                                        \
+                : "=&r" (__res), "=&r" (__ex_flag)                      \
+                : "r" (&(count)->counter)                               \
+                : "cc","memory" );                                      \
+                                                                        \
+        __res |= __ex_flag;                                             \
+        if (unlikely(__res != 0))                                       \
+                __res = fail_fn(count);                                 \
+        __res;                                                          \
+})
+/*
+ * Same trick is used for the unlock fast path. However the original value,
+ * rather than the result, is used to test for success in order to have
+ * better generated assembly.
+ */
+#define __mutex_fastpath_unlock(count, fail_fn)                         \
+do {                                                                    \
+        int __ex_flag, __res, __orig;                                   \
+                                                                        \
+        typecheck(atomic_t *, count);                                   \
+        typecheck_fn(fastcall void (*)(atomic_t *), fail_fn);           \
+                                                                        \
+        __asm__ (                                                       \
+                "ldrex  %0, [%3]        \n"                             \
+                "add    %1, %0, #1      \n"                             \
+                "strex  %2, %1, [%3]    \n"                             \
+                                                                        \
+                : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag)      \
+                : "r" (&(count)->counter)                               \
+                : "cc","memory" );                                      \
+                                                                        \
+        if (unlikely(__orig || __ex_flag))                              \
+                fail_fn(count);                                         \
+} while (0)
+/*
+ * If the unlock was done on a contended lock, or if the unlock simply fails
+ * then the mutex remains locked.
+ */
+#define __mutex_slowpath_needs_to_unlock()      1
+/*
+ * For __mutex_fastpath_trylock we use another construct which could be
+ * described as a "single value cmpxchg".
+ *
+ * This provides the needed trylock semantics like cmpxchg would, but it is
+ * lighter and less generic than a true cmpxchg implementation.
+ */
+static inline int
+__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
+{
+        int __ex_flag, __res, __orig;
+        __asm__ (
+                "1: ldrex       %0, [%3]        \n"
+                "subs           %1, %0, #1      \n"
+                "strexeq        %2, %1, [%3]    \n"
+                "movlt          %0, #0          \n"
+                "cmpeq          %2, #0          \n"
+                "bgt            1b              \n"
+                : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag)
+                : "r" (&count->counter)
+                : "cc", "memory" );
+        return __orig;
+}
+#endif
+#endif
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 4da1d532cbeb..416320d95419 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -170,6 +170,13 @@ extern pmd_t *top_pmd;
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+/*
+ * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
+ */
+#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
+#define ARCH_SLAB_MINALIGN 8
+#endif
 #endif /* __KERNEL__ */
 #include <asm-generic/page.h>
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
index 7d4118e09054..04f4d34c6317 100644
--- a/include/asm-arm/processor.h
+++ b/include/asm-arm/processor.h
@@ -49,6 +49,12 @@ struct thread_struct {
 #define INIT_THREAD  {  }
+#ifdef CONFIG_MMU
+#define nommu_start_thread(regs) do { } while (0)
+#else
+#define nommu_start_thread(regs) regs->ARM_r10 = current->mm->start_data
+#endif
 #define start_thread(regs,pc,sp)                                        \
 ({                                                                      \
        unsigned long *stack = (unsigned long *)sp;                     \
@@ -65,6 +71,7 @@ struct thread_struct {
        regs->ARM_r2 = stack[2];        /* r2 (envp) */                 \
        regs->ARM_r1 = stack[1];        /* r1 (argv) */                 \
        regs->ARM_r0 = stack[0];        /* r0 (argc) */                 \
+        nommu_start_thread(regs);                                       \
 })
 /* Forward declaration, a strange C thing */
@@ -85,9 +92,11 @@ unsigned long get_wchan(struct task_struct *p);
 */
 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-#define KSTK_REGS(tsk)  (((struct pt_regs *)(THREAD_START_SP + (unsigned long)(tsk)->thread_info)) - 1)
+#define task_pt_regs(p) \
-#define KSTK_EIP(tsk)   KSTK_REGS(tsk)->ARM_pc
+        ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
-#define KSTK_ESP(tsk)   KSTK_REGS(tsk)->ARM_sp
+#define KSTK_EIP(tsk)   task_pt_regs(tsk)->ARM_pc
+#define KSTK_ESP(tsk)   task_pt_regs(tsk)->ARM_sp
 /*
 * Prefetching support - only ARMv5.
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index 4377e22b7e1a..77adb7fa169b 100644
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -23,6 +23,9 @@
 #define PTRACE_OLDSETOPTIONS    21
 #define PTRACE_GET_THREAD_AREA  22
+#define PTRACE_SET_SYSCALL      23
 /*
 * PSR bits
 */
@@ -60,9 +63,11 @@
 #ifndef __ASSEMBLY__
-/* this struct defines the way the registers are stored on the
+/*
-   stack during a system call. */
+ * This struct defines the way the registers are stored on the
+ * stack during a system call.  Note that sizeof(struct pt_regs)
+ * has to be a multiple of 8.
+ */
 struct pt_regs {
        long uregs[18];
 };
diff --git a/include/asm-arm/scatterlist.h b/include/asm-arm/scatterlist.h
index 83b876fb04cc..de2f65eb42ed 100644
--- a/include/asm-arm/scatterlist.h
+++ b/include/asm-arm/scatterlist.h
@@ -9,7 +9,6 @@ struct scatterlist {
        unsigned int    offset;         /* buffer offset                 */
        dma_addr_t      dma_address;    /* dma address                   */
        unsigned int    length;         /* length                        */
-        char            *__address;     /* for set_dma_addr              */
 };
 /*
diff --git a/include/asm-arm/stat.h b/include/asm-arm/stat.h
index ec4e2c2e3b47..42c0c13999d5 100644
--- a/include/asm-arm/stat.h
+++ b/include/asm-arm/stat.h
@@ -70,14 +70,7 @@ struct stat64 {
        long long       st_size;
        unsigned long   st_blksize;
+        unsigned long long st_blocks;   /* Number 512-byte blocks allocated. */
-#if defined(__ARMEB__)
-        unsigned long   __pad4;         /* Future possible st_blocks hi bits */
-        unsigned long   st_blocks;      /* Number 512-byte blocks allocated. */
-#else /* Must be little */
-        unsigned long   st_blocks;      /* Number 512-byte blocks allocated. */
-        unsigned long   __pad4;         /* Future possible st_blocks hi bits */
-#endif
        unsigned long   st_atime;
        unsigned long   st_atime_nsec;
@@ -89,6 +82,6 @@ struct stat64 {
        unsigned long   st_ctime_nsec;
        unsigned long long      st_ino;
-} __attribute__((packed));
+};
 #endif
diff --git a/include/asm-arm/statfs.h b/include/asm-arm/statfs.h
index e81f82783b87..a02e6a8c3d70 100644
--- a/include/asm-arm/statfs.h
+++ b/include/asm-arm/statfs.h
@@ -1,6 +1,42 @@
 #ifndef _ASMARM_STATFS_H
 #define _ASMARM_STATFS_H
-#include <asm-generic/statfs.h>
+#ifndef __KERNEL_STRICT_NAMES
+# include <linux/types.h>
+typedef __kernel_fsid_t fsid_t;
+#endif
+struct statfs {
+        __u32 f_type;
+        __u32 f_bsize;
+        __u32 f_blocks;
+        __u32 f_bfree;
+        __u32 f_bavail;
+        __u32 f_files;
+        __u32 f_ffree;
+        __kernel_fsid_t f_fsid;
+        __u32 f_namelen;
+        __u32 f_frsize;
+        __u32 f_spare[5];
+};
+/*
+ * With EABI there is 4 bytes of padding added to this structure.
+ * Let's pack it so the padding goes away to simplify dual ABI support.
+ * Note that user space does NOT have to pack this structure.
+ */
+struct statfs64 {
+        __u32 f_type;
+        __u32 f_bsize;
+        __u64 f_blocks;
+        __u64 f_bfree;
+        __u64 f_bavail;
+        __u64 f_files;
+        __u64 f_ffree;
+        __kernel_fsid_t f_fsid;
+        __u32 f_namelen;
+        __u32 f_frsize;
+        __u32 f_spare[5];
+} __attribute__ ((packed,aligned(4)));
 #endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 5621d61ebc07..eb2de8c10515 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -168,10 +168,20 @@ extern struct task_struct *__switch_to(struct task_struct *, struct thread_info
 #define switch_to(prev,next,last)                                       \
 do {                                                                    \
-        last = __switch_to(prev,prev->thread_info,next->thread_info);   \
+        last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));        \
 } while (0)
 /*
+ * On SMP systems, when the scheduler does migration-cost autodetection,
+ * it needs a way to flush as much of the CPU's caches as possible.
+ *
+ * TODO: fill this in!
+ */
+static inline void sched_cacheflush(void)
+{
+}
+/*
 * CPU interrupt mask handling.
 */
 #if __LINUX_ARM_ARCH__ >= 6
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index 7c98557b717f..33a33cbb6329 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -96,13 +96,10 @@ static inline struct thread_info *current_thread_info(void)
 extern struct thread_info *alloc_thread_info(struct task_struct *task);
 extern void free_thread_info(struct thread_info *);
-#define get_thread_info(ti)     get_task_struct((ti)->task)
-#define put_thread_info(ti)     put_task_struct((ti)->task)
 #define thread_saved_pc(tsk)    \
-        ((unsigned long)(pc_pointer((tsk)->thread_info->cpu_context.pc)))
+        ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc)))
 #define thread_saved_fp(tsk)    \
-        ((unsigned long)((tsk)->thread_info->cpu_context.fp))
+        ((unsigned long)(task_thread_info(tsk)->cpu_context.fp))
 extern void iwmmxt_task_disable(struct thread_info *);
 extern void iwmmxt_task_copy(struct thread_info *, void *);
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index d626e70faded..77430d6178ae 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -15,10 +15,12 @@
 #include <linux/linkage.h>
-#if defined(__thumb__)
+#define __NR_OABI_SYSCALL_BASE  0x900000
+#if defined(__thumb__) || defined(__ARM_EABI__)
 #define __NR_SYSCALL_BASE       0
 #else
-#define __NR_SYSCALL_BASE       0x900000
+#define __NR_SYSCALL_BASE       __NR_OABI_SYSCALL_BASE
 #endif
 /*
@@ -373,13 +375,13 @@
 #define __sys1(x) __sys2(x)
 #ifndef __syscall
-#if defined(__thumb__)
+#if defined(__thumb__) || defined(__ARM_EABI__)
-#define __syscall(name)                                 \
+#define __SYS_REG(name) register long __sysreg __asm__("r7") = __NR_##name;
-        "push   {r7}\n\t"                               \
+#define __SYS_REG_LIST(regs...) "r" (__sysreg) , ##regs
-        "mov    r7, #" __sys1(__NR_##name) "\n\t"       \
+#define __syscall(name) "swi\t0"
-        "swi    0\n\t"                                  \
-        "pop    {r7}"
 #else
+#define __SYS_REG(name)
+#define __SYS_REG_LIST(regs...) regs
 #define __syscall(name) "swi\t" __sys1(__NR_##name) ""
 #endif
 #endif
@@ -395,33 +397,34 @@ do {									\
 #define _syscall0(type,name)                                            \
 type name(void) {                                                       \
+  __SYS_REG(name)                                                       \
  register long __res_r0 __asm__("r0");                                 \
  long __res;                                                           \
  __asm__ __volatile__ (                                                \
  __syscall(name)                                                       \
        : "=r" (__res_r0)                                               \
-        :                                                               \
+        : __SYS_REG_LIST() );                                           \
-        : "lr");                                                        \
  __res = __res_r0;                                                     \
  __syscall_return(type,__res);                                         \
 }
 #define _syscall1(type,name,type1,arg1)                                 \
 type name(type1 arg1) {                                                 \
+  __SYS_REG(name)                                                       \
  register long __r0 __asm__("r0") = (long)arg1;                        \
  register long __res_r0 __asm__("r0");                                 \
  long __res;                                                           \
  __asm__ __volatile__ (                                                \
  __syscall(name)                                                       \
        : "=r" (__res_r0)                                               \
-        : "r" (__r0)                                                    \
+        : __SYS_REG_LIST( "0" (__r0) ) );                               \
-        : "lr");                                                        \
  __res = __res_r0;                                                     \
  __syscall_return(type,__res);                                         \
 }
 #define _syscall2(type,name,type1,arg1,type2,arg2)                      \
 type name(type1 arg1,type2 arg2) {                                      \
+  __SYS_REG(name)                                                       \
  register long __r0 __asm__("r0") = (long)arg1;                        \
  register long __r1 __asm__("r1") = (long)arg2;                        \
  register long __res_r0 __asm__("r0");                                 \
@@ -429,8 +432,7 @@ type name(type1 arg1,type2 arg2) {					\
  __asm__ __volatile__ (                                                \
  __syscall(name)                                                       \
        : "=r" (__res_r0)                                               \
-        : "r" (__r0),"r" (__r1)                                         \
+        : __SYS_REG_LIST( "0" (__r0), "r" (__r1) ) );                   \
-        : "lr");                                                        \
  __res = __res_r0;                                                     \
  __syscall_return(type,__res);                                         \
 }
@@ -438,6 +440,7 @@ type name(type1 arg1,type2 arg2) {					\
 #define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)           \
 type name(type1 arg1,type2 arg2,type3 arg3) {                           \
+  __SYS_REG(name)                                                       \
  register long __r0 __asm__("r0") = (long)arg1;                        \
  register long __r1 __asm__("r1") = (long)arg2;                        \
  register long __r2 __asm__("r2") = (long)arg3;                        \
@@ -446,8 +449,7 @@ type name(type1 arg1,type2 arg2,type3 arg3) {				\
  __asm__ __volatile__ (                                                \
  __syscall(name)                                                       \
        : "=r" (__res_r0)                                               \
-        : "r" (__r0),"r" (__r1),"r" (__r2)                              \
+        : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2) ) );       \
-        : "lr");                                                        \
  __res = __res_r0;                                                     \
  __syscall_return(type,__res);                                         \
 }
@@ -455,6 +457,7 @@ type name(type1 arg1,type2 arg2,type3 arg3) {				\
 #define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4)\
 type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) {             \
+  __SYS_REG(name)                                                       \
  register long __r0 __asm__("r0") = (long)arg1;                        \
  register long __r1 __asm__("r1") = (long)arg2;                        \
  register long __r2 __asm__("r2") = (long)arg3;                        \
@@ -464,8 +467,7 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) {		\
  __asm__ __volatile__ (                                                \
  __syscall(name)                                                       \
        : "=r" (__res_r0)                                               \
-        : "r" (__r0),"r" (__r1),"r" (__r2),"r" (__r3)                   \
+        : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) ) ); \
-        : "lr");                                                        \
  __res = __res_r0;                                                     \
  __syscall_return(type,__res);                                         \
 }
@@ -473,6 +475,7 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) {		\
 #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5)     \
 type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) { \
+  __SYS_REG(name)                                                       \
  register long __r0 __asm__("r0") = (long)arg1;                        \
  register long __r1 __asm__("r1") = (long)arg2;                        \
  register long __r2 __asm__("r2") = (long)arg3;                        \
@@ -483,14 +486,15 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) {	\
  __asm__ __volatile__ (                                                \
  __syscall(name)                                                       \
        : "=r" (__res_r0)                                               \
-        : "r" (__r0),"r" (__r1),"r" (__r2),"r" (__r3),"r" (__r4)        \
+        : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2),           \
-        : "lr");                                                        \
+                          "r" (__r3), "r" (__r4) ) );                   \
  __res = __res_r0;                                                     \
  __syscall_return(type,__res);                                         \
 }
 #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6)  \
 type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) {     \
+  __SYS_REG(name)                                                       \
  register long __r0 __asm__("r0") = (long)arg1;                        \
  register long __r1 __asm__("r1") = (long)arg2;                        \
  register long __r2 __asm__("r2") = (long)arg3;                        \
@@ -502,30 +506,33 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
  __asm__ __volatile__ (                                                \
  __syscall(name)                                                       \
        : "=r" (__res_r0)                                               \
-        : "r" (__r0),"r" (__r1),"r" (__r2),"r" (__r3), "r" (__r4),"r" (__r5)            \
+        : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2),           \
-        : "lr");                                                        \
+                          "r" (__r3), "r" (__r4), "r" (__r5) ) );       \
  __res = __res_r0;                                                     \
  __syscall_return(type,__res);                                         \
 }
 #ifdef __KERNEL__
 #define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
 #define __ARCH_WANT_SYS_GETHOSTNAME
 #define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_SOCKETCALL
 #define __ARCH_WANT_SYS_GETPGRP
 #define __ARCH_WANT_SYS_LLSEEK
 #define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
 #define __ARCH_WANT_SYS_SIGPENDING
 #define __ARCH_WANT_SYS_SIGPROCMASK
 #define __ARCH_WANT_SYS_RT_SIGACTION
+#if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT)
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_SYS_SOCKETCALL
+#endif
 #endif
 #ifdef __KERNEL_SYSCALLS__