diff options
Diffstat (limited to 'include/asm-arm')
-rw-r--r-- | include/asm-arm/arch-davinci/gpio.h | 156 | ||||
-rw-r--r-- | include/asm-arm/arch-davinci/hardware.h | 38 |
2 files changed, 194 insertions, 0 deletions
diff --git a/include/asm-arm/arch-davinci/gpio.h b/include/asm-arm/arch-davinci/gpio.h new file mode 100644 index 000000000000..ea24a0e0bfd6 --- /dev/null +++ b/include/asm-arm/arch-davinci/gpio.h | |||
@@ -0,0 +1,156 @@ | |||
1 | /* | ||
2 | * TI DaVinci GPIO Support | ||
3 | * | ||
4 | * Copyright (c) 2006 David Brownell | ||
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef __DAVINCI_GPIO_H | ||
14 | #define __DAVINCI_GPIO_H | ||
15 | |||
16 | /* | ||
17 | * basic gpio routines | ||
18 | * | ||
19 | * board-specific init should be done by arch/.../.../board-XXX.c (maybe | ||
20 | * initializing banks together) rather than boot loaders; kexec() won't | ||
21 | * go through boot loaders. | ||
22 | * | ||
23 | * the gpio clock will be turned on when gpios are used, and you may also | ||
24 | * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are | ||
25 | * used as gpios, not with other peripherals. | ||
26 | * | ||
27 | * GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe | ||
28 | * for later updates, code should write GPIO(N) or: | ||
29 | * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) | ||
30 | * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) | ||
31 | * | ||
32 | * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc | ||
33 | * for now, that's != GPIO(N) | ||
34 | */ | ||
35 | #define GPIO(X) (X) /* 0 <= X <= 70 */ | ||
36 | #define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */ | ||
37 | #define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */ | ||
38 | |||
39 | struct gpio_controller { | ||
40 | u32 dir; | ||
41 | u32 out_data; | ||
42 | u32 set_data; | ||
43 | u32 clr_data; | ||
44 | u32 in_data; | ||
45 | u32 set_rising; | ||
46 | u32 clr_rising; | ||
47 | u32 set_falling; | ||
48 | u32 clr_falling; | ||
49 | u32 intstat; | ||
50 | }; | ||
51 | |||
52 | /* The __gpio_to_controller() and __gpio_mask() functions inline to constants | ||
53 | * with constant parameters; or in outlined code they execute at runtime. | ||
54 | * | ||
55 | * You'd access the controller directly when reading or writing more than | ||
56 | * one gpio value at a time, and to support wired logic where the value | ||
57 | * being driven by the cpu need not match the value read back. | ||
58 | * | ||
59 | * These are NOT part of the cross-platform GPIO interface | ||
60 | */ | ||
61 | static inline struct gpio_controller *__iomem | ||
62 | __gpio_to_controller(unsigned gpio) | ||
63 | { | ||
64 | void *__iomem ptr; | ||
65 | |||
66 | if (gpio < 32) | ||
67 | ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); | ||
68 | else if (gpio < 64) | ||
69 | ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); | ||
70 | else if (gpio < DAVINCI_N_GPIO) | ||
71 | ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); | ||
72 | else | ||
73 | ptr = NULL; | ||
74 | return ptr; | ||
75 | } | ||
76 | |||
77 | static inline u32 __gpio_mask(unsigned gpio) | ||
78 | { | ||
79 | return 1 << (gpio % 32); | ||
80 | } | ||
81 | |||
82 | /* The get/set/clear functions will inline when called with constant | ||
83 | * parameters, for low-overhead bitbanging. Illegal constant parameters | ||
84 | * cause link-time errors. | ||
85 | * | ||
86 | * Otherwise, calls with variable parameters use outlined functions. | ||
87 | */ | ||
88 | extern int __error_inval_gpio(void); | ||
89 | |||
90 | extern void __gpio_set(unsigned gpio, int value); | ||
91 | extern int __gpio_get(unsigned gpio); | ||
92 | |||
93 | static inline void gpio_set_value(unsigned gpio, int value) | ||
94 | { | ||
95 | if (__builtin_constant_p(value)) { | ||
96 | struct gpio_controller *__iomem g; | ||
97 | u32 mask; | ||
98 | |||
99 | if (gpio >= DAVINCI_N_GPIO) | ||
100 | __error_inval_gpio(); | ||
101 | |||
102 | g = __gpio_to_controller(gpio); | ||
103 | mask = __gpio_mask(gpio); | ||
104 | if (value) | ||
105 | __raw_writel(mask, &g->set_data); | ||
106 | else | ||
107 | __raw_writel(mask, &g->clr_data); | ||
108 | return; | ||
109 | } | ||
110 | |||
111 | __gpio_set(gpio, value); | ||
112 | } | ||
113 | |||
114 | /* Returns zero or nonzero; works for gpios configured as inputs OR | ||
115 | * as outputs. | ||
116 | * | ||
117 | * NOTE: changes in reported values are synchronized to the GPIO clock. | ||
118 | * This is most easily seen after calling gpio_set_value() and then immediatly | ||
119 | * gpio_get_value(), where the gpio_get_value() would return the old value | ||
120 | * until the GPIO clock ticks and the new value gets latched. | ||
121 | */ | ||
122 | |||
123 | static inline int gpio_get_value(unsigned gpio) | ||
124 | { | ||
125 | struct gpio_controller *__iomem g; | ||
126 | |||
127 | if (!__builtin_constant_p(gpio)) | ||
128 | return __gpio_get(gpio); | ||
129 | |||
130 | if (gpio >= DAVINCI_N_GPIO) | ||
131 | return __error_inval_gpio(); | ||
132 | |||
133 | g = __gpio_to_controller(gpio); | ||
134 | return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data)); | ||
135 | } | ||
136 | |||
137 | /* powerup default direction is IN */ | ||
138 | extern int gpio_direction_input(unsigned gpio); | ||
139 | extern int gpio_direction_output(unsigned gpio, int value); | ||
140 | |||
141 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
142 | |||
143 | extern int gpio_request(unsigned gpio, const char *tag); | ||
144 | extern void gpio_free(unsigned gpio); | ||
145 | |||
146 | static inline int gpio_to_irq(unsigned gpio) | ||
147 | { | ||
148 | return DAVINCI_N_AINTC_IRQ + gpio; | ||
149 | } | ||
150 | |||
151 | static inline int irq_to_gpio(unsigned irq) | ||
152 | { | ||
153 | return irq - DAVINCI_N_AINTC_IRQ; | ||
154 | } | ||
155 | |||
156 | #endif /* __DAVINCI_GPIO_H */ | ||
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index 60362d80229e..a2e8969afaca 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h | |||
@@ -11,4 +11,42 @@ | |||
11 | #ifndef __ASM_ARCH_HARDWARE_H | 11 | #ifndef __ASM_ARCH_HARDWARE_H |
12 | #define __ASM_ARCH_HARDWARE_H | 12 | #define __ASM_ARCH_HARDWARE_H |
13 | 13 | ||
14 | /* | ||
15 | * Base register addresses | ||
16 | */ | ||
17 | #define DAVINCI_DMA_3PCC_BASE (0x01C00000) | ||
18 | #define DAVINCI_DMA_3PTC0_BASE (0x01C10000) | ||
19 | #define DAVINCI_DMA_3PTC1_BASE (0x01C10400) | ||
20 | #define DAVINCI_I2C_BASE (0x01C21000) | ||
21 | #define DAVINCI_PWM0_BASE (0x01C22000) | ||
22 | #define DAVINCI_PWM1_BASE (0x01C22400) | ||
23 | #define DAVINCI_PWM2_BASE (0x01C22800) | ||
24 | #define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) | ||
25 | #define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) | ||
26 | #define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) | ||
27 | #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) | ||
28 | #define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) | ||
29 | #define DAVINCI_IEEE1394_BASE (0x01C60000) | ||
30 | #define DAVINCI_USB_OTG_BASE (0x01C64000) | ||
31 | #define DAVINCI_CFC_ATA_BASE (0x01C66000) | ||
32 | #define DAVINCI_SPI_BASE (0x01C66800) | ||
33 | #define DAVINCI_GPIO_BASE (0x01C67000) | ||
34 | #define DAVINCI_UHPI_BASE (0x01C67800) | ||
35 | #define DAVINCI_VPSS_REGS_BASE (0x01C70000) | ||
36 | #define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) | ||
37 | #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) | ||
38 | #define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) | ||
39 | #define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) | ||
40 | #define DAVINCI_IMCOP_BASE (0x01CC0000) | ||
41 | #define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) | ||
42 | #define DAVINCI_VLYNQ_BASE (0x01E01000) | ||
43 | #define DAVINCI_MCBSP_BASE (0x01E02000) | ||
44 | #define DAVINCI_MMC_SD_BASE (0x01E10000) | ||
45 | #define DAVINCI_MS_BASE (0x01E20000) | ||
46 | #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) | ||
47 | #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) | ||
48 | #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) | ||
49 | #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) | ||
50 | #define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) | ||
51 | |||
14 | #endif /* __ASM_ARCH_HARDWARE_H */ | 52 | #endif /* __ASM_ARCH_HARDWARE_H */ |