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-rw-r--r--include/asm-arm/locks.h40
1 files changed, 26 insertions, 14 deletions
diff --git a/include/asm-arm/locks.h b/include/asm-arm/locks.h
index c26298f3891f..f08dc8447913 100644
--- a/include/asm-arm/locks.h
+++ b/include/asm-arm/locks.h
@@ -28,7 +28,8 @@
28" blmi " #fail \ 28" blmi " #fail \
29 : \ 29 : \
30 : "r" (ptr), "I" (1) \ 30 : "r" (ptr), "I" (1) \
31 : "ip", "lr", "cc", "memory"); \ 31 : "ip", "lr", "cc"); \
32 smp_mb(); \
32 }) 33 })
33 34
34#define __down_op_ret(ptr,fail) \ 35#define __down_op_ret(ptr,fail) \
@@ -48,12 +49,14 @@
48" mov %0, ip" \ 49" mov %0, ip" \
49 : "=&r" (ret) \ 50 : "=&r" (ret) \
50 : "r" (ptr), "I" (1) \ 51 : "r" (ptr), "I" (1) \
51 : "ip", "lr", "cc", "memory"); \ 52 : "ip", "lr", "cc"); \
53 smp_mb(); \
52 ret; \ 54 ret; \
53 }) 55 })
54 56
55#define __up_op(ptr,wake) \ 57#define __up_op(ptr,wake) \
56 ({ \ 58 ({ \
59 smp_mb(); \
57 __asm__ __volatile__( \ 60 __asm__ __volatile__( \
58 "@ up_op\n" \ 61 "@ up_op\n" \
59"1: ldrex lr, [%0]\n" \ 62"1: ldrex lr, [%0]\n" \
@@ -61,12 +64,12 @@
61" strex ip, lr, [%0]\n" \ 64" strex ip, lr, [%0]\n" \
62" teq ip, #0\n" \ 65" teq ip, #0\n" \
63" bne 1b\n" \ 66" bne 1b\n" \
64" teq lr, #0\n" \ 67" cmp lr, #0\n" \
65" movle ip, %0\n" \ 68" movle ip, %0\n" \
66" blle " #wake \ 69" blle " #wake \
67 : \ 70 : \
68 : "r" (ptr), "I" (1) \ 71 : "r" (ptr), "I" (1) \
69 : "ip", "lr", "cc", "memory"); \ 72 : "ip", "lr", "cc"); \
70 }) 73 })
71 74
72/* 75/*
@@ -92,15 +95,17 @@
92" blne " #fail \ 95" blne " #fail \
93 : \ 96 : \
94 : "r" (ptr), "I" (RW_LOCK_BIAS) \ 97 : "r" (ptr), "I" (RW_LOCK_BIAS) \
95 : "ip", "lr", "cc", "memory"); \ 98 : "ip", "lr", "cc"); \
99 smp_mb(); \
96 }) 100 })
97 101
98#define __up_op_write(ptr,wake) \ 102#define __up_op_write(ptr,wake) \
99 ({ \ 103 ({ \
104 smp_mb(); \
100 __asm__ __volatile__( \ 105 __asm__ __volatile__( \
101 "@ up_op_read\n" \ 106 "@ up_op_read\n" \
102"1: ldrex lr, [%0]\n" \ 107"1: ldrex lr, [%0]\n" \
103" add lr, lr, %1\n" \ 108" adds lr, lr, %1\n" \
104" strex ip, lr, [%0]\n" \ 109" strex ip, lr, [%0]\n" \
105" teq ip, #0\n" \ 110" teq ip, #0\n" \
106" bne 1b\n" \ 111" bne 1b\n" \
@@ -108,7 +113,7 @@
108" blcs " #wake \ 113" blcs " #wake \
109 : \ 114 : \
110 : "r" (ptr), "I" (RW_LOCK_BIAS) \ 115 : "r" (ptr), "I" (RW_LOCK_BIAS) \
111 : "ip", "lr", "cc", "memory"); \ 116 : "ip", "lr", "cc"); \
112 }) 117 })
113 118
114#define __down_op_read(ptr,fail) \ 119#define __down_op_read(ptr,fail) \
@@ -116,6 +121,7 @@
116 121
117#define __up_op_read(ptr,wake) \ 122#define __up_op_read(ptr,wake) \
118 ({ \ 123 ({ \
124 smp_mb(); \
119 __asm__ __volatile__( \ 125 __asm__ __volatile__( \
120 "@ up_op_read\n" \ 126 "@ up_op_read\n" \
121"1: ldrex lr, [%0]\n" \ 127"1: ldrex lr, [%0]\n" \
@@ -128,7 +134,7 @@
128" bleq " #wake \ 134" bleq " #wake \
129 : \ 135 : \
130 : "r" (ptr), "I" (1) \ 136 : "r" (ptr), "I" (1) \
131 : "ip", "lr", "cc", "memory"); \ 137 : "ip", "lr", "cc"); \
132 }) 138 })
133 139
134#else 140#else
@@ -148,7 +154,8 @@
148" blmi " #fail \ 154" blmi " #fail \
149 : \ 155 : \
150 : "r" (ptr), "I" (1) \ 156 : "r" (ptr), "I" (1) \
151 : "ip", "lr", "cc", "memory"); \ 157 : "ip", "lr", "cc"); \
158 smp_mb(); \
152 }) 159 })
153 160
154#define __down_op_ret(ptr,fail) \ 161#define __down_op_ret(ptr,fail) \
@@ -169,12 +176,14 @@
169" mov %0, ip" \ 176" mov %0, ip" \
170 : "=&r" (ret) \ 177 : "=&r" (ret) \
171 : "r" (ptr), "I" (1) \ 178 : "r" (ptr), "I" (1) \
172 : "ip", "lr", "cc", "memory"); \ 179 : "ip", "lr", "cc"); \
180 smp_mb(); \
173 ret; \ 181 ret; \
174 }) 182 })
175 183
176#define __up_op(ptr,wake) \ 184#define __up_op(ptr,wake) \
177 ({ \ 185 ({ \
186 smp_mb(); \
178 __asm__ __volatile__( \ 187 __asm__ __volatile__( \
179 "@ up_op\n" \ 188 "@ up_op\n" \
180" mrs ip, cpsr\n" \ 189" mrs ip, cpsr\n" \
@@ -188,7 +197,7 @@
188" blle " #wake \ 197" blle " #wake \
189 : \ 198 : \
190 : "r" (ptr), "I" (1) \ 199 : "r" (ptr), "I" (1) \
191 : "ip", "lr", "cc", "memory"); \ 200 : "ip", "lr", "cc"); \
192 }) 201 })
193 202
194/* 203/*
@@ -215,7 +224,8 @@
215" blne " #fail \ 224" blne " #fail \
216 : \ 225 : \
217 : "r" (ptr), "I" (RW_LOCK_BIAS) \ 226 : "r" (ptr), "I" (RW_LOCK_BIAS) \
218 : "ip", "lr", "cc", "memory"); \ 227 : "ip", "lr", "cc"); \
228 smp_mb(); \
219 }) 229 })
220 230
221#define __up_op_write(ptr,wake) \ 231#define __up_op_write(ptr,wake) \
@@ -233,7 +243,8 @@
233" blcs " #wake \ 243" blcs " #wake \
234 : \ 244 : \
235 : "r" (ptr), "I" (RW_LOCK_BIAS) \ 245 : "r" (ptr), "I" (RW_LOCK_BIAS) \
236 : "ip", "lr", "cc", "memory"); \ 246 : "ip", "lr", "cc"); \
247 smp_mb(); \
237 }) 248 })
238 249
239#define __down_op_read(ptr,fail) \ 250#define __down_op_read(ptr,fail) \
@@ -241,6 +252,7 @@
241 252
242#define __up_op_read(ptr,wake) \ 253#define __up_op_read(ptr,wake) \
243 ({ \ 254 ({ \
255 smp_mb(); \
244 __asm__ __volatile__( \ 256 __asm__ __volatile__( \
245 "@ up_op_read\n" \ 257 "@ up_op_read\n" \
246" mrs ip, cpsr\n" \ 258" mrs ip, cpsr\n" \
@@ -254,7 +266,7 @@
254" bleq " #wake \ 266" bleq " #wake \
255 : \ 267 : \
256 : "r" (ptr), "I" (1) \ 268 : "r" (ptr), "I" (1) \
257 : "ip", "lr", "cc", "memory"); \ 269 : "ip", "lr", "cc"); \
258 }) 270 })
259 271
260#endif 272#endif
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