diff options
Diffstat (limited to 'include/asm-arm/hardware')
-rw-r--r-- | include/asm-arm/hardware/iop3xx.h | 301 | ||||
-rw-r--r-- | include/asm-arm/hardware/locomo.h | 33 | ||||
-rw-r--r-- | include/asm-arm/hardware/sharpsl_pm.h | 1 |
3 files changed, 320 insertions, 15 deletions
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h new file mode 100644 index 000000000000..1018a7486ab7 --- /dev/null +++ b/include/asm-arm/hardware/iop3xx.h | |||
@@ -0,0 +1,301 @@ | |||
1 | /* | ||
2 | * include/asm-arm/hardware/iop3xx.h | ||
3 | * | ||
4 | * Intel IOP32X and IOP33X register definitions | ||
5 | * | ||
6 | * Author: Rory Bolt <rorybolt@pacbell.net> | ||
7 | * Copyright (C) 2002 Rory Bolt | ||
8 | * Copyright (C) 2004 Intel Corp. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __IOP3XX_H | ||
16 | #define __IOP3XX_H | ||
17 | |||
18 | /* | ||
19 | * IOP3XX GPIO handling | ||
20 | */ | ||
21 | #define GPIO_IN 0 | ||
22 | #define GPIO_OUT 1 | ||
23 | #define GPIO_LOW 0 | ||
24 | #define GPIO_HIGH 1 | ||
25 | #define IOP3XX_GPIO_LINE(x) (x) | ||
26 | |||
27 | #ifndef __ASSEMBLY__ | ||
28 | extern void gpio_line_config(int line, int direction); | ||
29 | extern int gpio_line_get(int line); | ||
30 | extern void gpio_line_set(int line, int value); | ||
31 | #endif | ||
32 | |||
33 | |||
34 | /* | ||
35 | * IOP3XX processor registers | ||
36 | */ | ||
37 | #define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000 | ||
38 | #define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000 | ||
39 | #define IOP3XX_PERIPHERAL_SIZE 0x00002000 | ||
40 | #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) | ||
41 | |||
42 | /* Address Translation Unit */ | ||
43 | #define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100) | ||
44 | #define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102) | ||
45 | #define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104) | ||
46 | #define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106) | ||
47 | #define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108) | ||
48 | #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109) | ||
49 | #define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c) | ||
50 | #define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d) | ||
51 | #define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e) | ||
52 | #define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f) | ||
53 | #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110) | ||
54 | #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114) | ||
55 | #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118) | ||
56 | #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c) | ||
57 | #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120) | ||
58 | #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124) | ||
59 | #define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c) | ||
60 | #define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e) | ||
61 | #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130) | ||
62 | #define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c) | ||
63 | #define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d) | ||
64 | #define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e) | ||
65 | #define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f) | ||
66 | #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140) | ||
67 | #define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144) | ||
68 | #define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148) | ||
69 | #define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c) | ||
70 | #define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150) | ||
71 | #define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154) | ||
72 | #define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158) | ||
73 | #define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c) | ||
74 | #define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160) | ||
75 | #define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164) | ||
76 | #define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168) | ||
77 | #define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c) | ||
78 | #define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178) | ||
79 | #define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180) | ||
80 | #define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184) | ||
81 | #define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188) | ||
82 | #define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c) | ||
83 | #define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190) | ||
84 | #define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194) | ||
85 | #define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198) | ||
86 | #define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c) | ||
87 | #define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4) | ||
88 | #define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac) | ||
89 | #define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc) | ||
90 | #define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0) | ||
91 | #define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1) | ||
92 | #define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2) | ||
93 | #define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4) | ||
94 | #define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0) | ||
95 | #define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1) | ||
96 | #define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2) | ||
97 | #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) | ||
98 | #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) | ||
99 | |||
100 | /* Messaging Unit */ | ||
101 | #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) | ||
102 | #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) | ||
103 | #define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318) | ||
104 | #define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c) | ||
105 | #define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320) | ||
106 | #define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324) | ||
107 | #define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328) | ||
108 | #define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c) | ||
109 | #define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330) | ||
110 | #define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334) | ||
111 | #define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350) | ||
112 | #define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354) | ||
113 | #define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360) | ||
114 | #define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364) | ||
115 | #define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368) | ||
116 | #define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c) | ||
117 | #define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370) | ||
118 | #define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374) | ||
119 | #define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378) | ||
120 | #define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c) | ||
121 | #define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380) | ||
122 | |||
123 | /* DMA Controller */ | ||
124 | #define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400) | ||
125 | #define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404) | ||
126 | #define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c) | ||
127 | #define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410) | ||
128 | #define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414) | ||
129 | #define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418) | ||
130 | #define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c) | ||
131 | #define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420) | ||
132 | #define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424) | ||
133 | #define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440) | ||
134 | #define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444) | ||
135 | #define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c) | ||
136 | #define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450) | ||
137 | #define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454) | ||
138 | #define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458) | ||
139 | #define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c) | ||
140 | #define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460) | ||
141 | #define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464) | ||
142 | |||
143 | /* Peripheral bus interface */ | ||
144 | #define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680) | ||
145 | #define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684) | ||
146 | #define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688) | ||
147 | #define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c) | ||
148 | #define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690) | ||
149 | #define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694) | ||
150 | #define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698) | ||
151 | #define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c) | ||
152 | #define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0) | ||
153 | #define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4) | ||
154 | #define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8) | ||
155 | #define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac) | ||
156 | #define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0) | ||
157 | #define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4) | ||
158 | #define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0) | ||
159 | #define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0) | ||
160 | #define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4) | ||
161 | |||
162 | /* Peripheral performance monitoring unit */ | ||
163 | #define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700) | ||
164 | #define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704) | ||
165 | #define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708) | ||
166 | #define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710) | ||
167 | /* PERCR0 DOESN'T EXIST - index from 1! */ | ||
168 | #define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710) | ||
169 | |||
170 | /* General Purpose I/O */ | ||
171 | #define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0004) | ||
172 | #define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0008) | ||
173 | #define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x000c) | ||
174 | |||
175 | /* Timers */ | ||
176 | #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000) | ||
177 | #define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004) | ||
178 | #define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008) | ||
179 | #define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c) | ||
180 | #define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010) | ||
181 | #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) | ||
182 | #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) | ||
183 | #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) | ||
184 | #define IOP3XX_TMR_TC 0x01 | ||
185 | #define IOP3XX_TMR_EN 0x02 | ||
186 | #define IOP3XX_TMR_RELOAD 0x04 | ||
187 | #define IOP3XX_TMR_PRIVILEGED 0x09 | ||
188 | #define IOP3XX_TMR_RATIO_1_1 0x00 | ||
189 | #define IOP3XX_TMR_RATIO_4_1 0x10 | ||
190 | #define IOP3XX_TMR_RATIO_8_1 0x20 | ||
191 | #define IOP3XX_TMR_RATIO_16_1 0x30 | ||
192 | |||
193 | /* Application accelerator unit */ | ||
194 | #define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) | ||
195 | #define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804) | ||
196 | #define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808) | ||
197 | #define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c) | ||
198 | #define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810) | ||
199 | #define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814) | ||
200 | #define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818) | ||
201 | #define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c) | ||
202 | #define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820) | ||
203 | #define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824) | ||
204 | #define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828) | ||
205 | #define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c) | ||
206 | #define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830) | ||
207 | #define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834) | ||
208 | #define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838) | ||
209 | #define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c) | ||
210 | #define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840) | ||
211 | #define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844) | ||
212 | #define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848) | ||
213 | #define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c) | ||
214 | #define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850) | ||
215 | #define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854) | ||
216 | #define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858) | ||
217 | #define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c) | ||
218 | #define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860) | ||
219 | #define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864) | ||
220 | #define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868) | ||
221 | #define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c) | ||
222 | #define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870) | ||
223 | #define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874) | ||
224 | #define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878) | ||
225 | #define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c) | ||
226 | #define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880) | ||
227 | #define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884) | ||
228 | #define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888) | ||
229 | #define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c) | ||
230 | #define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890) | ||
231 | #define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894) | ||
232 | #define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898) | ||
233 | #define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c) | ||
234 | #define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0) | ||
235 | #define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4) | ||
236 | |||
237 | /* I2C bus interface unit */ | ||
238 | #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) | ||
239 | #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) | ||
240 | #define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688) | ||
241 | #define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c) | ||
242 | #define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694) | ||
243 | #define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0) | ||
244 | #define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4) | ||
245 | #define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8) | ||
246 | #define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac) | ||
247 | #define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4) | ||
248 | |||
249 | |||
250 | /* | ||
251 | * IOP3XX I/O and Mem space regions for PCI autoconfiguration | ||
252 | */ | ||
253 | #define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000 | ||
254 | #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 | ||
255 | #define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0) | ||
256 | |||
257 | #define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 | ||
258 | #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 | ||
259 | #define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 | ||
260 | #define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR) | ||
261 | |||
262 | |||
263 | #ifndef __ASSEMBLY__ | ||
264 | void iop3xx_map_io(void); | ||
265 | void iop3xx_init_time(unsigned long); | ||
266 | unsigned long iop3xx_gettimeoffset(void); | ||
267 | |||
268 | extern struct platform_device iop3xx_i2c0_device; | ||
269 | extern struct platform_device iop3xx_i2c1_device; | ||
270 | |||
271 | extern inline void iop3xx_cp6_enable(void) | ||
272 | { | ||
273 | u32 temp; | ||
274 | |||
275 | asm volatile ( | ||
276 | "mrc p15, 0, %0, c15, c1, 0\n\t" | ||
277 | "orr %0, %0, #(1 << 6)\n\t" | ||
278 | "mcr p15, 0, %0, c15, c1, 0\n\t" | ||
279 | "mrc p15, 0, %0, c15, c1, 0\n\t" | ||
280 | "mov %0, %0\n\t" | ||
281 | "sub pc, pc, #4\n\t" | ||
282 | : "=r" (temp) ); | ||
283 | } | ||
284 | |||
285 | extern inline void iop3xx_cp6_disable(void) | ||
286 | { | ||
287 | u32 temp; | ||
288 | |||
289 | asm volatile ( | ||
290 | "mrc p15, 0, %0, c15, c1, 0\n\t" | ||
291 | "bic %0, %0, #(1 << 6)\n\t" | ||
292 | "mcr p15, 0, %0, c15, c1, 0\n\t" | ||
293 | "mrc p15, 0, %0, c15, c1, 0\n\t" | ||
294 | "mov %0, %0\n\t" | ||
295 | "sub pc, pc, #4\n\t" | ||
296 | : "=r" (temp) ); | ||
297 | } | ||
298 | #endif | ||
299 | |||
300 | |||
301 | #endif | ||
diff --git a/include/asm-arm/hardware/locomo.h b/include/asm-arm/hardware/locomo.h index 22dfb1737768..adab77780ed3 100644 --- a/include/asm-arm/hardware/locomo.h +++ b/include/asm-arm/hardware/locomo.h | |||
@@ -54,17 +54,18 @@ | |||
54 | #define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */ | 54 | #define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */ |
55 | 55 | ||
56 | /* SPI interface */ | 56 | /* SPI interface */ |
57 | #define LOCOMO_SPIMD 0x60 /* SPI mode setting */ | 57 | #define LOCOMO_SPI 0x60 |
58 | #define LOCOMO_SPICT 0x64 /* SPI mode control */ | 58 | #define LOCOMO_SPIMD 0x00 /* SPI mode setting */ |
59 | #define LOCOMO_SPIST 0x68 /* SPI status */ | 59 | #define LOCOMO_SPICT 0x04 /* SPI mode control */ |
60 | #define LOCOMO_SPIIS 0x70 /* SPI interrupt status */ | 60 | #define LOCOMO_SPIST 0x08 /* SPI status */ |
61 | #define LOCOMO_SPIWE 0x74 /* SPI interrupt status write enable */ | 61 | #define LOCOMO_SPIIS 0x10 /* SPI interrupt status */ |
62 | #define LOCOMO_SPIIE 0x78 /* SPI interrupt enable */ | 62 | #define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */ |
63 | #define LOCOMO_SPIIR 0x7c /* SPI interrupt request */ | 63 | #define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */ |
64 | #define LOCOMO_SPITD 0x80 /* SPI transfer data write */ | 64 | #define LOCOMO_SPIIR 0x1c /* SPI interrupt request */ |
65 | #define LOCOMO_SPIRD 0x84 /* SPI receive data read */ | 65 | #define LOCOMO_SPITD 0x20 /* SPI transfer data write */ |
66 | #define LOCOMO_SPITS 0x88 /* SPI transfer data shift */ | 66 | #define LOCOMO_SPIRD 0x24 /* SPI receive data read */ |
67 | #define LOCOMO_SPIRS 0x8C /* SPI receive data shift */ | 67 | #define LOCOMO_SPITS 0x28 /* SPI transfer data shift */ |
68 | #define LOCOMO_SPIRS 0x2C /* SPI receive data shift */ | ||
68 | #define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */ | 69 | #define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */ |
69 | #define LOCOMO_SPI_OVRN (1 << 2) /* Over Run bit */ | 70 | #define LOCOMO_SPI_OVRN (1 << 2) /* Over Run bit */ |
70 | #define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */ | 71 | #define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */ |
@@ -161,6 +162,7 @@ extern struct bus_type locomo_bus_type; | |||
161 | #define LOCOMO_DEVID_AUDIO 3 | 162 | #define LOCOMO_DEVID_AUDIO 3 |
162 | #define LOCOMO_DEVID_LED 4 | 163 | #define LOCOMO_DEVID_LED 4 |
163 | #define LOCOMO_DEVID_UART 5 | 164 | #define LOCOMO_DEVID_UART 5 |
165 | #define LOCOMO_DEVID_SPI 6 | ||
164 | 166 | ||
165 | struct locomo_dev { | 167 | struct locomo_dev { |
166 | struct device dev; | 168 | struct device dev; |
@@ -197,10 +199,11 @@ int locomo_driver_register(struct locomo_driver *); | |||
197 | void locomo_driver_unregister(struct locomo_driver *); | 199 | void locomo_driver_unregister(struct locomo_driver *); |
198 | 200 | ||
199 | /* GPIO control functions */ | 201 | /* GPIO control functions */ |
200 | void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned int dir); | 202 | void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir); |
201 | unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits); | 203 | int locomo_gpio_read_level(struct device *dev, unsigned int bits); |
202 | unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits); | 204 | int locomo_gpio_read_output(struct device *dev, unsigned int bits); |
203 | void locomo_gpio_write(struct locomo_dev *ldev, unsigned int bits, unsigned int set); | 205 | void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set); |
206 | |||
204 | 207 | ||
205 | /* M62332 control function */ | 208 | /* M62332 control function */ |
206 | void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel); | 209 | void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel); |
diff --git a/include/asm-arm/hardware/sharpsl_pm.h b/include/asm-arm/hardware/sharpsl_pm.h index ecf15b83956f..a836e76a14f7 100644 --- a/include/asm-arm/hardware/sharpsl_pm.h +++ b/include/asm-arm/hardware/sharpsl_pm.h | |||
@@ -25,6 +25,7 @@ struct sharpsl_charger_machinfo { | |||
25 | void (*measure_temp)(int); | 25 | void (*measure_temp)(int); |
26 | void (*presuspend)(void); | 26 | void (*presuspend)(void); |
27 | void (*postsuspend)(void); | 27 | void (*postsuspend)(void); |
28 | void (*earlyresume)(void); | ||
28 | unsigned long (*read_devdata)(int); | 29 | unsigned long (*read_devdata)(int); |
29 | #define SHARPSL_BATT_VOLT 1 | 30 | #define SHARPSL_BATT_VOLT 1 |
30 | #define SHARPSL_BATT_TEMP 2 | 31 | #define SHARPSL_BATT_TEMP 2 |