diff options
Diffstat (limited to 'include/asm-arm/hardware')
-rw-r--r-- | include/asm-arm/hardware/amba.h | 55 | ||||
-rw-r--r-- | include/asm-arm/hardware/amba_clcd.h | 271 | ||||
-rw-r--r-- | include/asm-arm/hardware/amba_kmi.h | 92 | ||||
-rw-r--r-- | include/asm-arm/hardware/amba_serial.h | 161 |
4 files changed, 0 insertions, 579 deletions
diff --git a/include/asm-arm/hardware/amba.h b/include/asm-arm/hardware/amba.h deleted file mode 100644 index 51e6e54b2aa1..000000000000 --- a/include/asm-arm/hardware/amba.h +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/hardware/amba.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef ASMARM_AMBA_H | ||
11 | #define ASMARM_AMBA_H | ||
12 | |||
13 | #define AMBA_NR_IRQS 2 | ||
14 | |||
15 | struct amba_device { | ||
16 | struct device dev; | ||
17 | struct resource res; | ||
18 | u64 dma_mask; | ||
19 | unsigned int periphid; | ||
20 | unsigned int irq[AMBA_NR_IRQS]; | ||
21 | }; | ||
22 | |||
23 | struct amba_id { | ||
24 | unsigned int id; | ||
25 | unsigned int mask; | ||
26 | void *data; | ||
27 | }; | ||
28 | |||
29 | struct amba_driver { | ||
30 | struct device_driver drv; | ||
31 | int (*probe)(struct amba_device *, void *); | ||
32 | int (*remove)(struct amba_device *); | ||
33 | void (*shutdown)(struct amba_device *); | ||
34 | int (*suspend)(struct amba_device *, pm_message_t); | ||
35 | int (*resume)(struct amba_device *); | ||
36 | struct amba_id *id_table; | ||
37 | }; | ||
38 | |||
39 | #define amba_get_drvdata(d) dev_get_drvdata(&d->dev) | ||
40 | #define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p) | ||
41 | |||
42 | int amba_driver_register(struct amba_driver *); | ||
43 | void amba_driver_unregister(struct amba_driver *); | ||
44 | int amba_device_register(struct amba_device *, struct resource *); | ||
45 | void amba_device_unregister(struct amba_device *); | ||
46 | struct amba_device *amba_find_device(const char *, struct device *, unsigned int, unsigned int); | ||
47 | int amba_request_regions(struct amba_device *, const char *); | ||
48 | void amba_release_regions(struct amba_device *); | ||
49 | |||
50 | #define amba_config(d) (((d)->periphid >> 24) & 0xff) | ||
51 | #define amba_rev(d) (((d)->periphid >> 20) & 0x0f) | ||
52 | #define amba_manf(d) (((d)->periphid >> 12) & 0xff) | ||
53 | #define amba_part(d) ((d)->periphid & 0xfff) | ||
54 | |||
55 | #endif | ||
diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h deleted file mode 100644 index 6b8d73dc1ab0..000000000000 --- a/include/asm-arm/hardware/amba_clcd.h +++ /dev/null | |||
@@ -1,271 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel. | ||
3 | * | ||
4 | * David A Rusling | ||
5 | * | ||
6 | * Copyright (C) 2001 ARM Limited | ||
7 | * | ||
8 | * This file is subject to the terms and conditions of the GNU General Public | ||
9 | * License. See the file COPYING in the main directory of this archive | ||
10 | * for more details. | ||
11 | */ | ||
12 | #include <linux/config.h> | ||
13 | #include <linux/fb.h> | ||
14 | |||
15 | /* | ||
16 | * CLCD Controller Internal Register addresses | ||
17 | */ | ||
18 | #define CLCD_TIM0 0x00000000 | ||
19 | #define CLCD_TIM1 0x00000004 | ||
20 | #define CLCD_TIM2 0x00000008 | ||
21 | #define CLCD_TIM3 0x0000000c | ||
22 | #define CLCD_UBAS 0x00000010 | ||
23 | #define CLCD_LBAS 0x00000014 | ||
24 | |||
25 | #if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW) | ||
26 | #define CLCD_IENB 0x00000018 | ||
27 | #define CLCD_CNTL 0x0000001c | ||
28 | #else | ||
29 | /* | ||
30 | * Someone rearranged these two registers on the Versatile | ||
31 | * platform... | ||
32 | */ | ||
33 | #define CLCD_IENB 0x0000001c | ||
34 | #define CLCD_CNTL 0x00000018 | ||
35 | #endif | ||
36 | |||
37 | #define CLCD_STAT 0x00000020 | ||
38 | #define CLCD_INTR 0x00000024 | ||
39 | #define CLCD_UCUR 0x00000028 | ||
40 | #define CLCD_LCUR 0x0000002C | ||
41 | #define CLCD_PALL 0x00000200 | ||
42 | #define CLCD_PALETTE 0x00000200 | ||
43 | |||
44 | #define TIM2_CLKSEL (1 << 5) | ||
45 | #define TIM2_IVS (1 << 11) | ||
46 | #define TIM2_IHS (1 << 12) | ||
47 | #define TIM2_IPC (1 << 13) | ||
48 | #define TIM2_IOE (1 << 14) | ||
49 | #define TIM2_BCD (1 << 26) | ||
50 | |||
51 | #define CNTL_LCDEN (1 << 0) | ||
52 | #define CNTL_LCDBPP1 (0 << 1) | ||
53 | #define CNTL_LCDBPP2 (1 << 1) | ||
54 | #define CNTL_LCDBPP4 (2 << 1) | ||
55 | #define CNTL_LCDBPP8 (3 << 1) | ||
56 | #define CNTL_LCDBPP16 (4 << 1) | ||
57 | #define CNTL_LCDBPP24 (5 << 1) | ||
58 | #define CNTL_LCDBW (1 << 4) | ||
59 | #define CNTL_LCDTFT (1 << 5) | ||
60 | #define CNTL_LCDMONO8 (1 << 6) | ||
61 | #define CNTL_LCDDUAL (1 << 7) | ||
62 | #define CNTL_BGR (1 << 8) | ||
63 | #define CNTL_BEBO (1 << 9) | ||
64 | #define CNTL_BEPO (1 << 10) | ||
65 | #define CNTL_LCDPWR (1 << 11) | ||
66 | #define CNTL_LCDVCOMP(x) ((x) << 12) | ||
67 | #define CNTL_LDMAFIFOTIME (1 << 15) | ||
68 | #define CNTL_WATERMARK (1 << 16) | ||
69 | |||
70 | struct clcd_panel { | ||
71 | struct fb_videomode mode; | ||
72 | signed short width; /* width in mm */ | ||
73 | signed short height; /* height in mm */ | ||
74 | u32 tim2; | ||
75 | u32 tim3; | ||
76 | u32 cntl; | ||
77 | unsigned int bpp:8, | ||
78 | fixedtimings:1, | ||
79 | grayscale:1; | ||
80 | unsigned int connector; | ||
81 | }; | ||
82 | |||
83 | struct clcd_regs { | ||
84 | u32 tim0; | ||
85 | u32 tim1; | ||
86 | u32 tim2; | ||
87 | u32 tim3; | ||
88 | u32 cntl; | ||
89 | unsigned long pixclock; | ||
90 | }; | ||
91 | |||
92 | struct clcd_fb; | ||
93 | |||
94 | /* | ||
95 | * the board-type specific routines | ||
96 | */ | ||
97 | struct clcd_board { | ||
98 | const char *name; | ||
99 | |||
100 | /* | ||
101 | * Optional. Check whether the var structure is acceptable | ||
102 | * for this display. | ||
103 | */ | ||
104 | int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var); | ||
105 | |||
106 | /* | ||
107 | * Compulsary. Decode fb->fb.var into regs->*. In the case of | ||
108 | * fixed timing, set regs->* to the register values required. | ||
109 | */ | ||
110 | void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs); | ||
111 | |||
112 | /* | ||
113 | * Optional. Disable any extra display hardware. | ||
114 | */ | ||
115 | void (*disable)(struct clcd_fb *); | ||
116 | |||
117 | /* | ||
118 | * Optional. Enable any extra display hardware. | ||
119 | */ | ||
120 | void (*enable)(struct clcd_fb *); | ||
121 | |||
122 | /* | ||
123 | * Setup platform specific parts of CLCD driver | ||
124 | */ | ||
125 | int (*setup)(struct clcd_fb *); | ||
126 | |||
127 | /* | ||
128 | * mmap the framebuffer memory | ||
129 | */ | ||
130 | int (*mmap)(struct clcd_fb *, struct vm_area_struct *); | ||
131 | |||
132 | /* | ||
133 | * Remove platform specific parts of CLCD driver | ||
134 | */ | ||
135 | void (*remove)(struct clcd_fb *); | ||
136 | }; | ||
137 | |||
138 | struct amba_device; | ||
139 | struct clk; | ||
140 | |||
141 | /* this data structure describes each frame buffer device we find */ | ||
142 | struct clcd_fb { | ||
143 | struct fb_info fb; | ||
144 | struct amba_device *dev; | ||
145 | struct clk *clk; | ||
146 | struct clcd_panel *panel; | ||
147 | struct clcd_board *board; | ||
148 | void *board_data; | ||
149 | void __iomem *regs; | ||
150 | u32 clcd_cntl; | ||
151 | u32 cmap[16]; | ||
152 | }; | ||
153 | |||
154 | static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs) | ||
155 | { | ||
156 | u32 val, cpl; | ||
157 | |||
158 | /* | ||
159 | * Program the CLCD controller registers and start the CLCD | ||
160 | */ | ||
161 | val = ((fb->fb.var.xres / 16) - 1) << 2; | ||
162 | val |= (fb->fb.var.hsync_len - 1) << 8; | ||
163 | val |= (fb->fb.var.right_margin - 1) << 16; | ||
164 | val |= (fb->fb.var.left_margin - 1) << 24; | ||
165 | regs->tim0 = val; | ||
166 | |||
167 | val = fb->fb.var.yres; | ||
168 | if (fb->panel->cntl & CNTL_LCDDUAL) | ||
169 | val /= 2; | ||
170 | val -= 1; | ||
171 | val |= (fb->fb.var.vsync_len - 1) << 10; | ||
172 | val |= fb->fb.var.lower_margin << 16; | ||
173 | val |= fb->fb.var.upper_margin << 24; | ||
174 | regs->tim1 = val; | ||
175 | |||
176 | val = fb->panel->tim2; | ||
177 | val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS; | ||
178 | val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS; | ||
179 | |||
180 | cpl = fb->fb.var.xres_virtual; | ||
181 | if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */ | ||
182 | /* / 1 */; | ||
183 | else if (!fb->fb.var.grayscale) /* STN color */ | ||
184 | cpl = cpl * 8 / 3; | ||
185 | else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */ | ||
186 | cpl /= 8; | ||
187 | else /* STN monochrome, 4bit */ | ||
188 | cpl /= 4; | ||
189 | |||
190 | regs->tim2 = val | ((cpl - 1) << 16); | ||
191 | |||
192 | regs->tim3 = fb->panel->tim3; | ||
193 | |||
194 | val = fb->panel->cntl; | ||
195 | if (fb->fb.var.grayscale) | ||
196 | val |= CNTL_LCDBW; | ||
197 | |||
198 | switch (fb->fb.var.bits_per_pixel) { | ||
199 | case 1: | ||
200 | val |= CNTL_LCDBPP1; | ||
201 | break; | ||
202 | case 2: | ||
203 | val |= CNTL_LCDBPP2; | ||
204 | break; | ||
205 | case 4: | ||
206 | val |= CNTL_LCDBPP4; | ||
207 | break; | ||
208 | case 8: | ||
209 | val |= CNTL_LCDBPP8; | ||
210 | break; | ||
211 | case 16: | ||
212 | val |= CNTL_LCDBPP16; | ||
213 | break; | ||
214 | case 32: | ||
215 | val |= CNTL_LCDBPP24; | ||
216 | break; | ||
217 | } | ||
218 | |||
219 | regs->cntl = val; | ||
220 | regs->pixclock = fb->fb.var.pixclock; | ||
221 | } | ||
222 | |||
223 | static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var) | ||
224 | { | ||
225 | var->xres_virtual = var->xres = (var->xres + 15) & ~15; | ||
226 | var->yres_virtual = var->yres = (var->yres + 1) & ~1; | ||
227 | |||
228 | #define CHECK(e,l,h) (var->e < l || var->e > h) | ||
229 | if (CHECK(right_margin, (5+1), 256) || /* back porch */ | ||
230 | CHECK(left_margin, (5+1), 256) || /* front porch */ | ||
231 | CHECK(hsync_len, (5+1), 256) || | ||
232 | var->xres > 4096 || | ||
233 | var->lower_margin > 255 || /* back porch */ | ||
234 | var->upper_margin > 255 || /* front porch */ | ||
235 | var->vsync_len > 32 || | ||
236 | var->yres > 1024) | ||
237 | return -EINVAL; | ||
238 | #undef CHECK | ||
239 | |||
240 | /* single panel mode: PCD = max(PCD, 1) */ | ||
241 | /* dual panel mode: PCD = max(PCD, 5) */ | ||
242 | |||
243 | /* | ||
244 | * You can't change the grayscale setting, and | ||
245 | * we can only do non-interlaced video. | ||
246 | */ | ||
247 | if (var->grayscale != fb->fb.var.grayscale || | ||
248 | (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) | ||
249 | return -EINVAL; | ||
250 | |||
251 | #define CHECK(e) (var->e != fb->fb.var.e) | ||
252 | if (fb->panel->fixedtimings && | ||
253 | (CHECK(xres) || | ||
254 | CHECK(yres) || | ||
255 | CHECK(bits_per_pixel) || | ||
256 | CHECK(pixclock) || | ||
257 | CHECK(left_margin) || | ||
258 | CHECK(right_margin) || | ||
259 | CHECK(upper_margin) || | ||
260 | CHECK(lower_margin) || | ||
261 | CHECK(hsync_len) || | ||
262 | CHECK(vsync_len) || | ||
263 | CHECK(sync))) | ||
264 | return -EINVAL; | ||
265 | #undef CHECK | ||
266 | |||
267 | var->nonstd = 0; | ||
268 | var->accel_flags = 0; | ||
269 | |||
270 | return 0; | ||
271 | } | ||
diff --git a/include/asm-arm/hardware/amba_kmi.h b/include/asm-arm/hardware/amba_kmi.h deleted file mode 100644 index a39e5be751b3..000000000000 --- a/include/asm-arm/hardware/amba_kmi.h +++ /dev/null | |||
@@ -1,92 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/hardware/amba_kmi.h | ||
3 | * | ||
4 | * Internal header file for AMBA KMI ports | ||
5 | * | ||
6 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | * | ||
22 | * | ||
23 | * --------------------------------------------------------------------------- | ||
24 | * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical | ||
25 | * Reference Manual - ARM DDI 0143B - see http://www.arm.com/ | ||
26 | * --------------------------------------------------------------------------- | ||
27 | */ | ||
28 | #ifndef ASM_ARM_HARDWARE_AMBA_KMI_H | ||
29 | #define ASM_ARM_HARDWARE_AMBA_KMI_H | ||
30 | |||
31 | /* | ||
32 | * KMI control register: | ||
33 | * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode | ||
34 | * KMICR_RXINTREN 1 = enable RX interrupts | ||
35 | * KMICR_TXINTREN 1 = enable TX interrupts | ||
36 | * KMICR_EN 1 = enable KMI | ||
37 | * KMICR_FD 1 = force KMI data low | ||
38 | * KMICR_FC 1 = force KMI clock low | ||
39 | */ | ||
40 | #define KMICR (KMI_BASE + 0x00) | ||
41 | #define KMICR_TYPE (1 << 5) | ||
42 | #define KMICR_RXINTREN (1 << 4) | ||
43 | #define KMICR_TXINTREN (1 << 3) | ||
44 | #define KMICR_EN (1 << 2) | ||
45 | #define KMICR_FD (1 << 1) | ||
46 | #define KMICR_FC (1 << 0) | ||
47 | |||
48 | /* | ||
49 | * KMI status register: | ||
50 | * KMISTAT_TXEMPTY 1 = transmitter register empty | ||
51 | * KMISTAT_TXBUSY 1 = currently sending data | ||
52 | * KMISTAT_RXFULL 1 = receiver register ready to be read | ||
53 | * KMISTAT_RXBUSY 1 = currently receiving data | ||
54 | * KMISTAT_RXPARITY parity of last databyte received | ||
55 | * KMISTAT_IC current level of KMI clock input | ||
56 | * KMISTAT_ID current level of KMI data input | ||
57 | */ | ||
58 | #define KMISTAT (KMI_BASE + 0x04) | ||
59 | #define KMISTAT_TXEMPTY (1 << 6) | ||
60 | #define KMISTAT_TXBUSY (1 << 5) | ||
61 | #define KMISTAT_RXFULL (1 << 4) | ||
62 | #define KMISTAT_RXBUSY (1 << 3) | ||
63 | #define KMISTAT_RXPARITY (1 << 2) | ||
64 | #define KMISTAT_IC (1 << 1) | ||
65 | #define KMISTAT_ID (1 << 0) | ||
66 | |||
67 | /* | ||
68 | * KMI data register | ||
69 | */ | ||
70 | #define KMIDATA (KMI_BASE + 0x08) | ||
71 | |||
72 | /* | ||
73 | * KMI clock divisor: to generate 8MHz internal clock | ||
74 | * div = (ref / 8MHz) - 1; 0 <= div <= 15 | ||
75 | */ | ||
76 | #define KMICLKDIV (KMI_BASE + 0x0c) | ||
77 | |||
78 | /* | ||
79 | * KMI interrupt register: | ||
80 | * KMIIR_TXINTR 1 = transmit interrupt asserted | ||
81 | * KMIIR_RXINTR 1 = receive interrupt asserted | ||
82 | */ | ||
83 | #define KMIIR (KMI_BASE + 0x10) | ||
84 | #define KMIIR_TXINTR (1 << 1) | ||
85 | #define KMIIR_RXINTR (1 << 0) | ||
86 | |||
87 | /* | ||
88 | * The size of the KMI primecell | ||
89 | */ | ||
90 | #define KMI_SIZE (0x100) | ||
91 | |||
92 | #endif | ||
diff --git a/include/asm-arm/hardware/amba_serial.h b/include/asm-arm/hardware/amba_serial.h deleted file mode 100644 index dc726ffccebd..000000000000 --- a/include/asm-arm/hardware/amba_serial.h +++ /dev/null | |||
@@ -1,161 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/hardware/serial_amba.h | ||
3 | * | ||
4 | * Internal header file for AMBA serial ports | ||
5 | * | ||
6 | * Copyright (C) ARM Limited | ||
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | */ | ||
23 | #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H | ||
24 | #define ASM_ARM_HARDWARE_SERIAL_AMBA_H | ||
25 | |||
26 | /* ------------------------------------------------------------------------------- | ||
27 | * From AMBA UART (PL010) Block Specification | ||
28 | * ------------------------------------------------------------------------------- | ||
29 | * UART Register Offsets. | ||
30 | */ | ||
31 | #define UART01x_DR 0x00 /* Data read or written from the interface. */ | ||
32 | #define UART01x_RSR 0x04 /* Receive status register (Read). */ | ||
33 | #define UART01x_ECR 0x04 /* Error clear register (Write). */ | ||
34 | #define UART010_LCRH 0x08 /* Line control register, high byte. */ | ||
35 | #define UART010_LCRM 0x0C /* Line control register, middle byte. */ | ||
36 | #define UART010_LCRL 0x10 /* Line control register, low byte. */ | ||
37 | #define UART010_CR 0x14 /* Control register. */ | ||
38 | #define UART01x_FR 0x18 /* Flag register (Read only). */ | ||
39 | #define UART010_IIR 0x1C /* Interrupt indentification register (Read). */ | ||
40 | #define UART010_ICR 0x1C /* Interrupt clear register (Write). */ | ||
41 | #define UART01x_ILPR 0x20 /* IrDA low power counter register. */ | ||
42 | #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */ | ||
43 | #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */ | ||
44 | #define UART011_LCRH 0x2c /* Line control register. */ | ||
45 | #define UART011_CR 0x30 /* Control register. */ | ||
46 | #define UART011_IFLS 0x34 /* Interrupt fifo level select. */ | ||
47 | #define UART011_IMSC 0x38 /* Interrupt mask. */ | ||
48 | #define UART011_RIS 0x3c /* Raw interrupt status. */ | ||
49 | #define UART011_MIS 0x40 /* Masked interrupt status. */ | ||
50 | #define UART011_ICR 0x44 /* Interrupt clear register. */ | ||
51 | #define UART011_DMACR 0x48 /* DMA control register. */ | ||
52 | |||
53 | #define UART011_DR_OE (1 << 11) | ||
54 | #define UART011_DR_BE (1 << 10) | ||
55 | #define UART011_DR_PE (1 << 9) | ||
56 | #define UART011_DR_FE (1 << 8) | ||
57 | |||
58 | #define UART01x_RSR_OE 0x08 | ||
59 | #define UART01x_RSR_BE 0x04 | ||
60 | #define UART01x_RSR_PE 0x02 | ||
61 | #define UART01x_RSR_FE 0x01 | ||
62 | |||
63 | #define UART011_FR_RI 0x100 | ||
64 | #define UART011_FR_TXFE 0x080 | ||
65 | #define UART011_FR_RXFF 0x040 | ||
66 | #define UART01x_FR_TXFF 0x020 | ||
67 | #define UART01x_FR_RXFE 0x010 | ||
68 | #define UART01x_FR_BUSY 0x008 | ||
69 | #define UART01x_FR_DCD 0x004 | ||
70 | #define UART01x_FR_DSR 0x002 | ||
71 | #define UART01x_FR_CTS 0x001 | ||
72 | #define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY) | ||
73 | |||
74 | #define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */ | ||
75 | #define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */ | ||
76 | #define UART011_CR_OUT2 0x2000 /* OUT2 */ | ||
77 | #define UART011_CR_OUT1 0x1000 /* OUT1 */ | ||
78 | #define UART011_CR_RTS 0x0800 /* RTS */ | ||
79 | #define UART011_CR_DTR 0x0400 /* DTR */ | ||
80 | #define UART011_CR_RXE 0x0200 /* receive enable */ | ||
81 | #define UART011_CR_TXE 0x0100 /* transmit enable */ | ||
82 | #define UART011_CR_LBE 0x0080 /* loopback enable */ | ||
83 | #define UART010_CR_RTIE 0x0040 | ||
84 | #define UART010_CR_TIE 0x0020 | ||
85 | #define UART010_CR_RIE 0x0010 | ||
86 | #define UART010_CR_MSIE 0x0008 | ||
87 | #define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */ | ||
88 | #define UART01x_CR_SIREN 0x0002 /* SIR enable */ | ||
89 | #define UART01x_CR_UARTEN 0x0001 /* UART enable */ | ||
90 | |||
91 | #define UART011_LCRH_SPS 0x80 | ||
92 | #define UART01x_LCRH_WLEN_8 0x60 | ||
93 | #define UART01x_LCRH_WLEN_7 0x40 | ||
94 | #define UART01x_LCRH_WLEN_6 0x20 | ||
95 | #define UART01x_LCRH_WLEN_5 0x00 | ||
96 | #define UART01x_LCRH_FEN 0x10 | ||
97 | #define UART01x_LCRH_STP2 0x08 | ||
98 | #define UART01x_LCRH_EPS 0x04 | ||
99 | #define UART01x_LCRH_PEN 0x02 | ||
100 | #define UART01x_LCRH_BRK 0x01 | ||
101 | |||
102 | #define UART010_IIR_RTIS 0x08 | ||
103 | #define UART010_IIR_TIS 0x04 | ||
104 | #define UART010_IIR_RIS 0x02 | ||
105 | #define UART010_IIR_MIS 0x01 | ||
106 | |||
107 | #define UART011_IFLS_RX1_8 (0 << 3) | ||
108 | #define UART011_IFLS_RX2_8 (1 << 3) | ||
109 | #define UART011_IFLS_RX4_8 (2 << 3) | ||
110 | #define UART011_IFLS_RX6_8 (3 << 3) | ||
111 | #define UART011_IFLS_RX7_8 (4 << 3) | ||
112 | #define UART011_IFLS_TX1_8 (0 << 0) | ||
113 | #define UART011_IFLS_TX2_8 (1 << 0) | ||
114 | #define UART011_IFLS_TX4_8 (2 << 0) | ||
115 | #define UART011_IFLS_TX6_8 (3 << 0) | ||
116 | #define UART011_IFLS_TX7_8 (4 << 0) | ||
117 | |||
118 | #define UART011_OEIM (1 << 10) /* overrun error interrupt mask */ | ||
119 | #define UART011_BEIM (1 << 9) /* break error interrupt mask */ | ||
120 | #define UART011_PEIM (1 << 8) /* parity error interrupt mask */ | ||
121 | #define UART011_FEIM (1 << 7) /* framing error interrupt mask */ | ||
122 | #define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */ | ||
123 | #define UART011_TXIM (1 << 5) /* transmit interrupt mask */ | ||
124 | #define UART011_RXIM (1 << 4) /* receive interrupt mask */ | ||
125 | #define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */ | ||
126 | #define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */ | ||
127 | #define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */ | ||
128 | #define UART011_RIMIM (1 << 0) /* RI interrupt mask */ | ||
129 | |||
130 | #define UART011_OEIS (1 << 10) /* overrun error interrupt status */ | ||
131 | #define UART011_BEIS (1 << 9) /* break error interrupt status */ | ||
132 | #define UART011_PEIS (1 << 8) /* parity error interrupt status */ | ||
133 | #define UART011_FEIS (1 << 7) /* framing error interrupt status */ | ||
134 | #define UART011_RTIS (1 << 6) /* receive timeout interrupt status */ | ||
135 | #define UART011_TXIS (1 << 5) /* transmit interrupt status */ | ||
136 | #define UART011_RXIS (1 << 4) /* receive interrupt status */ | ||
137 | #define UART011_DSRMIS (1 << 3) /* DSR interrupt status */ | ||
138 | #define UART011_DCDMIS (1 << 2) /* DCD interrupt status */ | ||
139 | #define UART011_CTSMIS (1 << 1) /* CTS interrupt status */ | ||
140 | #define UART011_RIMIS (1 << 0) /* RI interrupt status */ | ||
141 | |||
142 | #define UART011_OEIC (1 << 10) /* overrun error interrupt clear */ | ||
143 | #define UART011_BEIC (1 << 9) /* break error interrupt clear */ | ||
144 | #define UART011_PEIC (1 << 8) /* parity error interrupt clear */ | ||
145 | #define UART011_FEIC (1 << 7) /* framing error interrupt clear */ | ||
146 | #define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */ | ||
147 | #define UART011_TXIC (1 << 5) /* transmit interrupt clear */ | ||
148 | #define UART011_RXIC (1 << 4) /* receive interrupt clear */ | ||
149 | #define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */ | ||
150 | #define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */ | ||
151 | #define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */ | ||
152 | #define UART011_RIMIC (1 << 0) /* RI interrupt clear */ | ||
153 | |||
154 | #define UART011_DMAONERR (1 << 2) /* disable dma on error */ | ||
155 | #define UART011_TXDMAE (1 << 1) /* enable transmit dma */ | ||
156 | #define UART011_RXDMAE (1 << 0) /* enable receive dma */ | ||
157 | |||
158 | #define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE) | ||
159 | #define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS) | ||
160 | |||
161 | #endif | ||