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-rw-r--r--include/asm-arm/hardware/iop3xx.h312
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diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
deleted file mode 100644
index 18f6937f5010..000000000000
--- a/include/asm-arm/hardware/iop3xx.h
+++ /dev/null
@@ -1,312 +0,0 @@
1/*
2 * include/asm-arm/hardware/iop3xx.h
3 *
4 * Intel IOP32X and IOP33X register definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __IOP3XX_H
16#define __IOP3XX_H
17
18/*
19 * IOP3XX GPIO handling
20 */
21#define GPIO_IN 0
22#define GPIO_OUT 1
23#define GPIO_LOW 0
24#define GPIO_HIGH 1
25#define IOP3XX_GPIO_LINE(x) (x)
26
27#ifndef __ASSEMBLY__
28extern void gpio_line_config(int line, int direction);
29extern int gpio_line_get(int line);
30extern void gpio_line_set(int line, int value);
31extern int init_atu;
32extern int iop3xx_get_init_atu(void);
33#endif
34
35
36/*
37 * IOP3XX processor registers
38 */
39#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
40#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
41#define IOP3XX_PERIPHERAL_SIZE 0x00002000
42#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
43 IOP3XX_PERIPHERAL_SIZE - 1)
44#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
45 IOP3XX_PERIPHERAL_SIZE - 1)
46#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
47 (IOP3XX_PERIPHERAL_PHYS_BASE\
48 - IOP3XX_PERIPHERAL_VIRT_BASE))
49#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
50
51/* Address Translation Unit */
52#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
53#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
54#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
55#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
56#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
57#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
58#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
59#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
60#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
61#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
62#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
63#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
64#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
65#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
66#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
67#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
68#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
69#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
70#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
71#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
72#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
73#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
74#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
75#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
76#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
77#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
78#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
79#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
80#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
81#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
82#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
83#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
84#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
85#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
86#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
87#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
88#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
89#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
90#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
91#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
92#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
93#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
94#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
95#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
96#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
97#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
98#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
99#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
100#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
101#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
102#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
103#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
104#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
105#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
106#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
107#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
108#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
109#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
110#define IOP3XX_ATUCR_OUT_EN (1 << 1)
111
112#define IOP3XX_INIT_ATU_DEFAULT 0
113#define IOP3XX_INIT_ATU_DISABLE -1
114#define IOP3XX_INIT_ATU_ENABLE 1
115
116/* Messaging Unit */
117#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
118#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
119#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
120#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
121#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
122#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
123#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
124#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
125#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
126#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
127#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
128#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
129#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
130#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
131#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
132#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
133#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
134#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
135#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
136#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
137#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
138
139/* DMA Controller */
140#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
141 (0x400 + (chan << 6)))
142#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
143
144/* Peripheral bus interface */
145#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
146#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
147#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
148#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
149#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
150#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
151#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
152#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
153#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
154#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
155#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
156#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
157#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
158#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
159#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
160#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
161#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
162
163/* Peripheral performance monitoring unit */
164#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
165#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
166#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
167#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
168/* PERCR0 DOESN'T EXIST - index from 1! */
169#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
170
171/* General Purpose I/O */
172#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000)
173#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
174#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
175
176/* Timers */
177#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
178#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
179#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
180#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
181#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
182#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
183#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
184#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
185#define IOP_TMR_EN 0x02
186#define IOP_TMR_RELOAD 0x04
187#define IOP_TMR_PRIVILEGED 0x08
188#define IOP_TMR_RATIO_1_1 0x00
189
190/* Watchdog timer definitions */
191#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
192#define IOP_WDTCR_EN 0xe1e1e1e1
193/* iop3xx does not support stopping the watchdog, so we just re-arm */
194#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
195#define IOP_WDTCR_DIS (IOP_WDTCR_EN)
196
197/* Application accelerator unit */
198#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
199#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
200
201/* I2C bus interface unit */
202#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
203#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
204#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
205#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
206#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
207#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
208#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
209#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
210#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
211#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
212
213
214/*
215 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
216 */
217#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
218
219#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
220#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
221#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
222#define IOP3XX_PCI_LOWER_IO_BA 0x90000000
223#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
224 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
225#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
226 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
227#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\
228 IOP3XX_PCI_LOWER_IO_PA) +\
229 IOP3XX_PCI_LOWER_IO_VA)
230
231
232#ifndef __ASSEMBLY__
233void iop3xx_map_io(void);
234void iop_init_cp6_handler(void);
235void iop_init_time(unsigned long tickrate);
236unsigned long iop_gettimeoffset(void);
237
238static inline void write_tmr0(u32 val)
239{
240 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
241}
242
243static inline void write_tmr1(u32 val)
244{
245 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
246}
247
248static inline u32 read_tcr0(void)
249{
250 u32 val;
251 asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
252 return val;
253}
254
255static inline u32 read_tcr1(void)
256{
257 u32 val;
258 asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
259 return val;
260}
261
262static inline void write_trr0(u32 val)
263{
264 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
265}
266
267static inline void write_trr1(u32 val)
268{
269 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
270}
271
272static inline void write_tisr(u32 val)
273{
274 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
275}
276
277static inline u32 read_wdtcr(void)
278{
279 u32 val;
280 asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
281 return val;
282}
283static inline void write_wdtcr(u32 val)
284{
285 asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
286}
287
288extern unsigned long get_iop_tick_rate(void);
289
290/* only iop13xx has these registers, we define these to present a
291 * common register interface for the iop_wdt driver.
292 */
293#define IOP_RCSR_WDT (0)
294static inline u32 read_rcsr(void)
295{
296 return 0;
297}
298static inline void write_wdtsr(u32 val)
299{
300 do { } while (0);
301}
302
303extern struct platform_device iop3xx_dma_0_channel;
304extern struct platform_device iop3xx_dma_1_channel;
305extern struct platform_device iop3xx_aau_channel;
306extern struct platform_device iop3xx_i2c0_device;
307extern struct platform_device iop3xx_i2c1_device;
308
309#endif
310
311
312#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 09:32:55 -0500