aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm/cacheflush.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm/cacheflush.h')
-rw-r--r--include/asm-arm/cacheflush.h17
1 files changed, 13 insertions, 4 deletions
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 03cf1ee977b7..e68a1cbcc852 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -459,15 +459,19 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
459#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0) 459#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
460 460
461#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT) 461#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
462 462/*
463 * VIVT caches only
464 */
463#define cache_is_vivt() 1 465#define cache_is_vivt() 1
464#define cache_is_vipt() 0 466#define cache_is_vipt() 0
465#define cache_is_vipt_nonaliasing() 0 467#define cache_is_vipt_nonaliasing() 0
466#define cache_is_vipt_aliasing() 0 468#define cache_is_vipt_aliasing() 0
467#define icache_is_vivt_asid_tagged() 0 469#define icache_is_vivt_asid_tagged() 0
468 470
469#elif defined(CONFIG_CPU_CACHE_VIPT) 471#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
470 472/*
473 * VIPT caches only
474 */
471#define cache_is_vivt() 0 475#define cache_is_vivt() 0
472#define cache_is_vipt() 1 476#define cache_is_vipt() 1
473#define cache_is_vipt_nonaliasing() \ 477#define cache_is_vipt_nonaliasing() \
@@ -489,7 +493,12 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
489 }) 493 })
490 494
491#else 495#else
492 496/*
497 * VIVT or VIPT caches. Note that this is unreliable since ARM926
498 * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
499 * There's no way to tell from the CacheType register what type (!)
500 * the cache is.
501 */
493#define cache_is_vivt() \ 502#define cache_is_vivt() \
494 ({ \ 503 ({ \
495 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ 504 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \