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-rw-r--r--include/asm-arm/assembler.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index fce832820825..911393b2c6f0 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -56,6 +56,21 @@
56#endif 56#endif
57 57
58/* 58/*
59 * This can be used to enable code to cacheline align the destination
60 * pointer when bulk writing to memory. Experiments on StrongARM and
61 * XScale didn't show this a worthwhile thing to do when the cache is not
62 * set to write-allocate (this would need further testing on XScale when WA
63 * is used).
64 *
65 * On Feroceon there is much to gain however, regardless of cache mode.
66 */
67#ifdef CONFIG_CPU_FEROCEON
68#define CALGN(code...) code
69#else
70#define CALGN(code...)
71#endif
72
73/*
59 * Enable and disable interrupts 74 * Enable and disable interrupts
60 */ 75 */
61#if __LINUX_ARM_ARCH__ >= 6 76#if __LINUX_ARM_ARCH__ >= 6