diff options
Diffstat (limited to 'include/asm-arm/arch-s3c2410')
20 files changed, 70 insertions, 1404 deletions
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S index 93064860e0e5..9c8cd9abb82b 100644 --- a/include/asm-arm/arch-s3c2410/debug-macro.S +++ b/include/asm-arm/arch-s3c2410/debug-macro.S | |||
@@ -13,32 +13,23 @@ | |||
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include <asm/arch/map.h> | 15 | #include <asm/arch/map.h> |
16 | #include <asm/arch/regs-serial.h> | ||
17 | #include <asm/arch/regs-gpio.h> | 16 | #include <asm/arch/regs-gpio.h> |
17 | #include <asm/plat-s3c/regs-serial.h> | ||
18 | 18 | ||
19 | #define S3C2410_UART1_OFF (0x4000) | 19 | #define S3C2410_UART1_OFF (0x4000) |
20 | #define SHIFT_2440TXF (14-9) | 20 | #define SHIFT_2440TXF (14-9) |
21 | 21 | ||
22 | .macro addruart, rx | 22 | .macro addruart, rx |
23 | mrc p15, 0, \rx, c1, c0 | 23 | mrc p15, 0, \rx, c1, c0 |
24 | tst \rx, #1 | 24 | tst \rx, #1 |
25 | ldreq \rx, = S3C24XX_PA_UART | 25 | ldreq \rx, = S3C24XX_PA_UART |
26 | ldrne \rx, = S3C24XX_VA_UART | 26 | ldrne \rx, = S3C24XX_VA_UART |
27 | #if CONFIG_DEBUG_S3C2410_UART != 0 | 27 | #if CONFIG_DEBUG_S3C_UART != 0 |
28 | add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART) | 28 | add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) |
29 | #endif | 29 | #endif |
30 | .endm | 30 | .endm |
31 | 31 | ||
32 | .macro senduart,rd,rx | 32 | .macro fifo_full_s3c24xx rd, rx |
33 | strb \rd, [\rx, # S3C2410_UTXH ] | ||
34 | .endm | ||
35 | |||
36 | .macro busyuart, rd, rx | ||
37 | ldr \rd, [ \rx, # S3C2410_UFCON ] | ||
38 | tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? | ||
39 | beq 1001f @ | ||
40 | @ FIFO enabled... | ||
41 | 1003: | ||
42 | @ check for arm920 vs arm926. currently assume all arm926 | 33 | @ check for arm920 vs arm926. currently assume all arm926 |
43 | @ devices have an 64 byte FIFO identical to the s3c2440 | 34 | @ devices have an 64 byte FIFO identical to the s3c2440 |
44 | mrc p15, 0, \rd, c0, c0 | 35 | mrc p15, 0, \rd, c0, c0 |
@@ -57,25 +48,22 @@ | |||
57 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | 48 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] |
58 | moveq \rd, \rd, lsr #SHIFT_2440TXF | 49 | moveq \rd, \rd, lsr #SHIFT_2440TXF |
59 | tst \rd, #S3C2410_UFSTAT_TXFULL | 50 | tst \rd, #S3C2410_UFSTAT_TXFULL |
60 | bne 1003b | 51 | .endm |
61 | b 1002f | ||
62 | |||
63 | 1001: | ||
64 | @ busy waiting for non fifo | ||
65 | ldr \rd, [ \rx, # S3C2410_UTRSTAT ] | ||
66 | tst \rd, #S3C2410_UTRSTAT_TXFE | ||
67 | beq 1001b | ||
68 | 52 | ||
69 | 1002: @ exit busyuart | 53 | .macro fifo_full_s3c2410 rd, rx |
70 | .endm | 54 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] |
55 | tst \rd, #S3C2410_UFSTAT_TXFULL | ||
56 | .endm | ||
71 | 57 | ||
72 | .macro waituart,rd,rx | 58 | /* fifo level reading */ |
73 | 59 | ||
74 | ldr \rd, [ \rx, # S3C2410_UFCON ] | 60 | .macro fifo_level_s3c24xx rd, rx |
75 | tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? | 61 | @ check for arm920 vs arm926. currently assume all arm926 |
76 | beq 1001f @ | 62 | @ devices have an 64 byte FIFO identical to the s3c2440 |
77 | @ FIFO enabled... | 63 | mrc p15, 0, \rd, c0, c0 |
78 | 1003: | 64 | and \rd, \rd, #0xff0 |
65 | teq \rd, #0x260 | ||
66 | beq 10000f | ||
79 | mrc p15, 0, \rd, c1, c0 | 67 | mrc p15, 0, \rd, c1, c0 |
80 | tst \rd, #1 | 68 | tst \rd, #1 |
81 | addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) | 69 | addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) |
@@ -85,18 +73,32 @@ | |||
85 | and \rd, \rd, #0x00ff0000 | 73 | and \rd, \rd, #0x00ff0000 |
86 | teq \rd, #0x00440000 @ is it 2440? | 74 | teq \rd, #0x00440000 @ is it 2440? |
87 | 75 | ||
76 | 10000: | ||
88 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | 77 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] |
89 | andne \rd, \rd, #S3C2410_UFSTAT_TXMASK | 78 | andne \rd, \rd, #S3C2410_UFSTAT_TXMASK |
90 | andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK | 79 | andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK |
91 | teq \rd, #0 | 80 | .endm |
92 | bne 1003b | 81 | |
93 | b 1002f | 82 | .macro fifo_level_s3c2410 rd, rx |
83 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | ||
84 | and \rd, \rd, #S3C2410_UFSTAT_TXMASK | ||
85 | .endm | ||
86 | |||
87 | /* Select the correct implementation depending on the configuration. The | ||
88 | * S3C2440 will get selected by default, as these are the most widely | ||
89 | * used variants of these | ||
90 | */ | ||
91 | |||
92 | #if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) | ||
93 | #define fifo_full fifo_full_s3c2410 | ||
94 | #define fifo_level fifo_level_s3c2410 | ||
95 | #warning 2410only | ||
96 | #elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) | ||
97 | #define fifo_full fifo_full_s3c24xx | ||
98 | #define fifo_level fifo_level_s3c24xx | ||
99 | #warning generic | ||
100 | #endif | ||
94 | 101 | ||
95 | 1001: | 102 | /* include the reset of the code which will do the work */ |
96 | @ idle waiting for non fifo | ||
97 | ldr \rd, [ \rx, # S3C2410_UTRSTAT ] | ||
98 | tst \rd, #S3C2410_UTRSTAT_TXFE | ||
99 | beq 1001b | ||
100 | 103 | ||
101 | 1002: @ exit busyuart | 104 | #include <asm/plat-s3c/debug-macro.S> |
102 | .endm | ||
diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/arch-s3c2410/iic.h deleted file mode 100644 index 71211c8b5384..000000000000 --- a/include/asm-arm/arch-s3c2410/iic.h +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/iic.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - I2C Controller platfrom_device info | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_IIC_H | ||
14 | #define __ASM_ARCH_IIC_H __FILE__ | ||
15 | |||
16 | #define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */ | ||
17 | |||
18 | /* Notes: | ||
19 | * 1) All frequencies are expressed in Hz | ||
20 | * 2) A value of zero is `do not care` | ||
21 | */ | ||
22 | |||
23 | struct s3c2410_platform_i2c { | ||
24 | unsigned int flags; | ||
25 | unsigned int slave_addr; /* slave address for controller */ | ||
26 | unsigned long bus_freq; /* standard bus frequency */ | ||
27 | unsigned long max_freq; /* max frequency for the bus */ | ||
28 | unsigned long min_freq; /* min frequency for the bus */ | ||
29 | unsigned int sda_delay; /* pclks (s3c2440 only) */ | ||
30 | }; | ||
31 | |||
32 | #endif /* __ASM_ARCH_IIC_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h index 19e77f038042..b33ed3b05ef5 100644 --- a/include/asm-arm/arch-s3c2410/map.h +++ b/include/asm-arm/arch-s3c2410/map.h | |||
@@ -13,58 +13,36 @@ | |||
13 | #ifndef __ASM_ARCH_MAP_H | 13 | #ifndef __ASM_ARCH_MAP_H |
14 | #define __ASM_ARCH_MAP_H | 14 | #define __ASM_ARCH_MAP_H |
15 | 15 | ||
16 | /* we have a bit of a tight squeeze to fit all our registers from | 16 | #include <asm/plat-s3c/map.h> |
17 | * 0xF00000000 upwards, since we use all of the nGCS space in some | ||
18 | * capacity, and also need to fit the S3C2410 registers in as well... | ||
19 | * | ||
20 | * we try to ensure stuff like the IRQ registers are available for | ||
21 | * an single MOVS instruction (ie, only 8 bits of set data) | ||
22 | * | ||
23 | * Note, we are trying to remove some of these from the implementation | ||
24 | * as they are only useful to certain drivers... | ||
25 | */ | ||
26 | |||
27 | #ifndef __ASSEMBLY__ | ||
28 | #define S3C2410_ADDR(x) ((void __iomem __force *)0xF0000000 + (x)) | ||
29 | #else | ||
30 | #define S3C2410_ADDR(x) (0xF0000000 + (x)) | ||
31 | #endif | ||
32 | 17 | ||
33 | #define S3C2400_ADDR(x) S3C2410_ADDR(x) | 18 | #define S3C2410_ADDR(x) S3C_ADDR(x) |
34 | 19 | ||
35 | /* interrupt controller is the first thing we put in, to make | 20 | /* interrupt controller is the first thing we put in, to make |
36 | * the assembly code for the irq detection easier | 21 | * the assembly code for the irq detection easier |
37 | */ | 22 | */ |
38 | #define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000) | 23 | #define S3C24XX_VA_IRQ S3C_VA_IRQ |
39 | #define S3C2400_PA_IRQ (0x14400000) | ||
40 | #define S3C2410_PA_IRQ (0x4A000000) | 24 | #define S3C2410_PA_IRQ (0x4A000000) |
41 | #define S3C24XX_SZ_IRQ SZ_1M | 25 | #define S3C24XX_SZ_IRQ SZ_1M |
42 | 26 | ||
43 | /* memory controller registers */ | 27 | /* memory controller registers */ |
44 | #define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000) | 28 | #define S3C24XX_VA_MEMCTRL S3C_VA_MEM |
45 | #define S3C2400_PA_MEMCTRL (0x14000000) | ||
46 | #define S3C2410_PA_MEMCTRL (0x48000000) | 29 | #define S3C2410_PA_MEMCTRL (0x48000000) |
47 | #define S3C24XX_SZ_MEMCTRL SZ_1M | 30 | #define S3C24XX_SZ_MEMCTRL SZ_1M |
48 | 31 | ||
49 | /* USB host controller */ | 32 | /* USB host controller */ |
50 | #define S3C2400_PA_USBHOST (0x14200000) | ||
51 | #define S3C2410_PA_USBHOST (0x49000000) | 33 | #define S3C2410_PA_USBHOST (0x49000000) |
52 | #define S3C24XX_SZ_USBHOST SZ_1M | 34 | #define S3C24XX_SZ_USBHOST SZ_1M |
53 | 35 | ||
54 | /* DMA controller */ | 36 | /* DMA controller */ |
55 | #define S3C2400_PA_DMA (0x14600000) | ||
56 | #define S3C2410_PA_DMA (0x4B000000) | 37 | #define S3C2410_PA_DMA (0x4B000000) |
57 | #define S3C24XX_SZ_DMA SZ_1M | 38 | #define S3C24XX_SZ_DMA SZ_1M |
58 | 39 | ||
59 | /* Clock and Power management */ | 40 | /* Clock and Power management */ |
60 | #define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000) | 41 | #define S3C24XX_VA_CLKPWR S3C_VA_SYS |
61 | #define S3C2400_PA_CLKPWR (0x14800000) | ||
62 | #define S3C2410_PA_CLKPWR (0x4C000000) | 42 | #define S3C2410_PA_CLKPWR (0x4C000000) |
63 | #define S3C24XX_SZ_CLKPWR SZ_1M | 43 | #define S3C24XX_SZ_CLKPWR SZ_1M |
64 | 44 | ||
65 | /* LCD controller */ | 45 | /* LCD controller */ |
66 | #define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000) | ||
67 | #define S3C2400_PA_LCD (0x14A00000) | ||
68 | #define S3C2410_PA_LCD (0x4D000000) | 46 | #define S3C2410_PA_LCD (0x4D000000) |
69 | #define S3C24XX_SZ_LCD SZ_1M | 47 | #define S3C24XX_SZ_LCD SZ_1M |
70 | 48 | ||
@@ -72,41 +50,30 @@ | |||
72 | #define S3C2410_PA_NAND (0x4E000000) | 50 | #define S3C2410_PA_NAND (0x4E000000) |
73 | #define S3C24XX_SZ_NAND SZ_1M | 51 | #define S3C24XX_SZ_NAND SZ_1M |
74 | 52 | ||
75 | /* MMC controller - available on the S3C2400 */ | ||
76 | #define S3C2400_PA_MMC (0x15A00000) | ||
77 | #define S3C2400_SZ_MMC SZ_1M | ||
78 | |||
79 | /* UARTs */ | 53 | /* UARTs */ |
80 | #define S3C24XX_VA_UART S3C2410_ADDR(0x00400000) | 54 | #define S3C24XX_VA_UART S3C_VA_UART |
81 | #define S3C2400_PA_UART (0x15000000) | ||
82 | #define S3C2410_PA_UART (0x50000000) | 55 | #define S3C2410_PA_UART (0x50000000) |
83 | #define S3C24XX_SZ_UART SZ_1M | 56 | #define S3C24XX_SZ_UART SZ_1M |
84 | 57 | ||
85 | /* Timers */ | 58 | /* Timers */ |
86 | #define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000) | 59 | #define S3C24XX_VA_TIMER S3C_VA_TIMER |
87 | #define S3C2400_PA_TIMER (0x15100000) | ||
88 | #define S3C2410_PA_TIMER (0x51000000) | 60 | #define S3C2410_PA_TIMER (0x51000000) |
89 | #define S3C24XX_SZ_TIMER SZ_1M | 61 | #define S3C24XX_SZ_TIMER SZ_1M |
90 | 62 | ||
91 | /* USB Device port */ | 63 | /* USB Device port */ |
92 | #define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000) | ||
93 | #define S3C2400_PA_USBDEV (0x15200140) | ||
94 | #define S3C2410_PA_USBDEV (0x52000000) | 64 | #define S3C2410_PA_USBDEV (0x52000000) |
95 | #define S3C24XX_SZ_USBDEV SZ_1M | 65 | #define S3C24XX_SZ_USBDEV SZ_1M |
96 | 66 | ||
97 | /* Watchdog */ | 67 | /* Watchdog */ |
98 | #define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000) | 68 | #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG |
99 | #define S3C2400_PA_WATCHDOG (0x15300000) | ||
100 | #define S3C2410_PA_WATCHDOG (0x53000000) | 69 | #define S3C2410_PA_WATCHDOG (0x53000000) |
101 | #define S3C24XX_SZ_WATCHDOG SZ_1M | 70 | #define S3C24XX_SZ_WATCHDOG SZ_1M |
102 | 71 | ||
103 | /* IIC hardware controller */ | 72 | /* IIC hardware controller */ |
104 | #define S3C2400_PA_IIC (0x15400000) | ||
105 | #define S3C2410_PA_IIC (0x54000000) | 73 | #define S3C2410_PA_IIC (0x54000000) |
106 | #define S3C24XX_SZ_IIC SZ_1M | 74 | #define S3C24XX_SZ_IIC SZ_1M |
107 | 75 | ||
108 | /* IIS controller */ | 76 | /* IIS controller */ |
109 | #define S3C2400_PA_IIS (0x15508000) | ||
110 | #define S3C2410_PA_IIS (0x55000000) | 77 | #define S3C2410_PA_IIS (0x55000000) |
111 | #define S3C24XX_SZ_IIS SZ_1M | 78 | #define S3C24XX_SZ_IIS SZ_1M |
112 | 79 | ||
@@ -116,27 +83,23 @@ | |||
116 | * it is the same distance apart from the UART in the | 83 | * it is the same distance apart from the UART in the |
117 | * phsyical address space, as the initial mapping for the IO | 84 | * phsyical address space, as the initial mapping for the IO |
118 | * is done as a 1:1 maping. This puts it (currently) at | 85 | * is done as a 1:1 maping. This puts it (currently) at |
119 | * 0xF6800000, which is not in the way of any current mapping | 86 | * 0xFA800000, which is not in the way of any current mapping |
120 | * by the base system. | 87 | * by the base system. |
121 | */ | 88 | */ |
122 | 89 | ||
123 | #define S3C2400_PA_GPIO (0x15600000) | ||
124 | #define S3C2410_PA_GPIO (0x56000000) | 90 | #define S3C2410_PA_GPIO (0x56000000) |
125 | #define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) | 91 | #define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) |
126 | #define S3C24XX_SZ_GPIO SZ_1M | 92 | #define S3C24XX_SZ_GPIO SZ_1M |
127 | 93 | ||
128 | /* RTC */ | 94 | /* RTC */ |
129 | #define S3C2400_PA_RTC (0x15700040) | ||
130 | #define S3C2410_PA_RTC (0x57000000) | 95 | #define S3C2410_PA_RTC (0x57000000) |
131 | #define S3C24XX_SZ_RTC SZ_1M | 96 | #define S3C24XX_SZ_RTC SZ_1M |
132 | 97 | ||
133 | /* ADC */ | 98 | /* ADC */ |
134 | #define S3C2400_PA_ADC (0x15800000) | ||
135 | #define S3C2410_PA_ADC (0x58000000) | 99 | #define S3C2410_PA_ADC (0x58000000) |
136 | #define S3C24XX_SZ_ADC SZ_1M | 100 | #define S3C24XX_SZ_ADC SZ_1M |
137 | 101 | ||
138 | /* SPI */ | 102 | /* SPI */ |
139 | #define S3C2400_PA_SPI (0x15900000) | ||
140 | #define S3C2410_PA_SPI (0x59000000) | 103 | #define S3C2410_PA_SPI (0x59000000) |
141 | #define S3C24XX_SZ_SPI SZ_1M | 104 | #define S3C24XX_SZ_SPI SZ_1M |
142 | 105 | ||
@@ -177,37 +140,8 @@ | |||
177 | 140 | ||
178 | #define S3C2410_SDRAM_PA (S3C2410_CS6) | 141 | #define S3C2410_SDRAM_PA (S3C2410_CS6) |
179 | 142 | ||
180 | #define S3C2400_CS0 (0x00000000) | ||
181 | #define S3C2400_CS1 (0x02000000) | ||
182 | #define S3C2400_CS2 (0x04000000) | ||
183 | #define S3C2400_CS3 (0x06000000) | ||
184 | #define S3C2400_CS4 (0x08000000) | ||
185 | #define S3C2400_CS5 (0x0A000000) | ||
186 | #define S3C2400_CS6 (0x0C000000) | ||
187 | #define S3C2400_CS7 (0x0E000000) | ||
188 | |||
189 | #define S3C2400_SDRAM_PA (S3C2400_CS6) | ||
190 | |||
191 | /* Use a single interface for common resources between S3C24XX cpus */ | 143 | /* Use a single interface for common resources between S3C24XX cpus */ |
192 | 144 | ||
193 | #ifdef CONFIG_CPU_S3C2400 | ||
194 | #define S3C24XX_PA_IRQ S3C2400_PA_IRQ | ||
195 | #define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL | ||
196 | #define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST | ||
197 | #define S3C24XX_PA_DMA S3C2400_PA_DMA | ||
198 | #define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR | ||
199 | #define S3C24XX_PA_LCD S3C2400_PA_LCD | ||
200 | #define S3C24XX_PA_UART S3C2400_PA_UART | ||
201 | #define S3C24XX_PA_TIMER S3C2400_PA_TIMER | ||
202 | #define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV | ||
203 | #define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG | ||
204 | #define S3C24XX_PA_IIC S3C2400_PA_IIC | ||
205 | #define S3C24XX_PA_IIS S3C2400_PA_IIS | ||
206 | #define S3C24XX_PA_GPIO S3C2400_PA_GPIO | ||
207 | #define S3C24XX_PA_RTC S3C2400_PA_RTC | ||
208 | #define S3C24XX_PA_ADC S3C2400_PA_ADC | ||
209 | #define S3C24XX_PA_SPI S3C2400_PA_SPI | ||
210 | #else | ||
211 | #define S3C24XX_PA_IRQ S3C2410_PA_IRQ | 145 | #define S3C24XX_PA_IRQ S3C2410_PA_IRQ |
212 | #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL | 146 | #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL |
213 | #define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST | 147 | #define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST |
@@ -224,7 +158,6 @@ | |||
224 | #define S3C24XX_PA_RTC S3C2410_PA_RTC | 158 | #define S3C24XX_PA_RTC S3C2410_PA_RTC |
225 | #define S3C24XX_PA_ADC S3C2410_PA_ADC | 159 | #define S3C24XX_PA_ADC S3C2410_PA_ADC |
226 | #define S3C24XX_PA_SPI S3C2410_PA_SPI | 160 | #define S3C24XX_PA_SPI S3C2410_PA_SPI |
227 | #endif | ||
228 | 161 | ||
229 | /* deal with the registers that move under the 2412/2413 */ | 162 | /* deal with the registers that move under the 2412/2413 */ |
230 | 163 | ||
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h index 4be6a74c4303..533e2436e707 100644 --- a/include/asm-arm/arch-s3c2410/memory.h +++ b/include/asm-arm/arch-s3c2410/memory.h | |||
@@ -11,20 +11,7 @@ | |||
11 | #ifndef __ASM_ARCH_MEMORY_H | 11 | #ifndef __ASM_ARCH_MEMORY_H |
12 | #define __ASM_ARCH_MEMORY_H | 12 | #define __ASM_ARCH_MEMORY_H |
13 | 13 | ||
14 | /* | ||
15 | * DRAM starts at 0x30000000 for S3C2410/S3C2440 | ||
16 | * and at 0x0C000000 for S3C2400 | ||
17 | */ | ||
18 | #ifdef CONFIG_CPU_S3C2400 | ||
19 | #define PHYS_OFFSET UL(0x0C000000) | ||
20 | #else | ||
21 | #define PHYS_OFFSET UL(0x30000000) | 14 | #define PHYS_OFFSET UL(0x30000000) |
22 | #endif | ||
23 | |||
24 | /* | ||
25 | * These are exactly the same on the S3C2410 as the | ||
26 | * physical memory view. | ||
27 | */ | ||
28 | 15 | ||
29 | #define __virt_to_bus(x) __virt_to_phys(x) | 16 | #define __virt_to_bus(x) __virt_to_phys(x) |
30 | #define __bus_to_virt(x) __phys_to_virt(x) | 17 | #define __bus_to_virt(x) __phys_to_virt(x) |
diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/arch-s3c2410/nand.h deleted file mode 100644 index 8816f7f9cee1..000000000000 --- a/include/asm-arm/arch-s3c2410/nand.h +++ /dev/null | |||
@@ -1,45 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/nand.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - NAND device controller platfrom_device info | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | /* struct s3c2410_nand_set | ||
14 | * | ||
15 | * define an set of one or more nand chips registered with an unique mtd | ||
16 | * | ||
17 | * nr_chips = number of chips in this set | ||
18 | * nr_partitions = number of partitions pointed to be partitoons (or zero) | ||
19 | * name = name of set (optional) | ||
20 | * nr_map = map for low-layer logical to physical chip numbers (option) | ||
21 | * partitions = mtd partition list | ||
22 | */ | ||
23 | |||
24 | struct s3c2410_nand_set { | ||
25 | int nr_chips; | ||
26 | int nr_partitions; | ||
27 | char *name; | ||
28 | int *nr_map; | ||
29 | struct mtd_partition *partitions; | ||
30 | }; | ||
31 | |||
32 | struct s3c2410_platform_nand { | ||
33 | /* timing information for controller, all times in nanoseconds */ | ||
34 | |||
35 | int tacls; /* time for active CLE/ALE to nWE/nOE */ | ||
36 | int twrph0; /* active time for nWE/nOE */ | ||
37 | int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ | ||
38 | |||
39 | int nr_sets; | ||
40 | struct s3c2410_nand_set *sets; | ||
41 | |||
42 | void (*select_chip)(struct s3c2410_nand_set *, | ||
43 | int chip); | ||
44 | }; | ||
45 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/arch-s3c2410/regs-ac97.h deleted file mode 100644 index b004dee6bcaf..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-ac97.h +++ /dev/null | |||
@@ -1,67 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-ac97.h | ||
2 | * | ||
3 | * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2440 AC97 Controller | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_AC97_H | ||
14 | #define __ASM_ARCH_REGS_AC97_H __FILE__ | ||
15 | |||
16 | #define S3C_AC97_GLBCTRL (0x00) | ||
17 | |||
18 | #define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22) | ||
19 | #define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21) | ||
20 | #define S3C_AC97_GLBCTRL_PCMINORIE (1<<20) | ||
21 | #define S3C_AC97_GLBCTRL_MICINORIE (1<<19) | ||
22 | #define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18) | ||
23 | #define S3C_AC97_GLBCTRL_PCMINTIE (1<<17) | ||
24 | #define S3C_AC97_GLBCTRL_MICINTIE (1<<16) | ||
25 | #define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12) | ||
26 | #define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12) | ||
27 | #define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12) | ||
28 | #define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12) | ||
29 | #define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10) | ||
30 | #define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10) | ||
31 | #define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10) | ||
32 | #define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10) | ||
33 | #define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8) | ||
34 | #define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8) | ||
35 | #define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8) | ||
36 | #define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8) | ||
37 | #define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3) | ||
38 | #define S3C_AC97_GLBCTRL_ACLINKON (1<<2) | ||
39 | #define S3C_AC97_GLBCTRL_WARMRESET (1<<1) | ||
40 | #define S3C_AC97_GLBCTRL_COLDRESET (1<<0) | ||
41 | |||
42 | #define S3C_AC97_GLBSTAT (0x04) | ||
43 | |||
44 | #define S3C_AC97_GLBSTAT_CODECREADY (1<<22) | ||
45 | #define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21) | ||
46 | #define S3C_AC97_GLBSTAT_PCMINORI (1<<20) | ||
47 | #define S3C_AC97_GLBSTAT_MICINORI (1<<19) | ||
48 | #define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18) | ||
49 | #define S3C_AC97_GLBSTAT_PCMINTI (1<<17) | ||
50 | #define S3C_AC97_GLBSTAT_MICINTI (1<<16) | ||
51 | #define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0) | ||
52 | #define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0) | ||
53 | #define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0) | ||
54 | #define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0) | ||
55 | #define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0) | ||
56 | #define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0) | ||
57 | |||
58 | #define S3C_AC97_CODEC_CMD (0x08) | ||
59 | |||
60 | #define S3C_AC97_CODEC_CMD_READ (1<<23) | ||
61 | |||
62 | #define S3C_AC97_STAT (0x0c) | ||
63 | #define S3C_AC97_PCM_ADDR (0x10) | ||
64 | #define S3C_AC97_PCM_DATA (0x18) | ||
65 | #define S3C_AC97_MIC_DATA (0x1C) | ||
66 | |||
67 | #endif /* __ASM_ARCH_REGS_AC97_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/arch-s3c2410/regs-adc.h deleted file mode 100644 index c7f231963e76..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-adc.h +++ /dev/null | |||
@@ -1,60 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-adc.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Shannon Holland <holland@loser.net> | ||
4 | * | ||
5 | * This program is free software; yosu can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | * S3C2410 ADC registers | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_REGS_ADC_H | ||
13 | #define __ASM_ARCH_REGS_ADC_H "regs-adc.h" | ||
14 | |||
15 | #define S3C2410_ADCREG(x) (x) | ||
16 | |||
17 | #define S3C2410_ADCCON S3C2410_ADCREG(0x00) | ||
18 | #define S3C2410_ADCTSC S3C2410_ADCREG(0x04) | ||
19 | #define S3C2410_ADCDLY S3C2410_ADCREG(0x08) | ||
20 | #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) | ||
21 | #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) | ||
22 | |||
23 | |||
24 | /* ADCCON Register Bits */ | ||
25 | #define S3C2410_ADCCON_ECFLG (1<<15) | ||
26 | #define S3C2410_ADCCON_PRSCEN (1<<14) | ||
27 | #define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) | ||
28 | #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) | ||
29 | #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) | ||
30 | #define S3C2410_ADCCON_MUXMASK (0x7<<3) | ||
31 | #define S3C2410_ADCCON_STDBM (1<<2) | ||
32 | #define S3C2410_ADCCON_READ_START (1<<1) | ||
33 | #define S3C2410_ADCCON_ENABLE_START (1<<0) | ||
34 | #define S3C2410_ADCCON_STARTMASK (0x3<<0) | ||
35 | |||
36 | |||
37 | /* ADCTSC Register Bits */ | ||
38 | #define S3C2410_ADCTSC_YM_SEN (1<<7) | ||
39 | #define S3C2410_ADCTSC_YP_SEN (1<<6) | ||
40 | #define S3C2410_ADCTSC_XM_SEN (1<<5) | ||
41 | #define S3C2410_ADCTSC_XP_SEN (1<<4) | ||
42 | #define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) | ||
43 | #define S3C2410_ADCTSC_AUTO_PST (1<<2) | ||
44 | #define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) | ||
45 | |||
46 | /* ADCDAT0 Bits */ | ||
47 | #define S3C2410_ADCDAT0_UPDOWN (1<<15) | ||
48 | #define S3C2410_ADCDAT0_AUTO_PST (1<<14) | ||
49 | #define S3C2410_ADCDAT0_XY_PST (0x3<<12) | ||
50 | #define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) | ||
51 | |||
52 | /* ADCDAT1 Bits */ | ||
53 | #define S3C2410_ADCDAT1_UPDOWN (1<<15) | ||
54 | #define S3C2410_ADCDAT1_AUTO_PST (1<<14) | ||
55 | #define S3C2410_ADCDAT1_XY_PST (0x3<<12) | ||
56 | #define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) | ||
57 | |||
58 | #endif /* __ASM_ARCH_REGS_ADC_H */ | ||
59 | |||
60 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/arch-s3c2410/regs-iic.h deleted file mode 100644 index 2ae29522f253..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-iic.h +++ /dev/null | |||
@@ -1,56 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-iic.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 I2C Controller | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_IIC_H | ||
14 | #define __ASM_ARCH_REGS_IIC_H __FILE__ | ||
15 | |||
16 | /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ | ||
17 | |||
18 | #define S3C2410_IICREG(x) (x) | ||
19 | |||
20 | #define S3C2410_IICCON S3C2410_IICREG(0x00) | ||
21 | #define S3C2410_IICSTAT S3C2410_IICREG(0x04) | ||
22 | #define S3C2410_IICADD S3C2410_IICREG(0x08) | ||
23 | #define S3C2410_IICDS S3C2410_IICREG(0x0C) | ||
24 | #define S3C2440_IICLC S3C2410_IICREG(0x10) | ||
25 | |||
26 | #define S3C2410_IICCON_ACKEN (1<<7) | ||
27 | #define S3C2410_IICCON_TXDIV_16 (0<<6) | ||
28 | #define S3C2410_IICCON_TXDIV_512 (1<<6) | ||
29 | #define S3C2410_IICCON_IRQEN (1<<5) | ||
30 | #define S3C2410_IICCON_IRQPEND (1<<4) | ||
31 | #define S3C2410_IICCON_SCALE(x) ((x)&15) | ||
32 | #define S3C2410_IICCON_SCALEMASK (0xf) | ||
33 | |||
34 | #define S3C2410_IICSTAT_MASTER_RX (2<<6) | ||
35 | #define S3C2410_IICSTAT_MASTER_TX (3<<6) | ||
36 | #define S3C2410_IICSTAT_SLAVE_RX (0<<6) | ||
37 | #define S3C2410_IICSTAT_SLAVE_TX (1<<6) | ||
38 | #define S3C2410_IICSTAT_MODEMASK (3<<6) | ||
39 | |||
40 | #define S3C2410_IICSTAT_START (1<<5) | ||
41 | #define S3C2410_IICSTAT_BUSBUSY (1<<5) | ||
42 | #define S3C2410_IICSTAT_TXRXEN (1<<4) | ||
43 | #define S3C2410_IICSTAT_ARBITR (1<<3) | ||
44 | #define S3C2410_IICSTAT_ASSLAVE (1<<2) | ||
45 | #define S3C2410_IICSTAT_ADDR0 (1<<1) | ||
46 | #define S3C2410_IICSTAT_LASTBIT (1<<0) | ||
47 | |||
48 | #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) | ||
49 | #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) | ||
50 | #define S3C2410_IICLC_SDA_DELAY10 (2 << 0) | ||
51 | #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) | ||
52 | #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) | ||
53 | |||
54 | #define S3C2410_IICLC_FILTER_ON (1<<2) | ||
55 | |||
56 | #endif /* __ASM_ARCH_REGS_IIC_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h deleted file mode 100644 index eaf77916a602..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-iis.h +++ /dev/null | |||
@@ -1,77 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-iis.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 IIS register definition | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_IIS_H | ||
14 | #define __ASM_ARCH_REGS_IIS_H | ||
15 | |||
16 | #define S3C2410_IISCON (0x00) | ||
17 | |||
18 | #define S3C2410_IISCON_LRINDEX (1<<8) | ||
19 | #define S3C2410_IISCON_TXFIFORDY (1<<7) | ||
20 | #define S3C2410_IISCON_RXFIFORDY (1<<6) | ||
21 | #define S3C2410_IISCON_TXDMAEN (1<<5) | ||
22 | #define S3C2410_IISCON_RXDMAEN (1<<4) | ||
23 | #define S3C2410_IISCON_TXIDLE (1<<3) | ||
24 | #define S3C2410_IISCON_RXIDLE (1<<2) | ||
25 | #define S3C2410_IISCON_PSCEN (1<<1) | ||
26 | #define S3C2410_IISCON_IISEN (1<<0) | ||
27 | |||
28 | #define S3C2410_IISMOD (0x04) | ||
29 | |||
30 | #define S3C2440_IISMOD_MPLL (1<<9) | ||
31 | #define S3C2410_IISMOD_SLAVE (1<<8) | ||
32 | #define S3C2410_IISMOD_NOXFER (0<<6) | ||
33 | #define S3C2410_IISMOD_RXMODE (1<<6) | ||
34 | #define S3C2410_IISMOD_TXMODE (2<<6) | ||
35 | #define S3C2410_IISMOD_TXRXMODE (3<<6) | ||
36 | #define S3C2410_IISMOD_LR_LLOW (0<<5) | ||
37 | #define S3C2410_IISMOD_LR_RLOW (1<<5) | ||
38 | #define S3C2410_IISMOD_IIS (0<<4) | ||
39 | #define S3C2410_IISMOD_MSB (1<<4) | ||
40 | #define S3C2410_IISMOD_8BIT (0<<3) | ||
41 | #define S3C2410_IISMOD_16BIT (1<<3) | ||
42 | #define S3C2410_IISMOD_BITMASK (1<<3) | ||
43 | #define S3C2410_IISMOD_256FS (0<<2) | ||
44 | #define S3C2410_IISMOD_384FS (1<<2) | ||
45 | #define S3C2410_IISMOD_16FS (0<<0) | ||
46 | #define S3C2410_IISMOD_32FS (1<<0) | ||
47 | #define S3C2410_IISMOD_48FS (2<<0) | ||
48 | #define S3C2410_IISMOD_FS_MASK (3<<0) | ||
49 | |||
50 | #define S3C2410_IISPSR (0x08) | ||
51 | #define S3C2410_IISPSR_INTMASK (31<<5) | ||
52 | #define S3C2410_IISPSR_INTSHIFT (5) | ||
53 | #define S3C2410_IISPSR_EXTMASK (31<<0) | ||
54 | #define S3C2410_IISPSR_EXTSHFIT (0) | ||
55 | |||
56 | #define S3C2410_IISFCON (0x0c) | ||
57 | |||
58 | #define S3C2410_IISFCON_TXDMA (1<<15) | ||
59 | #define S3C2410_IISFCON_RXDMA (1<<14) | ||
60 | #define S3C2410_IISFCON_TXENABLE (1<<13) | ||
61 | #define S3C2410_IISFCON_RXENABLE (1<<12) | ||
62 | #define S3C2410_IISFCON_TXMASK (0x3f << 6) | ||
63 | #define S3C2410_IISFCON_TXSHIFT (6) | ||
64 | #define S3C2410_IISFCON_RXMASK (0x3f) | ||
65 | #define S3C2410_IISFCON_RXSHIFT (0) | ||
66 | |||
67 | #define S3C2400_IISFCON_TXDMA (1<<11) | ||
68 | #define S3C2400_IISFCON_RXDMA (1<<10) | ||
69 | #define S3C2400_IISFCON_TXENABLE (1<<9) | ||
70 | #define S3C2400_IISFCON_RXENABLE (1<<8) | ||
71 | #define S3C2400_IISFCON_TXMASK (0x07 << 4) | ||
72 | #define S3C2400_IISFCON_TXSHIFT (4) | ||
73 | #define S3C2400_IISFCON_RXMASK (0x07) | ||
74 | #define S3C2400_IISFCON_RXSHIFT (0) | ||
75 | |||
76 | #define S3C2410_IISFIFO (0x10) | ||
77 | #endif /* __ASM_ARCH_REGS_IIS_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h index b7faeb04c0ff..76fe5f693426 100644 --- a/include/asm-arm/arch-s3c2410/regs-lcd.h +++ b/include/asm-arm/arch-s3c2410/regs-lcd.h | |||
@@ -12,7 +12,7 @@ | |||
12 | #ifndef ___ASM_ARCH_REGS_LCD_H | 12 | #ifndef ___ASM_ARCH_REGS_LCD_H |
13 | #define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $" | 13 | #define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $" |
14 | 14 | ||
15 | #define S3C2410_LCDREG(x) ((x) + S3C24XX_VA_LCD) | 15 | #define S3C2410_LCDREG(x) (x) |
16 | 16 | ||
17 | /* LCD control registers */ | 17 | /* LCD control registers */ |
18 | #define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) | 18 | #define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) |
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/arch-s3c2410/regs-nand.h deleted file mode 100644 index b824d371ae0b..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-nand.h +++ /dev/null | |||
@@ -1,123 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-nand.h | ||
2 | * | ||
3 | * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 NAND register definitions | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARM_REGS_NAND | ||
14 | #define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $" | ||
15 | |||
16 | |||
17 | #define S3C2410_NFREG(x) (x) | ||
18 | |||
19 | #define S3C2410_NFCONF S3C2410_NFREG(0x00) | ||
20 | #define S3C2410_NFCMD S3C2410_NFREG(0x04) | ||
21 | #define S3C2410_NFADDR S3C2410_NFREG(0x08) | ||
22 | #define S3C2410_NFDATA S3C2410_NFREG(0x0C) | ||
23 | #define S3C2410_NFSTAT S3C2410_NFREG(0x10) | ||
24 | #define S3C2410_NFECC S3C2410_NFREG(0x14) | ||
25 | |||
26 | #define S3C2440_NFCONT S3C2410_NFREG(0x04) | ||
27 | #define S3C2440_NFCMD S3C2410_NFREG(0x08) | ||
28 | #define S3C2440_NFADDR S3C2410_NFREG(0x0C) | ||
29 | #define S3C2440_NFDATA S3C2410_NFREG(0x10) | ||
30 | #define S3C2440_NFECCD0 S3C2410_NFREG(0x14) | ||
31 | #define S3C2440_NFECCD1 S3C2410_NFREG(0x18) | ||
32 | #define S3C2440_NFECCD S3C2410_NFREG(0x1C) | ||
33 | #define S3C2440_NFSTAT S3C2410_NFREG(0x20) | ||
34 | #define S3C2440_NFESTAT0 S3C2410_NFREG(0x24) | ||
35 | #define S3C2440_NFESTAT1 S3C2410_NFREG(0x28) | ||
36 | #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) | ||
37 | #define S3C2440_NFMECC1 S3C2410_NFREG(0x30) | ||
38 | #define S3C2440_NFSECC S3C24E10_NFREG(0x34) | ||
39 | #define S3C2440_NFSBLK S3C2410_NFREG(0x38) | ||
40 | #define S3C2440_NFEBLK S3C2410_NFREG(0x3C) | ||
41 | |||
42 | #define S3C2412_NFSBLK S3C2410_NFREG(0x20) | ||
43 | #define S3C2412_NFEBLK S3C2410_NFREG(0x24) | ||
44 | #define S3C2412_NFSTAT S3C2410_NFREG(0x28) | ||
45 | #define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C) | ||
46 | #define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30) | ||
47 | #define S3C2412_NFMECC0 S3C2410_NFREG(0x34) | ||
48 | #define S3C2412_NFMECC1 S3C2410_NFREG(0x38) | ||
49 | #define S3C2412_NFSECC S3C2410_NFREG(0x3C) | ||
50 | |||
51 | #define S3C2410_NFCONF_EN (1<<15) | ||
52 | #define S3C2410_NFCONF_512BYTE (1<<14) | ||
53 | #define S3C2410_NFCONF_4STEP (1<<13) | ||
54 | #define S3C2410_NFCONF_INITECC (1<<12) | ||
55 | #define S3C2410_NFCONF_nFCE (1<<11) | ||
56 | #define S3C2410_NFCONF_TACLS(x) ((x)<<8) | ||
57 | #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) | ||
58 | #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) | ||
59 | |||
60 | #define S3C2410_NFSTAT_BUSY (1<<0) | ||
61 | |||
62 | #define S3C2440_NFCONF_BUSWIDTH_8 (0<<0) | ||
63 | #define S3C2440_NFCONF_BUSWIDTH_16 (1<<0) | ||
64 | #define S3C2440_NFCONF_ADVFLASH (1<<3) | ||
65 | #define S3C2440_NFCONF_TACLS(x) ((x)<<12) | ||
66 | #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) | ||
67 | #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) | ||
68 | |||
69 | #define S3C2440_NFCONT_LOCKTIGHT (1<<13) | ||
70 | #define S3C2440_NFCONT_SOFTLOCK (1<<12) | ||
71 | #define S3C2440_NFCONT_ILLEGALACC_EN (1<<10) | ||
72 | #define S3C2440_NFCONT_RNBINT_EN (1<<9) | ||
73 | #define S3C2440_NFCONT_RN_FALLING (1<<8) | ||
74 | #define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6) | ||
75 | #define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5) | ||
76 | #define S3C2440_NFCONT_INITECC (1<<4) | ||
77 | #define S3C2440_NFCONT_nFCE (1<<1) | ||
78 | #define S3C2440_NFCONT_ENABLE (1<<0) | ||
79 | |||
80 | #define S3C2440_NFSTAT_READY (1<<0) | ||
81 | #define S3C2440_NFSTAT_nCE (1<<1) | ||
82 | #define S3C2440_NFSTAT_RnB_CHANGE (1<<2) | ||
83 | #define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3) | ||
84 | |||
85 | #define S3C2412_NFCONF_NANDBOOT (1<<31) | ||
86 | #define S3C2412_NFCONF_ECCCLKCON (1<<30) | ||
87 | #define S3C2412_NFCONF_ECC_MLC (1<<24) | ||
88 | #define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */ | ||
89 | |||
90 | #define S3C2412_NFCONT_ECC4_DIRWR (1<<18) | ||
91 | #define S3C2412_NFCONT_LOCKTIGHT (1<<17) | ||
92 | #define S3C2412_NFCONT_SOFTLOCK (1<<16) | ||
93 | #define S3C2412_NFCONT_ECC4_ENCINT (1<<13) | ||
94 | #define S3C2412_NFCONT_ECC4_DECINT (1<<12) | ||
95 | #define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7) | ||
96 | #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) | ||
97 | #define S3C2412_NFCONT_nFCE1 (1<<2) | ||
98 | #define S3C2412_NFCONT_nFCE0 (1<<1) | ||
99 | |||
100 | #define S3C2412_NFSTAT_ECC_ENCDONE (1<<7) | ||
101 | #define S3C2412_NFSTAT_ECC_DECDONE (1<<6) | ||
102 | #define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5) | ||
103 | #define S3C2412_NFSTAT_RnB_CHANGE (1<<4) | ||
104 | #define S3C2412_NFSTAT_nFCE1 (1<<3) | ||
105 | #define S3C2412_NFSTAT_nFCE0 (1<<2) | ||
106 | #define S3C2412_NFSTAT_Res1 (1<<1) | ||
107 | #define S3C2412_NFSTAT_READY (1<<0) | ||
108 | |||
109 | #define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf) | ||
110 | #define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7) | ||
111 | #define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff) | ||
112 | #define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7) | ||
113 | #define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3) | ||
114 | #define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3) | ||
115 | #define S3C2412_NFECCERR_NONE (0) | ||
116 | #define S3C2412_NFECCERR_1BIT (1) | ||
117 | #define S3C2412_NFECCERR_MULTIBIT (2) | ||
118 | #define S3C2412_NFECCERR_ECCAREA (3) | ||
119 | |||
120 | |||
121 | |||
122 | #endif /* __ASM_ARM_REGS_NAND */ | ||
123 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/arch-s3c2410/regs-rtc.h deleted file mode 100644 index 93b03c49710a..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-rtc.h +++ /dev/null | |||
@@ -1,61 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-rtc.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 Internal RTC register definition | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_RTC_H | ||
14 | #define __ASM_ARCH_REGS_RTC_H __FILE__ | ||
15 | |||
16 | #define S3C2410_RTCREG(x) (x) | ||
17 | |||
18 | #define S3C2410_RTCCON S3C2410_RTCREG(0x40) | ||
19 | #define S3C2410_RTCCON_RTCEN (1<<0) | ||
20 | #define S3C2410_RTCCON_CLKSEL (1<<1) | ||
21 | #define S3C2410_RTCCON_CNTSEL (1<<2) | ||
22 | #define S3C2410_RTCCON_CLKRST (1<<3) | ||
23 | |||
24 | #define S3C2410_TICNT S3C2410_RTCREG(0x44) | ||
25 | #define S3C2410_TICNT_ENABLE (1<<7) | ||
26 | |||
27 | #define S3C2410_RTCALM S3C2410_RTCREG(0x50) | ||
28 | #define S3C2410_RTCALM_ALMEN (1<<6) | ||
29 | #define S3C2410_RTCALM_YEAREN (1<<5) | ||
30 | #define S3C2410_RTCALM_MONEN (1<<4) | ||
31 | #define S3C2410_RTCALM_DAYEN (1<<3) | ||
32 | #define S3C2410_RTCALM_HOUREN (1<<2) | ||
33 | #define S3C2410_RTCALM_MINEN (1<<1) | ||
34 | #define S3C2410_RTCALM_SECEN (1<<0) | ||
35 | |||
36 | #define S3C2410_RTCALM_ALL \ | ||
37 | S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\ | ||
38 | S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\ | ||
39 | S3C2410_RTCALM_SECEN | ||
40 | |||
41 | |||
42 | #define S3C2410_ALMSEC S3C2410_RTCREG(0x54) | ||
43 | #define S3C2410_ALMMIN S3C2410_RTCREG(0x58) | ||
44 | #define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) | ||
45 | |||
46 | #define S3C2410_ALMDATE S3C2410_RTCREG(0x60) | ||
47 | #define S3C2410_ALMMON S3C2410_RTCREG(0x64) | ||
48 | #define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) | ||
49 | |||
50 | #define S3C2410_RTCRST S3C2410_RTCREG(0x6c) | ||
51 | |||
52 | #define S3C2410_RTCSEC S3C2410_RTCREG(0x70) | ||
53 | #define S3C2410_RTCMIN S3C2410_RTCREG(0x74) | ||
54 | #define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) | ||
55 | #define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) | ||
56 | #define S3C2410_RTCDAY S3C2410_RTCREG(0x80) | ||
57 | #define S3C2410_RTCMON S3C2410_RTCREG(0x84) | ||
58 | #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) | ||
59 | |||
60 | |||
61 | #endif /* __ASM_ARCH_REGS_RTC_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h deleted file mode 100644 index 8946702a87f5..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-serial.h +++ /dev/null | |||
@@ -1,232 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-serial.h | ||
2 | * | ||
3 | * From linux/include/asm-arm/hardware/serial_s3c2410.h | ||
4 | * | ||
5 | * Internal header file for Samsung S3C2410 serial ports (UART0-2) | ||
6 | * | ||
7 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
8 | * | ||
9 | * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk) | ||
10 | * | ||
11 | * Adapted from: | ||
12 | * | ||
13 | * Internal header file for MX1ADS serial ports (UART1 & 2) | ||
14 | * | ||
15 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
16 | * | ||
17 | * This program is free software; you can redistribute it and/or modify | ||
18 | * it under the terms of the GNU General Public License as published by | ||
19 | * the Free Software Foundation; either version 2 of the License, or | ||
20 | * (at your option) any later version. | ||
21 | * | ||
22 | * This program is distributed in the hope that it will be useful, | ||
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
25 | * GNU General Public License for more details. | ||
26 | * | ||
27 | * You should have received a copy of the GNU General Public License | ||
28 | * along with this program; if not, write to the Free Software | ||
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
30 | */ | ||
31 | |||
32 | #ifndef __ASM_ARM_REGS_SERIAL_H | ||
33 | #define __ASM_ARM_REGS_SERIAL_H | ||
34 | |||
35 | #define S3C24XX_VA_UART0 (S3C24XX_VA_UART) | ||
36 | #define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 ) | ||
37 | #define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 ) | ||
38 | #define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 ) | ||
39 | |||
40 | #define S3C2410_PA_UART0 (S3C24XX_PA_UART) | ||
41 | #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) | ||
42 | #define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) | ||
43 | #define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) | ||
44 | |||
45 | #define S3C2410_URXH (0x24) | ||
46 | #define S3C2410_UTXH (0x20) | ||
47 | #define S3C2410_ULCON (0x00) | ||
48 | #define S3C2410_UCON (0x04) | ||
49 | #define S3C2410_UFCON (0x08) | ||
50 | #define S3C2410_UMCON (0x0C) | ||
51 | #define S3C2410_UBRDIV (0x28) | ||
52 | #define S3C2410_UTRSTAT (0x10) | ||
53 | #define S3C2410_UERSTAT (0x14) | ||
54 | #define S3C2410_UFSTAT (0x18) | ||
55 | #define S3C2410_UMSTAT (0x1C) | ||
56 | |||
57 | #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) | ||
58 | |||
59 | #define S3C2410_LCON_CS5 (0x0) | ||
60 | #define S3C2410_LCON_CS6 (0x1) | ||
61 | #define S3C2410_LCON_CS7 (0x2) | ||
62 | #define S3C2410_LCON_CS8 (0x3) | ||
63 | #define S3C2410_LCON_CSMASK (0x3) | ||
64 | |||
65 | #define S3C2410_LCON_PNONE (0x0) | ||
66 | #define S3C2410_LCON_PEVEN (0x5 << 3) | ||
67 | #define S3C2410_LCON_PODD (0x4 << 3) | ||
68 | #define S3C2410_LCON_PMASK (0x7 << 3) | ||
69 | |||
70 | #define S3C2410_LCON_STOPB (1<<2) | ||
71 | #define S3C2410_LCON_IRM (1<<6) | ||
72 | |||
73 | #define S3C2440_UCON_CLKMASK (3<<10) | ||
74 | #define S3C2440_UCON_PCLK (0<<10) | ||
75 | #define S3C2440_UCON_UCLK (1<<10) | ||
76 | #define S3C2440_UCON_PCLK2 (2<<10) | ||
77 | #define S3C2440_UCON_FCLK (3<<10) | ||
78 | #define S3C2443_UCON_EPLL (3<<10) | ||
79 | |||
80 | #define S3C2440_UCON2_FCLK_EN (1<<15) | ||
81 | #define S3C2440_UCON0_DIVMASK (15 << 12) | ||
82 | #define S3C2440_UCON1_DIVMASK (15 << 12) | ||
83 | #define S3C2440_UCON2_DIVMASK (7 << 12) | ||
84 | #define S3C2440_UCON_DIVSHIFT (12) | ||
85 | |||
86 | #define S3C2412_UCON_CLKMASK (3<<10) | ||
87 | #define S3C2412_UCON_UCLK (1<<10) | ||
88 | #define S3C2412_UCON_USYSCLK (3<<10) | ||
89 | #define S3C2412_UCON_PCLK (0<<10) | ||
90 | #define S3C2412_UCON_PCLK2 (2<<10) | ||
91 | |||
92 | #define S3C2410_UCON_UCLK (1<<10) | ||
93 | #define S3C2410_UCON_SBREAK (1<<4) | ||
94 | |||
95 | #define S3C2410_UCON_TXILEVEL (1<<9) | ||
96 | #define S3C2410_UCON_RXILEVEL (1<<8) | ||
97 | #define S3C2410_UCON_TXIRQMODE (1<<2) | ||
98 | #define S3C2410_UCON_RXIRQMODE (1<<0) | ||
99 | #define S3C2410_UCON_RXFIFO_TOI (1<<7) | ||
100 | #define S3C2443_UCON_RXERR_IRQEN (1<<6) | ||
101 | #define S3C2443_UCON_LOOPBACK (1<<5) | ||
102 | |||
103 | #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | ||
104 | S3C2410_UCON_RXILEVEL | \ | ||
105 | S3C2410_UCON_TXIRQMODE | \ | ||
106 | S3C2410_UCON_RXIRQMODE | \ | ||
107 | S3C2410_UCON_RXFIFO_TOI) | ||
108 | |||
109 | #define S3C2410_UFCON_FIFOMODE (1<<0) | ||
110 | #define S3C2410_UFCON_TXTRIG0 (0<<6) | ||
111 | #define S3C2410_UFCON_RXTRIG8 (1<<4) | ||
112 | #define S3C2410_UFCON_RXTRIG12 (2<<4) | ||
113 | |||
114 | /* S3C2440 FIFO trigger levels */ | ||
115 | #define S3C2440_UFCON_RXTRIG1 (0<<4) | ||
116 | #define S3C2440_UFCON_RXTRIG8 (1<<4) | ||
117 | #define S3C2440_UFCON_RXTRIG16 (2<<4) | ||
118 | #define S3C2440_UFCON_RXTRIG32 (3<<4) | ||
119 | |||
120 | #define S3C2440_UFCON_TXTRIG0 (0<<6) | ||
121 | #define S3C2440_UFCON_TXTRIG16 (1<<6) | ||
122 | #define S3C2440_UFCON_TXTRIG32 (2<<6) | ||
123 | #define S3C2440_UFCON_TXTRIG48 (3<<6) | ||
124 | |||
125 | #define S3C2410_UFCON_RESETBOTH (3<<1) | ||
126 | #define S3C2410_UFCON_RESETTX (1<<2) | ||
127 | #define S3C2410_UFCON_RESETRX (1<<1) | ||
128 | |||
129 | #define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
130 | S3C2410_UFCON_TXTRIG0 | \ | ||
131 | S3C2410_UFCON_RXTRIG8 ) | ||
132 | |||
133 | #define S3C2410_UMCOM_AFC (1<<4) | ||
134 | #define S3C2410_UMCOM_RTS_LOW (1<<0) | ||
135 | |||
136 | #define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */ | ||
137 | #define S3C2412_UMCON_AFC_56 (1<<5) | ||
138 | #define S3C2412_UMCON_AFC_48 (2<<5) | ||
139 | #define S3C2412_UMCON_AFC_40 (3<<5) | ||
140 | #define S3C2412_UMCON_AFC_32 (4<<5) | ||
141 | #define S3C2412_UMCON_AFC_24 (5<<5) | ||
142 | #define S3C2412_UMCON_AFC_16 (6<<5) | ||
143 | #define S3C2412_UMCON_AFC_8 (7<<5) | ||
144 | |||
145 | #define S3C2410_UFSTAT_TXFULL (1<<9) | ||
146 | #define S3C2410_UFSTAT_RXFULL (1<<8) | ||
147 | #define S3C2410_UFSTAT_TXMASK (15<<4) | ||
148 | #define S3C2410_UFSTAT_TXSHIFT (4) | ||
149 | #define S3C2410_UFSTAT_RXMASK (15<<0) | ||
150 | #define S3C2410_UFSTAT_RXSHIFT (0) | ||
151 | |||
152 | /* UFSTAT S3C2443 same as S3C2440 */ | ||
153 | #define S3C2440_UFSTAT_TXFULL (1<<14) | ||
154 | #define S3C2440_UFSTAT_RXFULL (1<<6) | ||
155 | #define S3C2440_UFSTAT_TXSHIFT (8) | ||
156 | #define S3C2440_UFSTAT_RXSHIFT (0) | ||
157 | #define S3C2440_UFSTAT_TXMASK (63<<8) | ||
158 | #define S3C2440_UFSTAT_RXMASK (63) | ||
159 | |||
160 | #define S3C2410_UTRSTAT_TXE (1<<2) | ||
161 | #define S3C2410_UTRSTAT_TXFE (1<<1) | ||
162 | #define S3C2410_UTRSTAT_RXDR (1<<0) | ||
163 | |||
164 | #define S3C2410_UERSTAT_OVERRUN (1<<0) | ||
165 | #define S3C2410_UERSTAT_FRAME (1<<2) | ||
166 | #define S3C2410_UERSTAT_BREAK (1<<3) | ||
167 | #define S3C2443_UERSTAT_PARITY (1<<1) | ||
168 | |||
169 | #define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ | ||
170 | S3C2410_UERSTAT_FRAME | \ | ||
171 | S3C2410_UERSTAT_BREAK) | ||
172 | |||
173 | #define S3C2410_UMSTAT_CTS (1<<0) | ||
174 | #define S3C2410_UMSTAT_DeltaCTS (1<<2) | ||
175 | |||
176 | #define S3C2443_DIVSLOT (0x2C) | ||
177 | |||
178 | #ifndef __ASSEMBLY__ | ||
179 | |||
180 | /* struct s3c24xx_uart_clksrc | ||
181 | * | ||
182 | * this structure defines a named clock source that can be used for the | ||
183 | * uart, so that the best clock can be selected for the requested baud | ||
184 | * rate. | ||
185 | * | ||
186 | * min_baud and max_baud define the range of baud-rates this clock is | ||
187 | * acceptable for, if they are both zero, it is assumed any baud rate that | ||
188 | * can be generated from this clock will be used. | ||
189 | * | ||
190 | * divisor gives the divisor from the clock to the one seen by the uart | ||
191 | */ | ||
192 | |||
193 | struct s3c24xx_uart_clksrc { | ||
194 | const char *name; | ||
195 | unsigned int divisor; | ||
196 | unsigned int min_baud; | ||
197 | unsigned int max_baud; | ||
198 | }; | ||
199 | |||
200 | /* configuration structure for per-machine configurations for the | ||
201 | * serial port | ||
202 | * | ||
203 | * the pointer is setup by the machine specific initialisation from the | ||
204 | * arch/arm/mach-s3c2410/ directory. | ||
205 | */ | ||
206 | |||
207 | struct s3c2410_uartcfg { | ||
208 | unsigned char hwport; /* hardware port number */ | ||
209 | unsigned char unused; | ||
210 | unsigned short flags; | ||
211 | upf_t uart_flags; /* default uart flags */ | ||
212 | |||
213 | unsigned long ucon; /* value of ucon for port */ | ||
214 | unsigned long ulcon; /* value of ulcon for port */ | ||
215 | unsigned long ufcon; /* value of ufcon for port */ | ||
216 | |||
217 | struct s3c24xx_uart_clksrc *clocks; | ||
218 | unsigned int clocks_size; | ||
219 | }; | ||
220 | |||
221 | /* s3c24xx_uart_devs | ||
222 | * | ||
223 | * this is exported from the core as we cannot use driver_register(), | ||
224 | * or platform_add_device() before the console_initcall() | ||
225 | */ | ||
226 | |||
227 | extern struct platform_device *s3c24xx_uart_devs[3]; | ||
228 | |||
229 | #endif /* __ASSEMBLY__ */ | ||
230 | |||
231 | #endif /* __ASM_ARM_REGS_SERIAL_H */ | ||
232 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/arch-s3c2410/regs-spi.h deleted file mode 100644 index 4a499a138256..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-spi.h +++ /dev/null | |||
@@ -1,54 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-spi.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Fetron GmbH | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | * S3C2410 SPI register definition | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_REGS_SPI_H | ||
13 | #define __ASM_ARCH_REGS_SPI_H | ||
14 | |||
15 | #define S3C2410_SPI1 (0x20) | ||
16 | #define S3C2412_SPI1 (0x100) | ||
17 | |||
18 | #define S3C2410_SPCON (0x00) | ||
19 | |||
20 | #define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ | ||
21 | #define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ | ||
22 | #define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ | ||
23 | #define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */ | ||
24 | #define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select | ||
25 | 0: slave, 1: master */ | ||
26 | #define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */ | ||
27 | #define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */ | ||
28 | |||
29 | #define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */ | ||
30 | #define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */ | ||
31 | |||
32 | #define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */ | ||
33 | |||
34 | |||
35 | #define S3C2410_SPSTA (0x04) | ||
36 | |||
37 | #define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ | ||
38 | #define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ | ||
39 | #define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ | ||
40 | |||
41 | |||
42 | #define S3C2410_SPPIN (0x08) | ||
43 | |||
44 | #define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */ | ||
45 | #define S3C2410_SPPIN_RESERVED (1<<1) | ||
46 | #define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */ | ||
47 | #define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ | ||
48 | |||
49 | |||
50 | #define S3C2410_SPPRE (0x0C) | ||
51 | #define S3C2410_SPTDAT (0x10) | ||
52 | #define S3C2410_SPRDAT (0x14) | ||
53 | |||
54 | #endif /* __ASM_ARCH_REGS_SPI_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/arch-s3c2410/regs-timer.h deleted file mode 100644 index 6f8fe432fe3a..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-timer.h +++ /dev/null | |||
@@ -1,106 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-timer.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 Timer configuration | ||
11 | */ | ||
12 | |||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_TIMER_H | ||
15 | #define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $" | ||
16 | |||
17 | #define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x)) | ||
18 | #define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c)) | ||
19 | |||
20 | #define S3C2410_TCFG0 S3C2410_TIMERREG(0x00) | ||
21 | #define S3C2410_TCFG1 S3C2410_TIMERREG(0x04) | ||
22 | #define S3C2410_TCON S3C2410_TIMERREG(0x08) | ||
23 | |||
24 | #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) | ||
25 | #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) | ||
26 | #define S3C2410_TCFG_PRESCALER1_SHIFT (8) | ||
27 | #define S3C2410_TCFG_DEADZONE_MASK (255<<16) | ||
28 | #define S3C2410_TCFG_DEADZONE_SHIFT (16) | ||
29 | |||
30 | #define S3C2410_TCFG1_MUX4_DIV2 (0<<16) | ||
31 | #define S3C2410_TCFG1_MUX4_DIV4 (1<<16) | ||
32 | #define S3C2410_TCFG1_MUX4_DIV8 (2<<16) | ||
33 | #define S3C2410_TCFG1_MUX4_DIV16 (3<<16) | ||
34 | #define S3C2410_TCFG1_MUX4_TCLK1 (4<<16) | ||
35 | #define S3C2410_TCFG1_MUX4_MASK (15<<16) | ||
36 | #define S3C2410_TCFG1_MUX4_SHIFT (16) | ||
37 | |||
38 | #define S3C2410_TCFG1_MUX3_DIV2 (0<<12) | ||
39 | #define S3C2410_TCFG1_MUX3_DIV4 (1<<12) | ||
40 | #define S3C2410_TCFG1_MUX3_DIV8 (2<<12) | ||
41 | #define S3C2410_TCFG1_MUX3_DIV16 (3<<12) | ||
42 | #define S3C2410_TCFG1_MUX3_TCLK1 (4<<12) | ||
43 | #define S3C2410_TCFG1_MUX3_MASK (15<<12) | ||
44 | |||
45 | |||
46 | #define S3C2410_TCFG1_MUX2_DIV2 (0<<8) | ||
47 | #define S3C2410_TCFG1_MUX2_DIV4 (1<<8) | ||
48 | #define S3C2410_TCFG1_MUX2_DIV8 (2<<8) | ||
49 | #define S3C2410_TCFG1_MUX2_DIV16 (3<<8) | ||
50 | #define S3C2410_TCFG1_MUX2_TCLK1 (4<<8) | ||
51 | #define S3C2410_TCFG1_MUX2_MASK (15<<8) | ||
52 | |||
53 | |||
54 | #define S3C2410_TCFG1_MUX1_DIV2 (0<<4) | ||
55 | #define S3C2410_TCFG1_MUX1_DIV4 (1<<4) | ||
56 | #define S3C2410_TCFG1_MUX1_DIV8 (2<<4) | ||
57 | #define S3C2410_TCFG1_MUX1_DIV16 (3<<4) | ||
58 | #define S3C2410_TCFG1_MUX1_TCLK0 (4<<4) | ||
59 | #define S3C2410_TCFG1_MUX1_MASK (15<<4) | ||
60 | |||
61 | #define S3C2410_TCFG1_MUX0_DIV2 (0<<0) | ||
62 | #define S3C2410_TCFG1_MUX0_DIV4 (1<<0) | ||
63 | #define S3C2410_TCFG1_MUX0_DIV8 (2<<0) | ||
64 | #define S3C2410_TCFG1_MUX0_DIV16 (3<<0) | ||
65 | #define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) | ||
66 | #define S3C2410_TCFG1_MUX0_MASK (15<<0) | ||
67 | |||
68 | /* for each timer, we have an count buffer, an compare buffer and | ||
69 | * an observation buffer | ||
70 | */ | ||
71 | |||
72 | /* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ | ||
73 | |||
74 | #define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00) | ||
75 | #define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04) | ||
76 | #define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) | ||
77 | |||
78 | #define S3C2410_TCON_T4RELOAD (1<<22) | ||
79 | #define S3C2410_TCON_T4MANUALUPD (1<<21) | ||
80 | #define S3C2410_TCON_T4START (1<<20) | ||
81 | |||
82 | #define S3C2410_TCON_T3RELOAD (1<<19) | ||
83 | #define S3C2410_TCON_T3INVERT (1<<18) | ||
84 | #define S3C2410_TCON_T3MANUALUPD (1<<17) | ||
85 | #define S3C2410_TCON_T3START (1<<16) | ||
86 | |||
87 | #define S3C2410_TCON_T2RELOAD (1<<15) | ||
88 | #define S3C2410_TCON_T2INVERT (1<<14) | ||
89 | #define S3C2410_TCON_T2MANUALUPD (1<<13) | ||
90 | #define S3C2410_TCON_T2START (1<<12) | ||
91 | |||
92 | #define S3C2410_TCON_T1RELOAD (1<<11) | ||
93 | #define S3C2410_TCON_T1INVERT (1<<10) | ||
94 | #define S3C2410_TCON_T1MANUALUPD (1<<9) | ||
95 | #define S3C2410_TCON_T1START (1<<8) | ||
96 | |||
97 | #define S3C2410_TCON_T0DEADZONE (1<<4) | ||
98 | #define S3C2410_TCON_T0RELOAD (1<<3) | ||
99 | #define S3C2410_TCON_T0INVERT (1<<2) | ||
100 | #define S3C2410_TCON_T0MANUALUPD (1<<1) | ||
101 | #define S3C2410_TCON_T0START (1<<0) | ||
102 | |||
103 | #endif /* __ASM_ARCH_REGS_TIMER_H */ | ||
104 | |||
105 | |||
106 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/arch-s3c2410/regs-udc.h deleted file mode 100644 index e1e9805d2d9a..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-udc.h +++ /dev/null | |||
@@ -1,153 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-udc.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> | ||
4 | * | ||
5 | * This include file is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License as | ||
7 | * published by the Free Software Foundation; either version 2 of | ||
8 | * the License, or (at your option) any later version. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_REGS_UDC_H | ||
12 | #define __ASM_ARCH_REGS_UDC_H | ||
13 | |||
14 | #define S3C2410_USBDREG(x) (x) | ||
15 | |||
16 | #define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140) | ||
17 | #define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144) | ||
18 | #define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148) | ||
19 | |||
20 | #define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158) | ||
21 | #define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c) | ||
22 | |||
23 | #define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c) | ||
24 | |||
25 | #define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170) | ||
26 | #define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174) | ||
27 | |||
28 | #define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0) | ||
29 | #define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4) | ||
30 | #define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8) | ||
31 | #define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc) | ||
32 | #define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0) | ||
33 | |||
34 | #define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200) | ||
35 | #define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204) | ||
36 | #define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208) | ||
37 | #define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c) | ||
38 | #define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210) | ||
39 | #define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214) | ||
40 | |||
41 | #define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218) | ||
42 | #define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c) | ||
43 | #define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220) | ||
44 | #define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224) | ||
45 | #define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228) | ||
46 | #define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c) | ||
47 | |||
48 | #define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240) | ||
49 | #define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244) | ||
50 | #define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248) | ||
51 | #define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c) | ||
52 | #define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250) | ||
53 | #define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254) | ||
54 | |||
55 | #define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258) | ||
56 | #define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c) | ||
57 | #define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260) | ||
58 | #define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264) | ||
59 | #define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268) | ||
60 | #define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c) | ||
61 | |||
62 | #define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178) | ||
63 | |||
64 | /* indexed registers */ | ||
65 | |||
66 | #define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180) | ||
67 | |||
68 | #define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184) | ||
69 | |||
70 | #define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184) | ||
71 | #define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188) | ||
72 | |||
73 | #define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190) | ||
74 | #define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194) | ||
75 | #define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198) | ||
76 | #define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c) | ||
77 | |||
78 | #define S3C2410_UDC_FUNCADDR_UPDATE (1<<7) | ||
79 | |||
80 | #define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W | ||
81 | #define S3C2410_UDC_PWR_RESET (1<<3) // R | ||
82 | #define S3C2410_UDC_PWR_RESUME (1<<2) // R/W | ||
83 | #define S3C2410_UDC_PWR_SUSPEND (1<<1) // R | ||
84 | #define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W | ||
85 | |||
86 | #define S3C2410_UDC_PWR_DEFAULT 0x00 | ||
87 | |||
88 | #define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only) | ||
89 | #define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only) | ||
90 | #define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only) | ||
91 | #define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only) | ||
92 | #define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only) | ||
93 | |||
94 | #define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only) | ||
95 | #define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only) | ||
96 | #define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only) | ||
97 | |||
98 | #define S3C2410_UDC_INTE_EP4 (1<<4) // R/W | ||
99 | #define S3C2410_UDC_INTE_EP3 (1<<3) // R/W | ||
100 | #define S3C2410_UDC_INTE_EP2 (1<<2) // R/W | ||
101 | #define S3C2410_UDC_INTE_EP1 (1<<1) // R/W | ||
102 | #define S3C2410_UDC_INTE_EP0 (1<<0) // R/W | ||
103 | |||
104 | #define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W | ||
105 | #define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W | ||
106 | |||
107 | |||
108 | #define S3C2410_UDC_INDEX_EP0 (0x00) | ||
109 | #define S3C2410_UDC_INDEX_EP1 (0x01) // ?? | ||
110 | #define S3C2410_UDC_INDEX_EP2 (0x02) // ?? | ||
111 | #define S3C2410_UDC_INDEX_EP3 (0x03) // ?? | ||
112 | #define S3C2410_UDC_INDEX_EP4 (0x04) // ?? | ||
113 | |||
114 | #define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W | ||
115 | #define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only) | ||
116 | #define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W | ||
117 | #define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only) | ||
118 | #define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only) | ||
119 | #define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only) | ||
120 | |||
121 | #define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W | ||
122 | #define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W | ||
123 | #define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W | ||
124 | #define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W | ||
125 | |||
126 | #define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W | ||
127 | #define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only) | ||
128 | #define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W | ||
129 | #define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W | ||
130 | #define S3C2410_UDC_OCSR1_DERROR (1<<3) // R | ||
131 | #define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only) | ||
132 | #define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only) | ||
133 | |||
134 | #define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W | ||
135 | #define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W | ||
136 | #define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W | ||
137 | |||
138 | #define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0) | ||
139 | #define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1) | ||
140 | #define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2) | ||
141 | #define S3C2410_UDC_EP0_CSR_DE (1<<3) | ||
142 | #define S3C2410_UDC_EP0_CSR_SE (1<<4) | ||
143 | #define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5) | ||
144 | #define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6) | ||
145 | #define S3C2410_UDC_EP0_CSR_SSE (1<<7) | ||
146 | |||
147 | #define S3C2410_UDC_MAXP_8 (1<<0) | ||
148 | #define S3C2410_UDC_MAXP_16 (1<<1) | ||
149 | #define S3C2410_UDC_MAXP_32 (1<<2) | ||
150 | #define S3C2410_UDC_MAXP_64 (1<<3) | ||
151 | |||
152 | |||
153 | #endif | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/arch-s3c2410/regs-watchdog.h deleted file mode 100644 index a9c5d491bdb6..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-watchdog.h +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/regs-watchdog.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 Watchdog timer control | ||
11 | */ | ||
12 | |||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_WATCHDOG_H | ||
15 | #define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $" | ||
16 | |||
17 | #define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG) | ||
18 | |||
19 | #define S3C2410_WTCON S3C2410_WDOGREG(0x00) | ||
20 | #define S3C2410_WTDAT S3C2410_WDOGREG(0x04) | ||
21 | #define S3C2410_WTCNT S3C2410_WDOGREG(0x08) | ||
22 | |||
23 | /* the watchdog can either generate a reset pulse, or an | ||
24 | * interrupt. | ||
25 | */ | ||
26 | |||
27 | #define S3C2410_WTCON_RSTEN (0x01) | ||
28 | #define S3C2410_WTCON_INTEN (1<<2) | ||
29 | #define S3C2410_WTCON_ENABLE (1<<5) | ||
30 | |||
31 | #define S3C2410_WTCON_DIV16 (0<<3) | ||
32 | #define S3C2410_WTCON_DIV32 (1<<3) | ||
33 | #define S3C2410_WTCON_DIV64 (2<<3) | ||
34 | #define S3C2410_WTCON_DIV128 (3<<3) | ||
35 | |||
36 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) | ||
37 | #define S3C2410_WTCON_PRESCALE_MASK (0xff00) | ||
38 | |||
39 | #endif /* __ASM_ARCH_REGS_WATCHDOG_H */ | ||
40 | |||
41 | |||
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h index 1c74ef17da33..63891786dfa0 100644 --- a/include/asm-arm/arch-s3c2410/system.h +++ b/include/asm-arm/arch-s3c2410/system.h | |||
@@ -17,7 +17,7 @@ | |||
17 | #include <asm/arch/idle.h> | 17 | #include <asm/arch/idle.h> |
18 | #include <asm/arch/reset.h> | 18 | #include <asm/arch/reset.h> |
19 | 19 | ||
20 | #include <asm/arch/regs-watchdog.h> | 20 | #include <asm/plat-s3c/regs-watchdog.h> |
21 | #include <asm/arch/regs-clock.h> | 21 | #include <asm/arch/regs-clock.h> |
22 | 22 | ||
23 | void (*s3c24xx_idle)(void); | 23 | void (*s3c24xx_idle)(void); |
diff --git a/include/asm-arm/arch-s3c2410/udc.h b/include/asm-arm/arch-s3c2410/udc.h deleted file mode 100644 index b8aa6cb69b58..000000000000 --- a/include/asm-arm/arch-s3c2410/udc.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/udc.h | ||
2 | * | ||
3 | * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> | ||
4 | * | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * | ||
11 | * Changelog: | ||
12 | * 14-Mar-2005 RTP Created file | ||
13 | * 02-Aug-2005 RTP File rename | ||
14 | * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum | ||
15 | * 18-Jan-2007 HMW Add per-platform vbus_draw function | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARM_ARCH_UDC_H | ||
19 | #define __ASM_ARM_ARCH_UDC_H | ||
20 | |||
21 | enum s3c2410_udc_cmd_e { | ||
22 | S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */ | ||
23 | S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */ | ||
24 | S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */ | ||
25 | }; | ||
26 | |||
27 | struct s3c2410_udc_mach_info { | ||
28 | void (*udc_command)(enum s3c2410_udc_cmd_e); | ||
29 | void (*vbus_draw)(unsigned int ma); | ||
30 | unsigned int vbus_pin; | ||
31 | unsigned char vbus_pin_inverted; | ||
32 | }; | ||
33 | |||
34 | extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *); | ||
35 | |||
36 | #endif /* __ASM_ARM_ARCH_UDC_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h index dcb2cef38f50..48a5731ee988 100644 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ b/include/asm-arm/arch-s3c2410/uncompress.h | |||
@@ -1,6 +1,7 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c2410/uncompress.h | 1 | /* linux/include/asm-arm/arch-s3c2410/uncompress.h |
2 | * | 2 | * |
3 | * Copyright (c) 2003 Simtec Electronics | 3 | * Copyright (c) 2003, 2007 Simtec Electronics |
4 | * http://armlinux.simtec.co.uk/ | ||
4 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | 6 | * |
6 | * S3C2410 - uncompress code | 7 | * S3C2410 - uncompress code |
@@ -13,153 +14,39 @@ | |||
13 | #ifndef __ASM_ARCH_UNCOMPRESS_H | 14 | #ifndef __ASM_ARCH_UNCOMPRESS_H |
14 | #define __ASM_ARCH_UNCOMPRESS_H | 15 | #define __ASM_ARCH_UNCOMPRESS_H |
15 | 16 | ||
16 | typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ | 17 | #include <asm/arch/regs-gpio.h> |
17 | |||
18 | /* defines for UART registers */ | ||
19 | #include "asm/arch/regs-serial.h" | ||
20 | #include "asm/arch/regs-gpio.h" | ||
21 | #include "asm/arch/regs-watchdog.h" | ||
22 | |||
23 | #include <asm/arch/map.h> | 18 | #include <asm/arch/map.h> |
24 | 19 | ||
25 | /* working in physical space... */ | 20 | /* working in physical space... */ |
26 | #undef S3C2410_GPIOREG | 21 | #undef S3C2410_GPIOREG |
27 | #undef S3C2410_WDOGREG | ||
28 | |||
29 | #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) | 22 | #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) |
30 | #define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x))) | ||
31 | 23 | ||
32 | /* how many bytes we allow into the FIFO at a time in FIFO mode */ | 24 | #include <asm/plat-s3c/uncompress.h> |
33 | #define FIFO_MAX (14) | ||
34 | 25 | ||
35 | #define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT) | 26 | static inline int is_arm926(void) |
36 | |||
37 | static __inline__ void | ||
38 | uart_wr(unsigned int reg, unsigned int val) | ||
39 | { | 27 | { |
40 | volatile unsigned int *ptr; | 28 | unsigned int cpuid; |
41 | |||
42 | ptr = (volatile unsigned int *)(reg + uart_base); | ||
43 | *ptr = val; | ||
44 | } | ||
45 | 29 | ||
46 | static __inline__ unsigned int | 30 | asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid)); |
47 | uart_rd(unsigned int reg) | ||
48 | { | ||
49 | volatile unsigned int *ptr; | ||
50 | 31 | ||
51 | ptr = (volatile unsigned int *)(reg + uart_base); | 32 | return ((cpuid & 0xff0) == 0x260); |
52 | return *ptr; | ||
53 | } | 33 | } |
54 | 34 | ||
55 | 35 | static void arch_detect_cpu(void) | |
56 | /* we can deal with the case the UARTs are being run | ||
57 | * in FIFO mode, so that we don't hold up our execution | ||
58 | * waiting for tx to happen... | ||
59 | */ | ||
60 | |||
61 | static void putc(int ch) | ||
62 | { | 36 | { |
63 | int cpuid = S3C2410_GSTATUS1_2410; | 37 | unsigned int cpuid; |
64 | 38 | ||
65 | #ifndef CONFIG_CPU_S3C2400 | ||
66 | cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); | 39 | cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); |
67 | cpuid &= S3C2410_GSTATUS1_IDMASK; | 40 | cpuid &= S3C2410_GSTATUS1_IDMASK; |
68 | #endif | ||
69 | |||
70 | if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { | ||
71 | int level; | ||
72 | |||
73 | while (1) { | ||
74 | level = uart_rd(S3C2410_UFSTAT); | ||
75 | |||
76 | if (cpuid == S3C2410_GSTATUS1_2440 || | ||
77 | cpuid == S3C2410_GSTATUS1_2442) { | ||
78 | level &= S3C2440_UFSTAT_TXMASK; | ||
79 | level >>= S3C2440_UFSTAT_TXSHIFT; | ||
80 | } else { | ||
81 | level &= S3C2410_UFSTAT_TXMASK; | ||
82 | level >>= S3C2410_UFSTAT_TXSHIFT; | ||
83 | } | ||
84 | |||
85 | if (level < FIFO_MAX) | ||
86 | break; | ||
87 | } | ||
88 | 41 | ||
42 | if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || | ||
43 | cpuid == S3C2410_GSTATUS1_2442) { | ||
44 | fifo_mask = S3C2440_UFSTAT_TXMASK; | ||
45 | fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; | ||
89 | } else { | 46 | } else { |
90 | /* not using fifos */ | 47 | fifo_mask = S3C2410_UFSTAT_TXMASK; |
91 | 48 | fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; | |
92 | while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE) | ||
93 | barrier(); | ||
94 | } | 49 | } |
95 | |||
96 | /* write byte to transmission register */ | ||
97 | uart_wr(S3C2410_UTXH, ch); | ||
98 | } | 50 | } |
99 | 51 | ||
100 | static inline void flush(void) | ||
101 | { | ||
102 | } | ||
103 | |||
104 | #define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) | ||
105 | |||
106 | /* CONFIG_S3C2410_BOOT_WATCHDOG | ||
107 | * | ||
108 | * Simple boot-time watchdog setup, to reboot the system if there is | ||
109 | * any problem with the boot process | ||
110 | */ | ||
111 | |||
112 | #ifdef CONFIG_S3C2410_BOOT_WATCHDOG | ||
113 | |||
114 | #define WDOG_COUNT (0xff00) | ||
115 | |||
116 | static inline void arch_decomp_wdog(void) | ||
117 | { | ||
118 | __raw_writel(WDOG_COUNT, S3C2410_WTCNT); | ||
119 | } | ||
120 | |||
121 | static void arch_decomp_wdog_start(void) | ||
122 | { | ||
123 | __raw_writel(WDOG_COUNT, S3C2410_WTDAT); | ||
124 | __raw_writel(WDOG_COUNT, S3C2410_WTCNT); | ||
125 | __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); | ||
126 | } | ||
127 | |||
128 | #else | ||
129 | #define arch_decomp_wdog_start() | ||
130 | #define arch_decomp_wdog() | ||
131 | #endif | ||
132 | |||
133 | #ifdef CONFIG_S3C2410_BOOT_ERROR_RESET | ||
134 | |||
135 | static void arch_decomp_error(const char *x) | ||
136 | { | ||
137 | putstr("\n\n"); | ||
138 | putstr(x); | ||
139 | putstr("\n\n -- System resetting\n"); | ||
140 | |||
141 | __raw_writel(0x4000, S3C2410_WTDAT); | ||
142 | __raw_writel(0x4000, S3C2410_WTCNT); | ||
143 | __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); | ||
144 | |||
145 | while(1); | ||
146 | } | ||
147 | |||
148 | #define arch_error arch_decomp_error | ||
149 | #endif | ||
150 | |||
151 | static void error(char *err); | ||
152 | |||
153 | static void | ||
154 | arch_decomp_setup(void) | ||
155 | { | ||
156 | /* we may need to setup the uart(s) here if we are not running | ||
157 | * on an BAST... the BAST will have left the uarts configured | ||
158 | * after calling linux. | ||
159 | */ | ||
160 | |||
161 | arch_decomp_wdog_start(); | ||
162 | } | ||
163 | |||
164 | |||
165 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | 52 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ |