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-rw-r--r--include/asm-arm/arch-s3c2410/anubis-map.h10
-rw-r--r--include/asm-arm/arch-s3c2410/fb.h3
-rw-r--r--include/asm-arm/arch-s3c2410/hardware.h7
-rw-r--r--include/asm-arm/arch-s3c2410/io.h60
-rw-r--r--include/asm-arm/arch-s3c2410/memory.h4
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h21
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h245
-rw-r--r--include/asm-arm/arch-s3c2410/regs-iis.h1
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h22
9 files changed, 331 insertions, 42 deletions
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h
index 97741d6e506a..d529ffda8599 100644
--- a/include/asm-arm/arch-s3c2410/anubis-map.h
+++ b/include/asm-arm/arch-s3c2410/anubis-map.h
@@ -20,22 +20,22 @@
20 20
21/* start peripherals off after the S3C2410 */ 21/* start peripherals off after the S3C2410 */
22 22
23#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x02000000)) 23#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
24 24
25#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) 25#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
26 26
27/* we put the CPLD registers next, to get them out of the way */ 27/* we put the CPLD registers next, to get them out of the way */
28 28
29#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01300000 */ 29#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */
30#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) 30#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD)
31 31
32#define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01400000 */ 32#define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01900000 */
33#define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD) 33#define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD)
34 34
35#define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01500000 */ 35#define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01A00000 */
36#define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD) 36#define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD)
37 37
38#define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01600000 */ 38#define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */
39#define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD) 39#define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD)
40 40
41#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) 41#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h
index ac57bc887d82..4790491ba9d0 100644
--- a/include/asm-arm/arch-s3c2410/fb.h
+++ b/include/asm-arm/arch-s3c2410/fb.h
@@ -13,6 +13,7 @@
13 * 07-Sep-2004 RTP Created file 13 * 07-Sep-2004 RTP Created file
14 * 03-Nov-2004 BJD Updated and minor cleanups 14 * 03-Nov-2004 BJD Updated and minor cleanups
15 * 03-Aug-2005 RTP Renamed to fb.h 15 * 03-Aug-2005 RTP Renamed to fb.h
16 * 26-Oct-2005 BJD Changed name of platdata init
16*/ 17*/
17 18
18#ifndef __ASM_ARM_FB_H 19#ifndef __ASM_ARM_FB_H
@@ -64,6 +65,6 @@ struct s3c2410fb_mach_info {
64 unsigned long lpcsel; 65 unsigned long lpcsel;
65}; 66};
66 67
67void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info); 68extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
68 69
69#endif /* __ASM_ARM_FB_H */ 70#endif /* __ASM_ARM_FB_H */
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
index 48a39918a760..1c9de29cafef 100644
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -92,6 +92,13 @@ extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
92 92
93extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); 93extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
94 94
95#ifdef CONFIG_CPU_S3C2440
96
97extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
98
99#endif /* CONFIG_CPU_S3C2440 */
100
101
95#endif /* __ASSEMBLY__ */ 102#endif /* __ASSEMBLY__ */
96 103
97#include <asm/sizes.h> 104#include <asm/sizes.h>
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h
index 418233a7ee6f..16fbc8afffd9 100644
--- a/include/asm-arm/arch-s3c2410/io.h
+++ b/include/asm-arm/arch-s3c2410/io.h
@@ -9,12 +9,14 @@
9 * 06-Dec-1997 RMK Created. 9 * 06-Dec-1997 RMK Created.
10 * 02-Sep-2003 BJD Modified for S3C2410 10 * 02-Sep-2003 BJD Modified for S3C2410
11 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA 11 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
12 * 12 * 13-Oct-2005 BJD Fixed problems with LDRH/STRH offset range
13 */ 13 */
14 14
15#ifndef __ASM_ARM_ARCH_IO_H 15#ifndef __ASM_ARM_ARCH_IO_H
16#define __ASM_ARM_ARCH_IO_H 16#define __ASM_ARM_ARCH_IO_H
17 17
18#include <asm/hardware.h>
19
18#define IO_SPACE_LIMIT 0xffffffff 20#define IO_SPACE_LIMIT 0xffffffff
19 21
20/* 22/*
@@ -97,7 +99,7 @@ DECLARE_IO(int,l,"")
97 else \ 99 else \
98 __asm__ __volatile__( \ 100 __asm__ __volatile__( \
99 "strb %0, [%1, #0] @ outbc" \ 101 "strb %0, [%1, #0] @ outbc" \
100 : : "r" (value), "r" ((port))); \ 102 : : "r" (value), "r" ((port))); \
101}) 103})
102 104
103#define __inbc(port) \ 105#define __inbc(port) \
@@ -110,35 +112,61 @@ DECLARE_IO(int,l,"")
110 else \ 112 else \
111 __asm__ __volatile__( \ 113 __asm__ __volatile__( \
112 "ldrb %0, [%1, #0] @ inbc" \ 114 "ldrb %0, [%1, #0] @ inbc" \
113 : "=r" (result) : "r" ((port))); \ 115 : "=r" (result) : "r" ((port))); \
114 result; \ 116 result; \
115}) 117})
116 118
117#define __outwc(value,port) \ 119#define __outwc(value,port) \
118({ \ 120({ \
119 unsigned long v = value; \ 121 unsigned long v = value; \
120 if (__PORT_PCIO((port))) \ 122 if (__PORT_PCIO((port))) { \
121 __asm__ __volatile__( \ 123 if ((port) < 256 && (port) > -256) \
122 "strh %0, [%1, %2] @ outwc" \ 124 __asm__ __volatile__( \
123 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ 125 "strh %0, [%1, %2] @ outwc" \
124 else \ 126 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
127 else if ((port) > 0) \
128 __asm__ __volatile__( \
129 "strh %0, [%1, %2] @ outwc" \
130 : : "r" (v), \
131 "r" (PCIO_BASE + ((port) & ~0xff)), \
132 "Jr" (((port) & 0xff))); \
133 else \
134 __asm__ __volatile__( \
135 "strh %0, [%1, #0] @ outwc" \
136 : : "r" (v), \
137 "r" (PCIO_BASE + (port))); \
138 } else \
125 __asm__ __volatile__( \ 139 __asm__ __volatile__( \
126 "strh %0, [%1, #0] @ outwc" \ 140 "strh %0, [%1, #0] @ outwc" \
127 : : "r" (v), "r" ((port))); \ 141 : : "r" (v), "r" ((port))); \
128}) 142})
129 143
130#define __inwc(port) \ 144#define __inwc(port) \
131({ \ 145({ \
132 unsigned short result; \ 146 unsigned short result; \
133 if (__PORT_PCIO((port))) \ 147 if (__PORT_PCIO((port))) { \
134 __asm__ __volatile__( \ 148 if ((port) < 256 && (port) > -256 ) \
135 "ldrh %0, [%1, %2] @ inwc" \ 149 __asm__ __volatile__( \
136 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ 150 "ldrh %0, [%1, %2] @ inwc" \
137 else \ 151 : "=r" (result) \
152 : "r" (PCIO_BASE), \
153 "Jr" ((port))); \
154 else if ((port) > 0) \
155 __asm__ __volatile__( \
156 "ldrh %0, [%1, %2] @ inwc" \
157 : "=r" (result) \
158 : "r" (PCIO_BASE + ((port) & ~0xff)), \
159 "Jr" (((port) & 0xff))); \
160 else \
161 __asm__ __volatile__( \
162 "ldrh %0, [%1, #0] @ inwc" \
163 : "=r" (result) \
164 : "r" (PCIO_BASE + ((port)))); \
165 } else \
138 __asm__ __volatile__( \ 166 __asm__ __volatile__( \
139 "ldrh %0, [%1, #0] @ inwc" \ 167 "ldrh %0, [%1, #0] @ inwc" \
140 : "=r" (result) : "r" ((port))); \ 168 : "=r" (result) : "r" ((port))); \
141 result; \ 169 result; \
142}) 170})
143 171
144#define __outlc(value,port) \ 172#define __outlc(value,port) \
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
index 3380ab1d0749..6ab834a14c8e 100644
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -28,9 +28,9 @@
28 * and at 0x0C000000 for S3C2400 28 * and at 0x0C000000 for S3C2400
29 */ 29 */
30#ifdef CONFIG_CPU_S3C2400 30#ifdef CONFIG_CPU_S3C2400
31#define PHYS_OFFSET (0x0C000000UL) 31#define PHYS_OFFSET UL(0x0C000000)
32#else 32#else
33#define PHYS_OFFSET (0x30000000UL) 33#define PHYS_OFFSET UL(0x30000000)
34#endif 34#endif
35 35
36/* 36/*
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 16f4c3cc1388..34360706e016 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -18,7 +18,9 @@
18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) 18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA 19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
20 * 27-Aug-2005 Ben Dooks Add clock-slow info 20 * 27-Aug-2005 Ben Dooks Add clock-slow info
21 */ 21 * 20-Oct-2005 Ben Dooks Fixed overflow in PLL (Guillaume Gourat)
22 * 20-Oct-2005 Ben Dooks Add masks for DCLK (Guillaume Gourat)
23*/
22 24
23#ifndef __ASM_ARM_REGS_CLOCK 25#ifndef __ASM_ARM_REGS_CLOCK
24#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" 26#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
@@ -66,11 +68,16 @@
66#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) 68#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
67#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) 69#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
68#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) 70#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
71#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
72#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
69 73
70#define S3C2410_DCLKCON_DCLK1EN (1<<16) 74#define S3C2410_DCLKCON_DCLK1EN (1<<16)
71#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) 75#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
72#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) 76#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
73#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) 77#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
78#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
79#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
80#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
74 81
75#define S3C2410_CLKDIVN_PDIVN (1<<0) 82#define S3C2410_CLKDIVN_PDIVN (1<<0)
76#define S3C2410_CLKDIVN_HDIVN (1<<1) 83#define S3C2410_CLKDIVN_HDIVN (1<<1)
@@ -83,10 +90,13 @@
83 90
84#ifndef __ASSEMBLY__ 91#ifndef __ASSEMBLY__
85 92
93#include <asm/div64.h>
94
86static inline unsigned int 95static inline unsigned int
87s3c2410_get_pll(int pllval, int baseclk) 96s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
88{ 97{
89 int mdiv, pdiv, sdiv; 98 unsigned int mdiv, pdiv, sdiv;
99 uint64_t fvco;
90 100
91 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; 101 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
92 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; 102 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
@@ -96,7 +106,10 @@ s3c2410_get_pll(int pllval, int baseclk)
96 pdiv &= S3C2410_PLLCON_PDIVMASK; 106 pdiv &= S3C2410_PLLCON_PDIVMASK;
97 sdiv &= S3C2410_PLLCON_SDIVMASK; 107 sdiv &= S3C2410_PLLCON_SDIVMASK;
98 108
99 return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv); 109 fvco = (uint64_t)baseclk * (mdiv + 8);
110 do_div(fvco, (pdiv + 2) << sdiv);
111
112 return (unsigned int)fvco;
100} 113}
101 114
102#endif /* __ASSEMBLY__ */ 115#endif /* __ASSEMBLY__ */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 2053cbacffc3..7f1be48ad67e 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -20,6 +20,8 @@
20 * 18-11-2004 BJD Added S3C2440 AC97 controls 20 * 18-11-2004 BJD Added S3C2440 AC97 controls
21 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA 21 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
22 * 28-Mar-2005 LCVR Fixed definition of GPB10 22 * 28-Mar-2005 LCVR Fixed definition of GPB10
23 * 26-Oct-2005 BJD Added generic configuration types
24 * 27-Nov-2005 LCVR Added definitions to S3C2400 registers
23*/ 25*/
24 26
25 27
@@ -43,17 +45,26 @@
43/* general configuration options */ 45/* general configuration options */
44 46
45#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) 47#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
48#define S3C2410_GPIO_INPUT (0xFFFFFFF0)
49#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
50#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
51#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
52#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
46 53
47/* configure GPIO ports A..G */ 54/* configure GPIO ports A..G */
48 55
49#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) 56#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
50 57
51/* port A - 22bits, zero in bit X makes pin X output 58/* port A - S3C2410: 22bits, zero in bit X makes pin X output
59 * S3C2400: 18bits, zero in bit X makes pin X output
52 * 1 makes port special function, this is default 60 * 1 makes port special function, this is default
53*/ 61*/
54#define S3C2410_GPACON S3C2410_GPIOREG(0x00) 62#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
55#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) 63#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
56 64
65#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
66#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
67
57#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) 68#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
58#define S3C2410_GPA0_OUT (0<<0) 69#define S3C2410_GPA0_OUT (0<<0)
59#define S3C2410_GPA0_ADDR0 (1<<0) 70#define S3C2410_GPA0_ADDR0 (1<<0)
@@ -97,34 +108,42 @@
97#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) 108#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
98#define S3C2410_GPA10_OUT (0<<10) 109#define S3C2410_GPA10_OUT (0<<10)
99#define S3C2410_GPA10_ADDR25 (1<<10) 110#define S3C2410_GPA10_ADDR25 (1<<10)
111#define S3C2400_GPA10_SCKE (1<<10)
100 112
101#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) 113#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
102#define S3C2410_GPA11_OUT (0<<11) 114#define S3C2410_GPA11_OUT (0<<11)
103#define S3C2410_GPA11_ADDR26 (1<<11) 115#define S3C2410_GPA11_ADDR26 (1<<11)
116#define S3C2400_GPA11_nCAS0 (1<<11)
104 117
105#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) 118#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
106#define S3C2410_GPA12_OUT (0<<12) 119#define S3C2410_GPA12_OUT (0<<12)
107#define S3C2410_GPA12_nGCS1 (1<<12) 120#define S3C2410_GPA12_nGCS1 (1<<12)
121#define S3C2400_GPA12_nCAS1 (1<<12)
108 122
109#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) 123#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
110#define S3C2410_GPA13_OUT (0<<13) 124#define S3C2410_GPA13_OUT (0<<13)
111#define S3C2410_GPA13_nGCS2 (1<<13) 125#define S3C2410_GPA13_nGCS2 (1<<13)
126#define S3C2400_GPA13_nGCS1 (1<<13)
112 127
113#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) 128#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
114#define S3C2410_GPA14_OUT (0<<14) 129#define S3C2410_GPA14_OUT (0<<14)
115#define S3C2410_GPA14_nGCS3 (1<<14) 130#define S3C2410_GPA14_nGCS3 (1<<14)
131#define S3C2400_GPA14_nGCS2 (1<<14)
116 132
117#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) 133#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
118#define S3C2410_GPA15_OUT (0<<15) 134#define S3C2410_GPA15_OUT (0<<15)
119#define S3C2410_GPA15_nGCS4 (1<<15) 135#define S3C2410_GPA15_nGCS4 (1<<15)
136#define S3C2400_GPA15_nGCS3 (1<<15)
120 137
121#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) 138#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
122#define S3C2410_GPA16_OUT (0<<16) 139#define S3C2410_GPA16_OUT (0<<16)
123#define S3C2410_GPA16_nGCS5 (1<<16) 140#define S3C2410_GPA16_nGCS5 (1<<16)
141#define S3C2400_GPA16_nGCS4 (1<<16)
124 142
125#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) 143#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
126#define S3C2410_GPA17_OUT (0<<17) 144#define S3C2410_GPA17_OUT (0<<17)
127#define S3C2410_GPA17_CLE (1<<17) 145#define S3C2410_GPA17_CLE (1<<17)
146#define S3C2400_GPA17_nGCS5 (1<<17)
128 147
129#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) 148#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
130#define S3C2410_GPA18_OUT (0<<18) 149#define S3C2410_GPA18_OUT (0<<18)
@@ -146,10 +165,16 @@
146#define S3C2410_GPA22_OUT (0<<22) 165#define S3C2410_GPA22_OUT (0<<22)
147#define S3C2410_GPA22_nFCE (1<<22) 166#define S3C2410_GPA22_nFCE (1<<22)
148 167
149/* 0x08 and 0x0c are reserved */ 168/* 0x08 and 0x0c are reserved on S3C2410 */
150 169
151/* GPB is 10 IO pins, each configured by 2 bits each in GPBCON. 170/* S3C2410:
171 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
152 * 00 = input, 01 = output, 10=special function, 11=reserved 172 * 00 = input, 01 = output, 10=special function, 11=reserved
173
174 * S3C2400:
175 * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
176 * 00 = input, 01 = output, 10=data, 11=special function
177
153 * bit 0,1 = pin 0, 2,3= pin 1... 178 * bit 0,1 = pin 0, 2,3= pin 1...
154 * 179 *
155 * CPBUP = pull up resistor control, 1=disabled, 0=enabled 180 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
@@ -159,63 +184,113 @@
159#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) 184#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
160#define S3C2410_GPBUP S3C2410_GPIOREG(0x18) 185#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
161 186
187#define S3C2400_GPBCON S3C2410_GPIOREG(0x08)
188#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)
189#define S3C2400_GPBUP S3C2410_GPIOREG(0x10)
190
162/* no i/o pin in port b can have value 3! */ 191/* no i/o pin in port b can have value 3! */
163 192
164#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) 193#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
165#define S3C2410_GPB0_INP (0x00 << 0) 194#define S3C2410_GPB0_INP (0x00 << 0)
166#define S3C2410_GPB0_OUTP (0x01 << 0) 195#define S3C2410_GPB0_OUTP (0x01 << 0)
167#define S3C2410_GPB0_TOUT0 (0x02 << 0) 196#define S3C2410_GPB0_TOUT0 (0x02 << 0)
197#define S3C2400_GPB0_DATA16 (0x02 << 0)
168 198
169#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) 199#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
170#define S3C2410_GPB1_INP (0x00 << 2) 200#define S3C2410_GPB1_INP (0x00 << 2)
171#define S3C2410_GPB1_OUTP (0x01 << 2) 201#define S3C2410_GPB1_OUTP (0x01 << 2)
172#define S3C2410_GPB1_TOUT1 (0x02 << 2) 202#define S3C2410_GPB1_TOUT1 (0x02 << 2)
203#define S3C2400_GPB1_DATA17 (0x02 << 2)
173 204
174#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) 205#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
175#define S3C2410_GPB2_INP (0x00 << 4) 206#define S3C2410_GPB2_INP (0x00 << 4)
176#define S3C2410_GPB2_OUTP (0x01 << 4) 207#define S3C2410_GPB2_OUTP (0x01 << 4)
177#define S3C2410_GPB2_TOUT2 (0x02 << 4) 208#define S3C2410_GPB2_TOUT2 (0x02 << 4)
209#define S3C2400_GPB2_DATA18 (0x02 << 4)
210#define S3C2400_GPB2_TCLK1 (0x03 << 4)
178 211
179#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) 212#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
180#define S3C2410_GPB3_INP (0x00 << 6) 213#define S3C2410_GPB3_INP (0x00 << 6)
181#define S3C2410_GPB3_OUTP (0x01 << 6) 214#define S3C2410_GPB3_OUTP (0x01 << 6)
182#define S3C2410_GPB3_TOUT3 (0x02 << 6) 215#define S3C2410_GPB3_TOUT3 (0x02 << 6)
216#define S3C2400_GPB3_DATA19 (0x02 << 6)
217#define S3C2400_GPB3_TXD1 (0x03 << 6)
183 218
184#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) 219#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
185#define S3C2410_GPB4_INP (0x00 << 8) 220#define S3C2410_GPB4_INP (0x00 << 8)
186#define S3C2410_GPB4_OUTP (0x01 << 8) 221#define S3C2410_GPB4_OUTP (0x01 << 8)
187#define S3C2410_GPB4_TCLK0 (0x02 << 8) 222#define S3C2410_GPB4_TCLK0 (0x02 << 8)
223#define S3C2400_GPB4_DATA20 (0x02 << 8)
188#define S3C2410_GPB4_MASK (0x03 << 8) 224#define S3C2410_GPB4_MASK (0x03 << 8)
225#define S3C2400_GPB4_RXD1 (0x03 << 8)
226#define S3C2400_GPB4_MASK (0x03 << 8)
189 227
190#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) 228#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
191#define S3C2410_GPB5_INP (0x00 << 10) 229#define S3C2410_GPB5_INP (0x00 << 10)
192#define S3C2410_GPB5_OUTP (0x01 << 10) 230#define S3C2410_GPB5_OUTP (0x01 << 10)
193#define S3C2410_GPB5_nXBACK (0x02 << 10) 231#define S3C2410_GPB5_nXBACK (0x02 << 10)
232#define S3C2400_GPB5_DATA21 (0x02 << 10)
233#define S3C2400_GPB5_nCTS1 (0x03 << 10)
194 234
195#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) 235#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
196#define S3C2410_GPB6_INP (0x00 << 12) 236#define S3C2410_GPB6_INP (0x00 << 12)
197#define S3C2410_GPB6_OUTP (0x01 << 12) 237#define S3C2410_GPB6_OUTP (0x01 << 12)
198#define S3C2410_GPB6_nXBREQ (0x02 << 12) 238#define S3C2410_GPB6_nXBREQ (0x02 << 12)
239#define S3C2400_GPB6_DATA22 (0x02 << 12)
240#define S3C2400_GPB6_nRTS1 (0x03 << 12)
199 241
200#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) 242#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
201#define S3C2410_GPB7_INP (0x00 << 14) 243#define S3C2410_GPB7_INP (0x00 << 14)
202#define S3C2410_GPB7_OUTP (0x01 << 14) 244#define S3C2410_GPB7_OUTP (0x01 << 14)
203#define S3C2410_GPB7_nXDACK1 (0x02 << 14) 245#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
246#define S3C2400_GPB7_DATA23 (0x02 << 14)
204 247
205#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) 248#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
206#define S3C2410_GPB8_INP (0x00 << 16) 249#define S3C2410_GPB8_INP (0x00 << 16)
207#define S3C2410_GPB8_OUTP (0x01 << 16) 250#define S3C2410_GPB8_OUTP (0x01 << 16)
208#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) 251#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
252#define S3C2400_GPB8_DATA24 (0x02 << 16)
209 253
210#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) 254#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
211#define S3C2410_GPB9_INP (0x00 << 18) 255#define S3C2410_GPB9_INP (0x00 << 18)
212#define S3C2410_GPB9_OUTP (0x01 << 18) 256#define S3C2410_GPB9_OUTP (0x01 << 18)
213#define S3C2410_GPB9_nXDACK0 (0x02 << 18) 257#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
258#define S3C2400_GPB9_DATA25 (0x02 << 18)
259#define S3C2400_GPB9_I2SSDI (0x03 << 18)
214 260
215#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) 261#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
216#define S3C2410_GPB10_INP (0x00 << 20) 262#define S3C2410_GPB10_INP (0x00 << 20)
217#define S3C2410_GPB10_OUTP (0x01 << 20) 263#define S3C2410_GPB10_OUTP (0x01 << 20)
218#define S3C2410_GPB10_nXDRE0 (0x02 << 20) 264#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
265#define S3C2400_GPB10_DATA26 (0x02 << 20)
266#define S3C2400_GPB10_nSS (0x03 << 20)
267
268#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
269#define S3C2400_GPB11_INP (0x00 << 22)
270#define S3C2400_GPB11_OUTP (0x01 << 22)
271#define S3C2400_GPB11_DATA27 (0x02 << 22)
272
273#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
274#define S3C2400_GPB12_INP (0x00 << 24)
275#define S3C2400_GPB12_OUTP (0x01 << 24)
276#define S3C2400_GPB12_DATA28 (0x02 << 24)
277
278#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
279#define S3C2400_GPB13_INP (0x00 << 26)
280#define S3C2400_GPB13_OUTP (0x01 << 26)
281#define S3C2400_GPB13_DATA29 (0x02 << 26)
282
283#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
284#define S3C2400_GPB14_INP (0x00 << 28)
285#define S3C2400_GPB14_OUTP (0x01 << 28)
286#define S3C2400_GPB14_DATA30 (0x02 << 28)
287
288#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
289#define S3C2400_GPB15_INP (0x00 << 30)
290#define S3C2400_GPB15_OUTP (0x01 << 30)
291#define S3C2400_GPB15_DATA31 (0x02 << 30)
292
293#define S3C2410_GPB_PUPDIS(x) (1<<(x))
219 294
220/* Port C consits of 16 GPIO/Special function 295/* Port C consits of 16 GPIO/Special function
221 * 296 *
@@ -227,150 +302,193 @@
227#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) 302#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
228#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) 303#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
229 304
305#define S3C2400_GPCCON S3C2410_GPIOREG(0x14)
306#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
307#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
308
230#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) 309#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
231#define S3C2410_GPC0_INP (0x00 << 0) 310#define S3C2410_GPC0_INP (0x00 << 0)
232#define S3C2410_GPC0_OUTP (0x01 << 0) 311#define S3C2410_GPC0_OUTP (0x01 << 0)
233#define S3C2410_GPC0_LEND (0x02 << 0) 312#define S3C2410_GPC0_LEND (0x02 << 0)
313#define S3C2400_GPC0_VD0 (0x02 << 0)
234 314
235#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) 315#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
236#define S3C2410_GPC1_INP (0x00 << 2) 316#define S3C2410_GPC1_INP (0x00 << 2)
237#define S3C2410_GPC1_OUTP (0x01 << 2) 317#define S3C2410_GPC1_OUTP (0x01 << 2)
238#define S3C2410_GPC1_VCLK (0x02 << 2) 318#define S3C2410_GPC1_VCLK (0x02 << 2)
319#define S3C2400_GPC1_VD1 (0x02 << 2)
239 320
240#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) 321#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
241#define S3C2410_GPC2_INP (0x00 << 4) 322#define S3C2410_GPC2_INP (0x00 << 4)
242#define S3C2410_GPC2_OUTP (0x01 << 4) 323#define S3C2410_GPC2_OUTP (0x01 << 4)
243#define S3C2410_GPC2_VLINE (0x02 << 4) 324#define S3C2410_GPC2_VLINE (0x02 << 4)
325#define S3C2400_GPC2_VD2 (0x02 << 4)
244 326
245#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) 327#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
246#define S3C2410_GPC3_INP (0x00 << 6) 328#define S3C2410_GPC3_INP (0x00 << 6)
247#define S3C2410_GPC3_OUTP (0x01 << 6) 329#define S3C2410_GPC3_OUTP (0x01 << 6)
248#define S3C2410_GPC3_VFRAME (0x02 << 6) 330#define S3C2410_GPC3_VFRAME (0x02 << 6)
331#define S3C2400_GPC3_VD3 (0x02 << 6)
249 332
250#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) 333#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
251#define S3C2410_GPC4_INP (0x00 << 8) 334#define S3C2410_GPC4_INP (0x00 << 8)
252#define S3C2410_GPC4_OUTP (0x01 << 8) 335#define S3C2410_GPC4_OUTP (0x01 << 8)
253#define S3C2410_GPC4_VM (0x02 << 8) 336#define S3C2410_GPC4_VM (0x02 << 8)
337#define S3C2400_GPC4_VD4 (0x02 << 8)
254 338
255#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) 339#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
256#define S3C2410_GPC5_INP (0x00 << 10) 340#define S3C2410_GPC5_INP (0x00 << 10)
257#define S3C2410_GPC5_OUTP (0x01 << 10) 341#define S3C2410_GPC5_OUTP (0x01 << 10)
258#define S3C2410_GPC5_LCDVF0 (0x02 << 10) 342#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
343#define S3C2400_GPC5_VD5 (0x02 << 10)
259 344
260#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) 345#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
261#define S3C2410_GPC6_INP (0x00 << 12) 346#define S3C2410_GPC6_INP (0x00 << 12)
262#define S3C2410_GPC6_OUTP (0x01 << 12) 347#define S3C2410_GPC6_OUTP (0x01 << 12)
263#define S3C2410_GPC6_LCDVF1 (0x02 << 12) 348#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
349#define S3C2400_GPC6_VD6 (0x02 << 12)
264 350
265#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) 351#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
266#define S3C2410_GPC7_INP (0x00 << 14) 352#define S3C2410_GPC7_INP (0x00 << 14)
267#define S3C2410_GPC7_OUTP (0x01 << 14) 353#define S3C2410_GPC7_OUTP (0x01 << 14)
268#define S3C2410_GPC7_LCDVF2 (0x02 << 14) 354#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
355#define S3C2400_GPC7_VD7 (0x02 << 14)
269 356
270#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) 357#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
271#define S3C2410_GPC8_INP (0x00 << 16) 358#define S3C2410_GPC8_INP (0x00 << 16)
272#define S3C2410_GPC8_OUTP (0x01 << 16) 359#define S3C2410_GPC8_OUTP (0x01 << 16)
273#define S3C2410_GPC8_VD0 (0x02 << 16) 360#define S3C2410_GPC8_VD0 (0x02 << 16)
361#define S3C2400_GPC8_VD8 (0x02 << 16)
274 362
275#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) 363#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
276#define S3C2410_GPC9_INP (0x00 << 18) 364#define S3C2410_GPC9_INP (0x00 << 18)
277#define S3C2410_GPC9_OUTP (0x01 << 18) 365#define S3C2410_GPC9_OUTP (0x01 << 18)
278#define S3C2410_GPC9_VD1 (0x02 << 18) 366#define S3C2410_GPC9_VD1 (0x02 << 18)
367#define S3C2400_GPC9_VD9 (0x02 << 18)
279 368
280#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) 369#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
281#define S3C2410_GPC10_INP (0x00 << 20) 370#define S3C2410_GPC10_INP (0x00 << 20)
282#define S3C2410_GPC10_OUTP (0x01 << 20) 371#define S3C2410_GPC10_OUTP (0x01 << 20)
283#define S3C2410_GPC10_VD2 (0x02 << 20) 372#define S3C2410_GPC10_VD2 (0x02 << 20)
373#define S3C2400_GPC10_VD10 (0x02 << 20)
284 374
285#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) 375#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
286#define S3C2410_GPC11_INP (0x00 << 22) 376#define S3C2410_GPC11_INP (0x00 << 22)
287#define S3C2410_GPC11_OUTP (0x01 << 22) 377#define S3C2410_GPC11_OUTP (0x01 << 22)
288#define S3C2410_GPC11_VD3 (0x02 << 22) 378#define S3C2410_GPC11_VD3 (0x02 << 22)
379#define S3C2400_GPC11_VD11 (0x02 << 22)
289 380
290#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) 381#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
291#define S3C2410_GPC12_INP (0x00 << 24) 382#define S3C2410_GPC12_INP (0x00 << 24)
292#define S3C2410_GPC12_OUTP (0x01 << 24) 383#define S3C2410_GPC12_OUTP (0x01 << 24)
293#define S3C2410_GPC12_VD4 (0x02 << 24) 384#define S3C2410_GPC12_VD4 (0x02 << 24)
385#define S3C2400_GPC12_VD12 (0x02 << 24)
294 386
295#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) 387#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
296#define S3C2410_GPC13_INP (0x00 << 26) 388#define S3C2410_GPC13_INP (0x00 << 26)
297#define S3C2410_GPC13_OUTP (0x01 << 26) 389#define S3C2410_GPC13_OUTP (0x01 << 26)
298#define S3C2410_GPC13_VD5 (0x02 << 26) 390#define S3C2410_GPC13_VD5 (0x02 << 26)
391#define S3C2400_GPC13_VD13 (0x02 << 26)
299 392
300#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) 393#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
301#define S3C2410_GPC14_INP (0x00 << 28) 394#define S3C2410_GPC14_INP (0x00 << 28)
302#define S3C2410_GPC14_OUTP (0x01 << 28) 395#define S3C2410_GPC14_OUTP (0x01 << 28)
303#define S3C2410_GPC14_VD6 (0x02 << 28) 396#define S3C2410_GPC14_VD6 (0x02 << 28)
397#define S3C2400_GPC14_VD14 (0x02 << 28)
304 398
305#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) 399#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
306#define S3C2410_GPC15_INP (0x00 << 30) 400#define S3C2410_GPC15_INP (0x00 << 30)
307#define S3C2410_GPC15_OUTP (0x01 << 30) 401#define S3C2410_GPC15_OUTP (0x01 << 30)
308#define S3C2410_GPC15_VD7 (0x02 << 30) 402#define S3C2410_GPC15_VD7 (0x02 << 30)
403#define S3C2400_GPC15_VD15 (0x02 << 30)
404
405#define S3C2410_GPC_PUPDIS(x) (1<<(x))
309 406
310/* Port D consists of 16 GPIO/Special function 407/*
408 * S3C2410: Port D consists of 16 GPIO/Special function
311 * 409 *
312 * almost identical setup to port b, but the special functions are mostly 410 * almost identical setup to port b, but the special functions are mostly
313 * to do with the video system's data. 411 * to do with the video system's data.
412 *
413 * S3C2400: Port D consists of 11 GPIO/Special function
414 *
415 * almost identical setup to port c
314*/ 416*/
315 417
316#define S3C2410_GPDCON S3C2410_GPIOREG(0x30) 418#define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
317#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) 419#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
318#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) 420#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
319 421
422#define S3C2400_GPDCON S3C2410_GPIOREG(0x20)
423#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
424#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
425
320#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) 426#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
321#define S3C2410_GPD0_INP (0x00 << 0) 427#define S3C2410_GPD0_INP (0x00 << 0)
322#define S3C2410_GPD0_OUTP (0x01 << 0) 428#define S3C2410_GPD0_OUTP (0x01 << 0)
323#define S3C2410_GPD0_VD8 (0x02 << 0) 429#define S3C2410_GPD0_VD8 (0x02 << 0)
430#define S3C2400_GPD0_VFRAME (0x02 << 0)
324 431
325#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) 432#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
326#define S3C2410_GPD1_INP (0x00 << 2) 433#define S3C2410_GPD1_INP (0x00 << 2)
327#define S3C2410_GPD1_OUTP (0x01 << 2) 434#define S3C2410_GPD1_OUTP (0x01 << 2)
328#define S3C2410_GPD1_VD9 (0x02 << 2) 435#define S3C2410_GPD1_VD9 (0x02 << 2)
436#define S3C2400_GPD1_VM (0x02 << 2)
329 437
330#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) 438#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
331#define S3C2410_GPD2_INP (0x00 << 4) 439#define S3C2410_GPD2_INP (0x00 << 4)
332#define S3C2410_GPD2_OUTP (0x01 << 4) 440#define S3C2410_GPD2_OUTP (0x01 << 4)
333#define S3C2410_GPD2_VD10 (0x02 << 4) 441#define S3C2410_GPD2_VD10 (0x02 << 4)
442#define S3C2400_GPD2_VLINE (0x02 << 4)
334 443
335#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) 444#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
336#define S3C2410_GPD3_INP (0x00 << 6) 445#define S3C2410_GPD3_INP (0x00 << 6)
337#define S3C2410_GPD3_OUTP (0x01 << 6) 446#define S3C2410_GPD3_OUTP (0x01 << 6)
338#define S3C2410_GPD3_VD11 (0x02 << 6) 447#define S3C2410_GPD3_VD11 (0x02 << 6)
448#define S3C2400_GPD3_VCLK (0x02 << 6)
339 449
340#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) 450#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
341#define S3C2410_GPD4_INP (0x00 << 8) 451#define S3C2410_GPD4_INP (0x00 << 8)
342#define S3C2410_GPD4_OUTP (0x01 << 8) 452#define S3C2410_GPD4_OUTP (0x01 << 8)
343#define S3C2410_GPD4_VD12 (0x02 << 8) 453#define S3C2410_GPD4_VD12 (0x02 << 8)
454#define S3C2400_GPD4_LEND (0x02 << 8)
344 455
345#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) 456#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
346#define S3C2410_GPD5_INP (0x00 << 10) 457#define S3C2410_GPD5_INP (0x00 << 10)
347#define S3C2410_GPD5_OUTP (0x01 << 10) 458#define S3C2410_GPD5_OUTP (0x01 << 10)
348#define S3C2410_GPD5_VD13 (0x02 << 10) 459#define S3C2410_GPD5_VD13 (0x02 << 10)
460#define S3C2400_GPD5_TOUT0 (0x02 << 10)
349 461
350#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) 462#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
351#define S3C2410_GPD6_INP (0x00 << 12) 463#define S3C2410_GPD6_INP (0x00 << 12)
352#define S3C2410_GPD6_OUTP (0x01 << 12) 464#define S3C2410_GPD6_OUTP (0x01 << 12)
353#define S3C2410_GPD6_VD14 (0x02 << 12) 465#define S3C2410_GPD6_VD14 (0x02 << 12)
466#define S3C2400_GPD6_TOUT1 (0x02 << 12)
354 467
355#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) 468#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
356#define S3C2410_GPD7_INP (0x00 << 14) 469#define S3C2410_GPD7_INP (0x00 << 14)
357#define S3C2410_GPD7_OUTP (0x01 << 14) 470#define S3C2410_GPD7_OUTP (0x01 << 14)
358#define S3C2410_GPD7_VD15 (0x02 << 14) 471#define S3C2410_GPD7_VD15 (0x02 << 14)
472#define S3C2400_GPD7_TOUT2 (0x02 << 14)
359 473
360#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) 474#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
361#define S3C2410_GPD8_INP (0x00 << 16) 475#define S3C2410_GPD8_INP (0x00 << 16)
362#define S3C2410_GPD8_OUTP (0x01 << 16) 476#define S3C2410_GPD8_OUTP (0x01 << 16)
363#define S3C2410_GPD8_VD16 (0x02 << 16) 477#define S3C2410_GPD8_VD16 (0x02 << 16)
478#define S3C2400_GPD8_TOUT3 (0x02 << 16)
364 479
365#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) 480#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
366#define S3C2410_GPD9_INP (0x00 << 18) 481#define S3C2410_GPD9_INP (0x00 << 18)
367#define S3C2410_GPD9_OUTP (0x01 << 18) 482#define S3C2410_GPD9_OUTP (0x01 << 18)
368#define S3C2410_GPD9_VD17 (0x02 << 18) 483#define S3C2410_GPD9_VD17 (0x02 << 18)
484#define S3C2400_GPD9_TCLK0 (0x02 << 18)
485#define S3C2410_GPD9_MASK (0x03 << 18)
369 486
370#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) 487#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
371#define S3C2410_GPD10_INP (0x00 << 20) 488#define S3C2410_GPD10_INP (0x00 << 20)
372#define S3C2410_GPD10_OUTP (0x01 << 20) 489#define S3C2410_GPD10_OUTP (0x01 << 20)
373#define S3C2410_GPD10_VD18 (0x02 << 20) 490#define S3C2410_GPD10_VD18 (0x02 << 20)
491#define S3C2400_GPD10_nWAIT (0x02 << 20)
374 492
375#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) 493#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
376#define S3C2410_GPD11_INP (0x00 << 22) 494#define S3C2410_GPD11_INP (0x00 << 22)
@@ -397,37 +515,56 @@
397#define S3C2410_GPD15_OUTP (0x01 << 30) 515#define S3C2410_GPD15_OUTP (0x01 << 30)
398#define S3C2410_GPD15_VD23 (0x02 << 30) 516#define S3C2410_GPD15_VD23 (0x02 << 30)
399 517
400/* Port E consists of 16 GPIO/Special function 518#define S3C2410_GPD_PUPDIS(x) (1<<(x))
519
520/* S3C2410:
521 * Port E consists of 16 GPIO/Special function
401 * 522 *
402 * again, the same as port B, but dealing with I2S, SDI, and 523 * again, the same as port B, but dealing with I2S, SDI, and
403 * more miscellaneous functions 524 * more miscellaneous functions
525 *
526 * S3C2400:
527 * Port E consists of 12 GPIO/Special function
528 *
529 * GPIO / interrupt inputs
404*/ 530*/
405 531
406#define S3C2410_GPECON S3C2410_GPIOREG(0x40) 532#define S3C2410_GPECON S3C2410_GPIOREG(0x40)
407#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) 533#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
408#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) 534#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
409 535
536#define S3C2400_GPECON S3C2410_GPIOREG(0x2C)
537#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
538#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
539
410#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) 540#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
411#define S3C2410_GPE0_INP (0x00 << 0) 541#define S3C2410_GPE0_INP (0x00 << 0)
412#define S3C2410_GPE0_OUTP (0x01 << 0) 542#define S3C2410_GPE0_OUTP (0x01 << 0)
413#define S3C2410_GPE0_I2SLRCK (0x02 << 0) 543#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
544#define S3C2400_GPE0_EINT0 (0x02 << 0)
414#define S3C2410_GPE0_MASK (0x03 << 0) 545#define S3C2410_GPE0_MASK (0x03 << 0)
415 546
416#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) 547#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
417#define S3C2410_GPE1_INP (0x00 << 2) 548#define S3C2410_GPE1_INP (0x00 << 2)
418#define S3C2410_GPE1_OUTP (0x01 << 2) 549#define S3C2410_GPE1_OUTP (0x01 << 2)
419#define S3C2410_GPE1_I2SSCLK (0x02 << 2) 550#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
551#define S3C2400_GPE1_EINT1 (0x02 << 2)
552#define S3C2400_GPE1_nSS (0x03 << 2)
420#define S3C2410_GPE1_MASK (0x03 << 2) 553#define S3C2410_GPE1_MASK (0x03 << 2)
421 554
422#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) 555#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
423#define S3C2410_GPE2_INP (0x00 << 4) 556#define S3C2410_GPE2_INP (0x00 << 4)
424#define S3C2410_GPE2_OUTP (0x01 << 4) 557#define S3C2410_GPE2_OUTP (0x01 << 4)
425#define S3C2410_GPE2_CDCLK (0x02 << 4) 558#define S3C2410_GPE2_CDCLK (0x02 << 4)
559#define S3C2400_GPE2_EINT2 (0x02 << 4)
560#define S3C2400_GPE2_I2SSDI (0x03 << 4)
426 561
427#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) 562#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
428#define S3C2410_GPE3_INP (0x00 << 6) 563#define S3C2410_GPE3_INP (0x00 << 6)
429#define S3C2410_GPE3_OUTP (0x01 << 6) 564#define S3C2410_GPE3_OUTP (0x01 << 6)
430#define S3C2410_GPE3_I2SSDI (0x02 << 6) 565#define S3C2410_GPE3_I2SSDI (0x02 << 6)
566#define S3C2400_GPE3_EINT3 (0x02 << 6)
567#define S3C2400_GPE3_nCTS1 (0x03 << 6)
431#define S3C2410_GPE3_nSS0 (0x03 << 6) 568#define S3C2410_GPE3_nSS0 (0x03 << 6)
432#define S3C2410_GPE3_MASK (0x03 << 6) 569#define S3C2410_GPE3_MASK (0x03 << 6)
433 570
@@ -435,6 +572,8 @@
435#define S3C2410_GPE4_INP (0x00 << 8) 572#define S3C2410_GPE4_INP (0x00 << 8)
436#define S3C2410_GPE4_OUTP (0x01 << 8) 573#define S3C2410_GPE4_OUTP (0x01 << 8)
437#define S3C2410_GPE4_I2SSDO (0x02 << 8) 574#define S3C2410_GPE4_I2SSDO (0x02 << 8)
575#define S3C2400_GPE4_EINT4 (0x02 << 8)
576#define S3C2400_GPE4_nRTS1 (0x03 << 8)
438#define S3C2410_GPE4_I2SSDI (0x03 << 8) 577#define S3C2410_GPE4_I2SSDI (0x03 << 8)
439#define S3C2410_GPE4_MASK (0x03 << 8) 578#define S3C2410_GPE4_MASK (0x03 << 8)
440 579
@@ -442,36 +581,46 @@
442#define S3C2410_GPE5_INP (0x00 << 10) 581#define S3C2410_GPE5_INP (0x00 << 10)
443#define S3C2410_GPE5_OUTP (0x01 << 10) 582#define S3C2410_GPE5_OUTP (0x01 << 10)
444#define S3C2410_GPE5_SDCLK (0x02 << 10) 583#define S3C2410_GPE5_SDCLK (0x02 << 10)
584#define S3C2400_GPE5_EINT5 (0x02 << 10)
585#define S3C2400_GPE5_TCLK1 (0x03 << 10)
445 586
446#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) 587#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
447#define S3C2410_GPE6_INP (0x00 << 12) 588#define S3C2410_GPE6_INP (0x00 << 12)
448#define S3C2410_GPE6_OUTP (0x01 << 12) 589#define S3C2410_GPE6_OUTP (0x01 << 12)
449#define S3C2410_GPE6_SDCMD (0x02 << 12) 590#define S3C2410_GPE6_SDCMD (0x02 << 12)
591#define S3C2400_GPE6_EINT6 (0x02 << 12)
450 592
451#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) 593#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
452#define S3C2410_GPE7_INP (0x00 << 14) 594#define S3C2410_GPE7_INP (0x00 << 14)
453#define S3C2410_GPE7_OUTP (0x01 << 14) 595#define S3C2410_GPE7_OUTP (0x01 << 14)
454#define S3C2410_GPE7_SDDAT0 (0x02 << 14) 596#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
597#define S3C2400_GPE7_EINT7 (0x02 << 14)
455 598
456#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) 599#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
457#define S3C2410_GPE8_INP (0x00 << 16) 600#define S3C2410_GPE8_INP (0x00 << 16)
458#define S3C2410_GPE8_OUTP (0x01 << 16) 601#define S3C2410_GPE8_OUTP (0x01 << 16)
459#define S3C2410_GPE8_SDDAT1 (0x02 << 16) 602#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
603#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
460 604
461#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) 605#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
462#define S3C2410_GPE9_INP (0x00 << 18) 606#define S3C2410_GPE9_INP (0x00 << 18)
463#define S3C2410_GPE9_OUTP (0x01 << 18) 607#define S3C2410_GPE9_OUTP (0x01 << 18)
464#define S3C2410_GPE9_SDDAT2 (0x02 << 18) 608#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
609#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
610#define S3C2400_GPE9_nXBACK (0x03 << 18)
465 611
466#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) 612#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
467#define S3C2410_GPE10_INP (0x00 << 20) 613#define S3C2410_GPE10_INP (0x00 << 20)
468#define S3C2410_GPE10_OUTP (0x01 << 20) 614#define S3C2410_GPE10_OUTP (0x01 << 20)
469#define S3C2410_GPE10_SDDAT3 (0x02 << 20) 615#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
616#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
470 617
471#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) 618#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
472#define S3C2410_GPE11_INP (0x00 << 22) 619#define S3C2410_GPE11_INP (0x00 << 22)
473#define S3C2410_GPE11_OUTP (0x01 << 22) 620#define S3C2410_GPE11_OUTP (0x01 << 22)
474#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) 621#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
622#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
623#define S3C2400_GPE11_nXBREQ (0x03 << 22)
475 624
476#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) 625#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
477#define S3C2410_GPE12_INP (0x00 << 24) 626#define S3C2410_GPE12_INP (0x00 << 24)
@@ -503,7 +652,8 @@
503 652
504#define S3C2410_GPE_PUPDIS(x) (1<<(x)) 653#define S3C2410_GPE_PUPDIS(x) (1<<(x))
505 654
506/* Port F consists of 8 GPIO/Special function 655/* S3C2410:
656 * Port F consists of 8 GPIO/Special function
507 * 657 *
508 * GPIO / interrupt inputs 658 * GPIO / interrupt inputs
509 * 659 *
@@ -511,100 +661,141 @@
511 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined 661 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
512 * 662 *
513 * pull up works like all other ports. 663 * pull up works like all other ports.
664 *
665 * S3C2400:
666 * Port F consists of 7 GPIO/Special function
667 *
668 * GPIO/serial/misc pins
514*/ 669*/
515 670
516#define S3C2410_GPFCON S3C2410_GPIOREG(0x50) 671#define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
517#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) 672#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
518#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) 673#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
519 674
675#define S3C2400_GPFCON S3C2410_GPIOREG(0x38)
676#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
677#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
678
520#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) 679#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
521#define S3C2410_GPF0_INP (0x00 << 0) 680#define S3C2410_GPF0_INP (0x00 << 0)
522#define S3C2410_GPF0_OUTP (0x01 << 0) 681#define S3C2410_GPF0_OUTP (0x01 << 0)
523#define S3C2410_GPF0_EINT0 (0x02 << 0) 682#define S3C2410_GPF0_EINT0 (0x02 << 0)
683#define S3C2400_GPF0_RXD0 (0x02 << 0)
524 684
525#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) 685#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
526#define S3C2410_GPF1_INP (0x00 << 2) 686#define S3C2410_GPF1_INP (0x00 << 2)
527#define S3C2410_GPF1_OUTP (0x01 << 2) 687#define S3C2410_GPF1_OUTP (0x01 << 2)
528#define S3C2410_GPF1_EINT1 (0x02 << 2) 688#define S3C2410_GPF1_EINT1 (0x02 << 2)
689#define S3C2400_GPF1_RXD1 (0x02 << 2)
690#define S3C2400_GPF1_IICSDA (0x03 << 2)
529 691
530#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) 692#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
531#define S3C2410_GPF2_INP (0x00 << 4) 693#define S3C2410_GPF2_INP (0x00 << 4)
532#define S3C2410_GPF2_OUTP (0x01 << 4) 694#define S3C2410_GPF2_OUTP (0x01 << 4)
533#define S3C2410_GPF2_EINT2 (0x02 << 4) 695#define S3C2410_GPF2_EINT2 (0x02 << 4)
696#define S3C2400_GPF2_TXD0 (0x02 << 4)
534 697
535#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) 698#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
536#define S3C2410_GPF3_INP (0x00 << 6) 699#define S3C2410_GPF3_INP (0x00 << 6)
537#define S3C2410_GPF3_OUTP (0x01 << 6) 700#define S3C2410_GPF3_OUTP (0x01 << 6)
538#define S3C2410_GPF3_EINT3 (0x02 << 6) 701#define S3C2410_GPF3_EINT3 (0x02 << 6)
702#define S3C2400_GPF3_TXD1 (0x02 << 6)
703#define S3C2400_GPF3_IICSCL (0x03 << 6)
539 704
540#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) 705#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
541#define S3C2410_GPF4_INP (0x00 << 8) 706#define S3C2410_GPF4_INP (0x00 << 8)
542#define S3C2410_GPF4_OUTP (0x01 << 8) 707#define S3C2410_GPF4_OUTP (0x01 << 8)
543#define S3C2410_GPF4_EINT4 (0x02 << 8) 708#define S3C2410_GPF4_EINT4 (0x02 << 8)
709#define S3C2400_GPF4_nRTS0 (0x02 << 8)
710#define S3C2400_GPF4_nXBACK (0x03 << 8)
544 711
545#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) 712#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
546#define S3C2410_GPF5_INP (0x00 << 10) 713#define S3C2410_GPF5_INP (0x00 << 10)
547#define S3C2410_GPF5_OUTP (0x01 << 10) 714#define S3C2410_GPF5_OUTP (0x01 << 10)
548#define S3C2410_GPF5_EINT5 (0x02 << 10) 715#define S3C2410_GPF5_EINT5 (0x02 << 10)
716#define S3C2400_GPF5_nCTS0 (0x02 << 10)
717#define S3C2400_GPF5_nXBREQ (0x03 << 10)
549 718
550#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) 719#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
551#define S3C2410_GPF6_INP (0x00 << 12) 720#define S3C2410_GPF6_INP (0x00 << 12)
552#define S3C2410_GPF6_OUTP (0x01 << 12) 721#define S3C2410_GPF6_OUTP (0x01 << 12)
553#define S3C2410_GPF6_EINT6 (0x02 << 12) 722#define S3C2410_GPF6_EINT6 (0x02 << 12)
723#define S3C2400_GPF6_CLKOUT (0x02 << 12)
554 724
555#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) 725#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
556#define S3C2410_GPF7_INP (0x00 << 14) 726#define S3C2410_GPF7_INP (0x00 << 14)
557#define S3C2410_GPF7_OUTP (0x01 << 14) 727#define S3C2410_GPF7_OUTP (0x01 << 14)
558#define S3C2410_GPF7_EINT7 (0x02 << 14) 728#define S3C2410_GPF7_EINT7 (0x02 << 14)
559 729
560/* Port G consists of 8 GPIO/IRQ/Special function 730#define S3C2410_GPF_PUPDIS(x) (1<<(x))
731
732/* S3C2410:
733 * Port G consists of 8 GPIO/IRQ/Special function
561 * 734 *
562 * GPGCON has 2 bits for each of the input pins on port F 735 * GPGCON has 2 bits for each of the input pins on port F
563 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func 736 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
564 * 737 *
565 * pull up works like all other ports. 738 * pull up works like all other ports.
739 *
740 * S3C2400:
741 * Port G consists of 10 GPIO/Special function
566*/ 742*/
567 743
568#define S3C2410_GPGCON S3C2410_GPIOREG(0x60) 744#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
569#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) 745#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
570#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) 746#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
571 747
748#define S3C2400_GPGCON S3C2410_GPIOREG(0x44)
749#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
750#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
751
572#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) 752#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
573#define S3C2410_GPG0_INP (0x00 << 0) 753#define S3C2410_GPG0_INP (0x00 << 0)
574#define S3C2410_GPG0_OUTP (0x01 << 0) 754#define S3C2410_GPG0_OUTP (0x01 << 0)
575#define S3C2410_GPG0_EINT8 (0x02 << 0) 755#define S3C2410_GPG0_EINT8 (0x02 << 0)
756#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
576 757
577#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) 758#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
578#define S3C2410_GPG1_INP (0x00 << 2) 759#define S3C2410_GPG1_INP (0x00 << 2)
579#define S3C2410_GPG1_OUTP (0x01 << 2) 760#define S3C2410_GPG1_OUTP (0x01 << 2)
580#define S3C2410_GPG1_EINT9 (0x02 << 2) 761#define S3C2410_GPG1_EINT9 (0x02 << 2)
762#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
581 763
582#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) 764#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
583#define S3C2410_GPG2_INP (0x00 << 4) 765#define S3C2410_GPG2_INP (0x00 << 4)
584#define S3C2410_GPG2_OUTP (0x01 << 4) 766#define S3C2410_GPG2_OUTP (0x01 << 4)
585#define S3C2410_GPG2_EINT10 (0x02 << 4) 767#define S3C2410_GPG2_EINT10 (0x02 << 4)
768#define S3C2400_GPG2_CDCLK (0x02 << 4)
586 769
587#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) 770#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
588#define S3C2410_GPG3_INP (0x00 << 6) 771#define S3C2410_GPG3_INP (0x00 << 6)
589#define S3C2410_GPG3_OUTP (0x01 << 6) 772#define S3C2410_GPG3_OUTP (0x01 << 6)
590#define S3C2410_GPG3_EINT11 (0x02 << 6) 773#define S3C2410_GPG3_EINT11 (0x02 << 6)
774#define S3C2400_GPG3_I2SSDO (0x02 << 6)
775#define S3C2400_GPG3_I2SSDI (0x03 << 6)
591 776
592#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) 777#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
593#define S3C2410_GPG4_INP (0x00 << 8) 778#define S3C2410_GPG4_INP (0x00 << 8)
594#define S3C2410_GPG4_OUTP (0x01 << 8) 779#define S3C2410_GPG4_OUTP (0x01 << 8)
595#define S3C2410_GPG4_EINT12 (0x02 << 8) 780#define S3C2410_GPG4_EINT12 (0x02 << 8)
781#define S3C2400_GPG4_MMCCLK (0x02 << 8)
782#define S3C2400_GPG4_I2SSDI (0x03 << 8)
596#define S3C2410_GPG4_LCDPWREN (0x03 << 8) 783#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
597 784
598#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) 785#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
599#define S3C2410_GPG5_INP (0x00 << 10) 786#define S3C2410_GPG5_INP (0x00 << 10)
600#define S3C2410_GPG5_OUTP (0x01 << 10) 787#define S3C2410_GPG5_OUTP (0x01 << 10)
601#define S3C2410_GPG5_EINT13 (0x02 << 10) 788#define S3C2410_GPG5_EINT13 (0x02 << 10)
789#define S3C2400_GPG5_MMCCMD (0x02 << 10)
790#define S3C2400_GPG5_IICSDA (0x03 << 10)
602#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) 791#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
603 792
604#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) 793#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
605#define S3C2410_GPG6_INP (0x00 << 12) 794#define S3C2410_GPG6_INP (0x00 << 12)
606#define S3C2410_GPG6_OUTP (0x01 << 12) 795#define S3C2410_GPG6_OUTP (0x01 << 12)
607#define S3C2410_GPG6_EINT14 (0x02 << 12) 796#define S3C2410_GPG6_EINT14 (0x02 << 12)
797#define S3C2400_GPG6_MMCDAT (0x02 << 12)
798#define S3C2400_GPG6_IICSCL (0x03 << 12)
608#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) 799#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
609 800
610#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) 801#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
@@ -612,16 +803,22 @@
612#define S3C2410_GPG7_OUTP (0x01 << 14) 803#define S3C2410_GPG7_OUTP (0x01 << 14)
613#define S3C2410_GPG7_EINT15 (0x02 << 14) 804#define S3C2410_GPG7_EINT15 (0x02 << 14)
614#define S3C2410_GPG7_SPICLK1 (0x03 << 14) 805#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
806#define S3C2400_GPG7_SPIMISO (0x02 << 14)
807#define S3C2400_GPG7_IICSDA (0x03 << 14)
615 808
616#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) 809#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
617#define S3C2410_GPG8_INP (0x00 << 16) 810#define S3C2410_GPG8_INP (0x00 << 16)
618#define S3C2410_GPG8_OUTP (0x01 << 16) 811#define S3C2410_GPG8_OUTP (0x01 << 16)
619#define S3C2410_GPG8_EINT16 (0x02 << 16) 812#define S3C2410_GPG8_EINT16 (0x02 << 16)
813#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
814#define S3C2400_GPG8_IICSCL (0x03 << 16)
620 815
621#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) 816#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
622#define S3C2410_GPG9_INP (0x00 << 18) 817#define S3C2410_GPG9_INP (0x00 << 18)
623#define S3C2410_GPG9_OUTP (0x01 << 18) 818#define S3C2410_GPG9_OUTP (0x01 << 18)
624#define S3C2410_GPG9_EINT17 (0x02 << 18) 819#define S3C2410_GPG9_EINT17 (0x02 << 18)
820#define S3C2400_GPG9_SPICLK (0x02 << 18)
821#define S3C2400_GPG9_MMCCLK (0x03 << 18)
625 822
626#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) 823#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
627#define S3C2410_GPG10_INP (0x00 << 20) 824#define S3C2410_GPG10_INP (0x00 << 20)
@@ -731,19 +928,27 @@
731#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 928#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
732 929
733/* miscellaneous control */ 930/* miscellaneous control */
734 931#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
735#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 932#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
736#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) 933#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
737 934
738/* see clock.h for dclk definitions */ 935/* see clock.h for dclk definitions */
739 936
740/* pullup control on databus */ 937/* pullup control on databus */
741#define S3C2410_MISCCR_SPUCR_HEN (0) 938#define S3C2410_MISCCR_SPUCR_HEN (0<<0)
742#define S3C2410_MISCCR_SPUCR_HDIS (1<<0) 939#define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
743#define S3C2410_MISCCR_SPUCR_LEN (0) 940#define S3C2410_MISCCR_SPUCR_LEN (0<<1)
744#define S3C2410_MISCCR_SPUCR_LDIS (1<<1) 941#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
745 942
746#define S3C2410_MISCCR_USBDEV (0) 943#define S3C2400_MISCCR_SPUCR_LEN (0<<0)
944#define S3C2400_MISCCR_SPUCR_LDIS (1<<0)
945#define S3C2400_MISCCR_SPUCR_HEN (0<<1)
946#define S3C2400_MISCCR_SPUCR_HDIS (1<<1)
947
948#define S3C2400_MISCCR_HZ_STOPEN (0<<2)
949#define S3C2400_MISCCR_HZ_STOPPREV (1<<2)
950
951#define S3C2410_MISCCR_USBDEV (0<<3)
747#define S3C2410_MISCCR_USBHOST (1<<3) 952#define S3C2410_MISCCR_USBHOST (1<<3)
748 953
749#define S3C2410_MISCCR_CLK0_MPLL (0<<4) 954#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
@@ -779,7 +984,7 @@
779 * 984 *
780 * Samsung datasheet p9-25 985 * Samsung datasheet p9-25
781*/ 986*/
782 987#define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58)
783#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) 988#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
784#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) 989#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
785#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) 990#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
@@ -827,5 +1032,21 @@
827#define S3C2410_GSTATUS2_OFFRESET (1<<1) 1032#define S3C2410_GSTATUS2_OFFRESET (1<<1)
828#define S3C2410_GSTATUS2_PONRESET (1<<0) 1033#define S3C2410_GSTATUS2_PONRESET (1<<0)
829 1034
1035/* open drain control register */
1036#define S3C2400_OPENCR S3C2410_GPIOREG(0x50)
1037
1038#define S3C2400_OPENCR_OPC_RXD1DIS (0<<0)
1039#define S3C2400_OPENCR_OPC_RXD1EN (1<<0)
1040#define S3C2400_OPENCR_OPC_TXD1DIS (0<<1)
1041#define S3C2400_OPENCR_OPC_TXD1EN (1<<1)
1042#define S3C2400_OPENCR_OPC_CMDDIS (0<<2)
1043#define S3C2400_OPENCR_OPC_CMDEN (1<<2)
1044#define S3C2400_OPENCR_OPC_DATDIS (0<<3)
1045#define S3C2400_OPENCR_OPC_DATEN (1<<3)
1046#define S3C2400_OPENCR_OPC_MISODIS (0<<4)
1047#define S3C2400_OPENCR_OPC_MISOEN (1<<4)
1048#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
1049#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
1050
830#endif /* __ASM_ARCH_REGS_GPIO_H */ 1051#endif /* __ASM_ARCH_REGS_GPIO_H */
831 1052
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index fdd62e8cd6cb..7fdde9b91cb4 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -55,6 +55,7 @@
55#define S3C2410_IISMOD_16FS (0<<0) 55#define S3C2410_IISMOD_16FS (0<<0)
56#define S3C2410_IISMOD_32FS (1<<0) 56#define S3C2410_IISMOD_32FS (1<<0)
57#define S3C2410_IISMOD_48FS (2<<0) 57#define S3C2410_IISMOD_48FS (2<<0)
58#define S3C2410_IISMOD_FS_MASK (3<<0)
58 59
59#define S3C2410_IISPSR (0x08) 60#define S3C2410_IISPSR (0x08)
60#define S3C2410_IISPSR_INTMASK (31<<5) 61#define S3C2410_IISPSR_INTMASK (31<<5)
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index d7a4a8354fa9..ddd1578a7ee0 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -116,6 +116,8 @@ putstr(const char *ptr)
116 } 116 }
117} 117}
118 118
119#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
120
119/* CONFIG_S3C2410_BOOT_WATCHDOG 121/* CONFIG_S3C2410_BOOT_WATCHDOG
120 * 122 *
121 * Simple boot-time watchdog setup, to reboot the system if there is 123 * Simple boot-time watchdog setup, to reboot the system if there is
@@ -126,8 +128,6 @@ putstr(const char *ptr)
126 128
127#define WDOG_COUNT (0xff00) 129#define WDOG_COUNT (0xff00)
128 130
129#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
130
131static inline void arch_decomp_wdog(void) 131static inline void arch_decomp_wdog(void)
132{ 132{
133 __raw_writel(WDOG_COUNT, S3C2410_WTCNT); 133 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
@@ -145,6 +145,24 @@ static void arch_decomp_wdog_start(void)
145#define arch_decomp_wdog() 145#define arch_decomp_wdog()
146#endif 146#endif
147 147
148#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
149
150static void arch_decomp_error(const char *x)
151{
152 putstr("\n\n");
153 putstr(x);
154 putstr("\n\n -- System resetting\n");
155
156 __raw_writel(0x4000, S3C2410_WTDAT);
157 __raw_writel(0x4000, S3C2410_WTCNT);
158 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
159
160 while(1);
161}
162
163#define arch_error arch_decomp_error
164#endif
165
148static void error(char *err); 166static void error(char *err);
149 167
150static void 168static void
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