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-rw-r--r--include/asm-arm/arch-s3c2410/bast-cpld.h58
-rw-r--r--include/asm-arm/arch-s3c2410/bast-irq.h33
-rw-r--r--include/asm-arm/arch-s3c2410/bast-map.h150
-rw-r--r--include/asm-arm/arch-s3c2410/bast-pmu.h43
-rw-r--r--include/asm-arm/arch-s3c2410/debug-macro.S99
-rw-r--r--include/asm-arm/arch-s3c2410/dma.h376
-rw-r--r--include/asm-arm/arch-s3c2410/entry-macro.S119
-rw-r--r--include/asm-arm/arch-s3c2410/hardware.h105
-rw-r--r--include/asm-arm/arch-s3c2410/idle.h28
-rw-r--r--include/asm-arm/arch-s3c2410/iic.h36
-rw-r--r--include/asm-arm/arch-s3c2410/io.h196
-rw-r--r--include/asm-arm/arch-s3c2410/irqs.h126
-rw-r--r--include/asm-arm/arch-s3c2410/map.h192
-rw-r--r--include/asm-arm/arch-s3c2410/memory.h44
-rw-r--r--include/asm-arm/arch-s3c2410/nand.h48
-rw-r--r--include/asm-arm/arch-s3c2410/otom-map.h30
-rw-r--r--include/asm-arm/arch-s3c2410/param.h27
-rw-r--r--include/asm-arm/arch-s3c2410/regs-adc.h63
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h122
-rw-r--r--include/asm-arm/arch-s3c2410/regs-dsc.h183
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h831
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpioj.h101
-rw-r--r--include/asm-arm/arch-s3c2410/regs-iic.h60
-rw-r--r--include/asm-arm/arch-s3c2410/regs-iis.h72
-rw-r--r--include/asm-arm/arch-s3c2410/regs-irq.h44
-rw-r--r--include/asm-arm/arch-s3c2410/regs-lcd.h114
-rw-r--r--include/asm-arm/arch-s3c2410/regs-mem.h212
-rw-r--r--include/asm-arm/arch-s3c2410/regs-nand.h43
-rw-r--r--include/asm-arm/arch-s3c2410/regs-rtc.h66
-rw-r--r--include/asm-arm/arch-s3c2410/regs-sdi.h118
-rw-r--r--include/asm-arm/arch-s3c2410/regs-serial.h209
-rw-r--r--include/asm-arm/arch-s3c2410/regs-spi.h56
-rw-r--r--include/asm-arm/arch-s3c2410/regs-timer.h113
-rw-r--r--include/asm-arm/arch-s3c2410/regs-udc.h164
-rw-r--r--include/asm-arm/arch-s3c2410/regs-watchdog.h46
-rw-r--r--include/asm-arm/arch-s3c2410/system.h90
-rw-r--r--include/asm-arm/arch-s3c2410/timex.h32
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h158
-rw-r--r--include/asm-arm/arch-s3c2410/usb-control.h45
-rw-r--r--include/asm-arm/arch-s3c2410/vmalloc.h36
-rw-r--r--include/asm-arm/arch-s3c2410/vr1000-cpld.h22
-rw-r--r--include/asm-arm/arch-s3c2410/vr1000-irq.h30
-rw-r--r--include/asm-arm/arch-s3c2410/vr1000-map.h116
43 files changed, 4856 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/bast-cpld.h b/include/asm-arm/arch-s3c2410/bast-cpld.h
new file mode 100644
index 000000000000..e28ca51a4975
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/bast-cpld.h
@@ -0,0 +1,58 @@
1/* linux/include/asm-arm/arch-s3c2410/bast-cpld.h
2 *
3 * (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * BAST - CPLD control constants
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 25-May-2003 BJD Created file, added CTRL1 registers
14 * 30-Aug-2004 BJD Updated definitions from 2.4.26 port
15 * 30-Aug-2004 BJD Added CTRL3 and CTRL4 definitions
16*/
17
18#ifndef __ASM_ARCH_BASTCPLD_H
19#define __ASM_ARCH_BASTCPLD_H
20
21/* CTRL1 - Audio LR routing */
22
23#define BAST_CPLD_CTRL1_LRCOFF (0x00)
24#define BAST_CPLD_CTRL1_LRCADC (0x01)
25#define BAST_CPLD_CTRL1_LRCDAC (0x02)
26#define BAST_CPLD_CTRL1_LRCARM (0x03)
27#define BAST_CPLD_CTRL1_LRMASK (0x03)
28
29/* CTRL2 - NAND WP control, IDE Reset assert/check */
30
31#define BAST_CPLD_CTRL2_WNAND (0x04)
32#define BAST_CPLD_CTLR2_IDERST (0x08)
33
34/* CTRL3 - rom write control, CPLD identity */
35
36#define BAST_CPLD_CTRL3_IDMASK (0x0e)
37#define BAST_CPLD_CTRL3_ROMWEN (0x01)
38
39/* CTRL4 - 8bit LCD interface control/status */
40
41#define BAST_CPLD_CTRL4_LLAT (0x01)
42#define BAST_CPLD_CTRL4_LCDRW (0x02)
43#define BAST_CPLD_CTRL4_LCDCMD (0x04)
44#define BAST_CPLD_CTRL4_LCDE2 (0x01)
45
46/* CTRL5 - DMA routing */
47
48#define BAST_CPLD_DMA0_PRIIDE (0<<0)
49#define BAST_CPLD_DMA0_SECIDE (1<<0)
50#define BAST_CPLD_DMA0_ISA15 (2<<0)
51#define BAST_CPLD_DMA0_ISA36 (3<<0)
52
53#define BAST_CPLD_DMA1_PRIIDE (0<<2)
54#define BAST_CPLD_DMA1_SECIDE (1<<2)
55#define BAST_CPLD_DMA1_ISA15 (2<<2)
56#define BAST_CPLD_DMA1_ISA36 (3<<2)
57
58#endif /* __ASM_ARCH_BASTCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-irq.h b/include/asm-arm/arch-s3c2410/bast-irq.h
new file mode 100644
index 000000000000..b79b47f0d126
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/bast-irq.h
@@ -0,0 +1,33 @@
1/* linux/include/asm-arm/arch-s3c2410/bast-irq.h
2 *
3 * (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine BAST - IRQ Number definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 14-Sep-2004 BJD Fixed IRQ_USBOC definition
14 * 06-Jan-2003 BJD Linux 2.6.0 version
15 */
16
17#ifndef __ASM_ARCH_BASTIRQ_H
18#define __ASM_ARCH_BASTIRQ_H
19
20/* irq numbers to onboard peripherals */
21
22#define IRQ_USBOC IRQ_EINT18
23#define IRQ_IDE0 IRQ_EINT16
24#define IRQ_IDE1 IRQ_EINT17
25#define IRQ_PCSERIAL1 IRQ_EINT15
26#define IRQ_PCSERIAL2 IRQ_EINT14
27#define IRQ_PCPARALLEL IRQ_EINT13
28#define IRQ_ASIX IRQ_EINT11
29#define IRQ_DM9000 IRQ_EINT10
30#define IRQ_ISA IRQ_EINT9
31#define IRQ_SMALERT IRQ_EINT8
32
33#endif /* __ASM_ARCH_BASTIRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-map.h b/include/asm-arm/arch-s3c2410/bast-map.h
new file mode 100644
index 000000000000..29c07e302b04
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/bast-map.h
@@ -0,0 +1,150 @@
1/* linux/include/asm-arm/arch-s3c2410/bast-map.h
2 *
3 * (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine BAST - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 06-Jan-2003 BJD Linux 2.6.0 version, moved bast specifics from arch/map.h
14 * 12-Mar-2004 BJD Fixed header include protection
15*/
16
17/* needs arch/map.h including with this */
18
19/* ok, we've used up to 0x13000000, now we need to find space for the
20 * peripherals that live in the nGCS[x] areas, which are quite numerous
21 * in their space. We also have the board's CPLD to find register space
22 * for.
23 */
24
25#ifndef __ASM_ARCH_BASTMAP_H
26#define __ASM_ARCH_BASTMAP_H
27
28#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
29
30/* we put the CPLD registers next, to get them out of the way */
31
32#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */
33#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
34
35#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */
36#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
37
38#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */
39#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
40
41#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */
42#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
43
44/* next, we have the PC104 ISA interrupt registers */
45
46#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
47#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
48
49#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
50#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
51
52#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
53#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
54
55#define BAST_PA_LCD_RCMD1 (0x8800000)
56#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
57
58#define BAST_PA_LCD_WCMD1 (0x8000000)
59#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
60
61#define BAST_PA_LCD_RDATA1 (0x9800000)
62#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
63
64#define BAST_PA_LCD_WDATA1 (0x9000000)
65#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
66
67#define BAST_PA_LCD_RCMD2 (0xA800000)
68#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
69
70#define BAST_PA_LCD_WCMD2 (0xA000000)
71#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
72
73#define BAST_PA_LCD_RDATA2 (0xB800000)
74#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
75
76#define BAST_PA_LCD_WDATA2 (0xB000000)
77#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
78
79
80/* 0xE0000000 contains the IO space that is split by speed and
81 * wether the access is for 8 or 16bit IO... this ensures that
82 * the correct access is made
83 *
84 * 0x10000000 of space, partitioned as so:
85 *
86 * 0x00000000 to 0x04000000 8bit, slow
87 * 0x04000000 to 0x08000000 16bit, slow
88 * 0x08000000 to 0x0C000000 16bit, net
89 * 0x0C000000 to 0x10000000 16bit, fast
90 *
91 * each of these spaces has the following in:
92 *
93 * 0x00000000 to 0x01000000 16MB ISA IO space
94 * 0x01000000 to 0x02000000 16MB ISA memory space
95 * 0x02000000 to 0x02100000 1MB IDE primary channel
96 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
97 * 0x02200000 to 0x02400000 1MB IDE secondary channel
98 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
99 * 0x02400000 to 0x02500000 1MB ASIX ethernet controller
100 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
101 * 0x02600000 to 0x02700000 1MB PC SuperIO controller
102 *
103 * the phyiscal layout of the zones are:
104 * nGCS2 - 8bit, slow
105 * nGCS3 - 16bit, slow
106 * nGCS4 - 16bit, net
107 * nGCS5 - 16bit, fast
108 */
109
110#define BAST_VA_MULTISPACE (0xE0000000)
111
112#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
113#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
114#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
115#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
116#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
117#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
118#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
119#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
120#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
121
122#define BAST_VA_MULTISPACE (0xE0000000)
123
124#define BAST_VAM_CS2 (0x00000000)
125#define BAST_VAM_CS3 (0x04000000)
126#define BAST_VAM_CS4 (0x08000000)
127#define BAST_VAM_CS5 (0x0C000000)
128
129/* physical offset addresses for the peripherals */
130
131#define BAST_PA_ISAIO (0x00000000)
132#define BAST_PA_ASIXNET (0x01000000)
133#define BAST_PA_SUPERIO (0x01800000)
134#define BAST_PA_IDEPRI (0x02000000)
135#define BAST_PA_IDEPRIAUX (0x02800000)
136#define BAST_PA_IDESEC (0x03000000)
137#define BAST_PA_IDESECAUX (0x03800000)
138#define BAST_PA_ISAMEM (0x04000000)
139#define BAST_PA_DM9000 (0x05000000)
140
141/* some configurations for the peripherals */
142
143#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
144/* */
145
146#define BAST_ASIXNET_CS BAST_VAM_CS5
147#define BAST_IDE_CS BAST_VAM_CS5
148#define BAST_DM9000_CS BAST_VAM_CS4
149
150#endif /* __ASM_ARCH_BASTMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-pmu.h b/include/asm-arm/arch-s3c2410/bast-pmu.h
new file mode 100644
index 000000000000..758c5c59d4bf
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/bast-pmu.h
@@ -0,0 +1,43 @@
1/* linux/include/asm-arm/arch-s3c2410/bast-pmu.h
2 *
3 * (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * Machine BAST - Power Management chip
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Changelog:
14 * 08-Oct-2003 BJD Initial creation
15*/
16
17#ifndef __ASM_ARCH_BASTPMU_H
18#define __ASM_ARCH_BASTPMU_H "08_OCT_2004"
19
20#define BASTPMU_REG_IDENT (0x00)
21#define BASTPMU_REG_VERSION (0x01)
22#define BASTPMU_REG_DDCCTRL (0x02)
23#define BASTPMU_REG_POWER (0x03)
24#define BASTPMU_REG_RESET (0x04)
25#define BASTPMU_REG_GWO (0x05)
26#define BASTPMU_REG_WOL (0x06)
27#define BASTPMU_REG_WOR (0x07)
28#define BASTPMU_REG_UID (0x09)
29
30#define BASTPMU_EEPROM (0xC0)
31
32#define BASTPMU_EEP_UID (BASTPMU_EEPROM + 0)
33#define BASTPMU_EEP_WOL (BASTPMU_EEPROM + 8)
34#define BASTPMU_EEP_WOR (BASTPMU_EEPROM + 9)
35
36#define BASTPMU_IDENT_0 0x53
37#define BASTPMU_IDENT_1 0x42
38#define BASTPMU_IDENT_2 0x50
39#define BASTPMU_IDENT_3 0x4d
40
41#define BASTPMU_RESET_GUARD (0x55)
42
43#endif /* __ASM_ARCH_BASTPMU_H */
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
new file mode 100644
index 000000000000..abfbe45cd17c
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -0,0 +1,99 @@
1/* linux/include/asm-arm/arch-s3c2410/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Copyright (C) 2005 Simtec Electronics
7 *
8 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Modifications:
15 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
16*/
17
18#include <asm/arch/map.h>
19#include <asm/arch/regs-serial.h>
20#include <asm/arch/regs-gpio.h>
21
22#define S3C2410_UART1_OFF (0x4000)
23#define SHIFT_2440TXF (14-9)
24
25 .macro addruart, rx
26 mrc p15, 0, \rx, c1, c0
27 tst \rx, #1
28 ldreq \rx, = S3C2410_PA_UART
29 ldrne \rx, = S3C24XX_VA_UART
30#if CONFIG_DEBUG_S3C2410_UART != 0
31 add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART)
32#endif
33 .endm
34
35 .macro senduart,rd,rx
36 str \rd, [\rx, # S3C2410_UTXH ]
37 .endm
38
39 .macro busyuart, rd, rx
40 ldr \rd, [ \rx, # S3C2410_UFCON ]
41 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
42 beq 1001f @
43 @ FIFO enabled...
441003:
45 mrc p15, 0, \rd, c1, c0
46 tst \rd, #1
47 addeq \rd, \rx, #(S3C2410_PA_GPIO - S3C2410_PA_UART)
48 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
49 bic \rd, \rd, #0xff000
50 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
51 and \rd, \rd, #0x00ff0000
52 teq \rd, #0x00440000 @ is it 2440?
53
54 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
55 moveq \rd, \rd, lsr #SHIFT_2440TXF
56 tst \rd, #S3C2410_UFSTAT_TXFULL
57 bne 1003b
58 b 1002f
59
601001:
61 @ busy waiting for non fifo
62 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
63 tst \rd, #S3C2410_UTRSTAT_TXFE
64 beq 1001b
65
661002: @ exit busyuart
67 .endm
68
69 .macro waituart,rd,rx
70
71 ldr \rd, [ \rx, # S3C2410_UFCON ]
72 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
73 beq 1001f @
74 @ FIFO enabled...
751003:
76 mrc p15, 0, \rd, c1, c0
77 tst \rd, #1
78 addeq \rd, \rx, #(S3C2410_PA_GPIO - S3C2410_PA_UART)
79 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
80 bic \rd, \rd, #0xff000
81 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
82 and \rd, \rd, #0x00ff0000
83 teq \rd, #0x00440000 @ is it 2440?
84
85 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
86 andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
87 andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
88 teq \rd, #0
89 bne 1003b
90 b 1002f
91
921001:
93 @ idle waiting for non fifo
94 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
95 tst \rd, #S3C2410_UTRSTAT_TXFE
96 beq 1001b
97
981002: @ exit busyuart
99 .endm
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
new file mode 100644
index 000000000000..e830a40e573a
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -0,0 +1,376 @@
1/* linux/include/asm-arm/arch-bast/dma.h
2 *
3 * Copyright (C) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2410X DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * ??-May-2003 BJD Created file
14 * ??-Jun-2003 BJD Added more dma functionality to go with arch
15 * 10-Nov-2004 BJD Added sys_device support
16*/
17
18#ifndef __ASM_ARCH_DMA_H
19#define __ASM_ARCH_DMA_H __FILE__
20
21#include <linux/config.h>
22#include <linux/sysdev.h>
23#include "hardware.h"
24
25
26/*
27 * This is the maximum DMA address(physical address) that can be DMAd to.
28 *
29 */
30#define MAX_DMA_ADDRESS 0x20000000
31#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
32
33
34/* according to the samsung port, we cannot use the regular
35 * dma channels... we must therefore provide our own interface
36 * for DMA, and allow our drivers to use that.
37 */
38
39#define MAX_DMA_CHANNELS 0
40
41
42/* we have 4 dma channels */
43#define S3C2410_DMA_CHANNELS (4)
44
45/* types */
46
47typedef enum {
48 S3C2410_DMA_IDLE,
49 S3C2410_DMA_RUNNING,
50 S3C2410_DMA_PAUSED
51} s3c2410_dma_state_t;
52
53
54/* s3c2410_dma_loadst_t
55 *
56 * This represents the state of the DMA engine, wrt to the loaded / running
57 * transfers. Since we don't have any way of knowing exactly the state of
58 * the DMA transfers, we need to know the state to make decisions on wether
59 * we can
60 *
61 * S3C2410_DMA_NONE
62 *
63 * There are no buffers loaded (the channel should be inactive)
64 *
65 * S3C2410_DMA_1LOADED
66 *
67 * There is one buffer loaded, however it has not been confirmed to be
68 * loaded by the DMA engine. This may be because the channel is not
69 * yet running, or the DMA driver decided that it was too costly to
70 * sit and wait for it to happen.
71 *
72 * S3C2410_DMA_1RUNNING
73 *
74 * The buffer has been confirmed running, and not finisged
75 *
76 * S3C2410_DMA_1LOADED_1RUNNING
77 *
78 * There is a buffer waiting to be loaded by the DMA engine, and one
79 * currently running.
80*/
81
82typedef enum {
83 S3C2410_DMALOAD_NONE,
84 S3C2410_DMALOAD_1LOADED,
85 S3C2410_DMALOAD_1RUNNING,
86 S3C2410_DMALOAD_1LOADED_1RUNNING,
87} s3c2410_dma_loadst_t;
88
89typedef enum {
90 S3C2410_RES_OK,
91 S3C2410_RES_ERR,
92 S3C2410_RES_ABORT
93} s3c2410_dma_buffresult_t;
94
95
96typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
97
98enum s3c2410_dmasrc_e {
99 S3C2410_DMASRC_HW, /* source is memory */
100 S3C2410_DMASRC_MEM /* source is hardware */
101};
102
103/* enum s3c2410_chan_op_e
104 *
105 * operation codes passed to the DMA code by the user, and also used
106 * to inform the current channel owner of any changes to the system state
107*/
108
109enum s3c2410_chan_op_e {
110 S3C2410_DMAOP_START,
111 S3C2410_DMAOP_STOP,
112 S3C2410_DMAOP_PAUSE,
113 S3C2410_DMAOP_RESUME,
114 S3C2410_DMAOP_FLUSH,
115 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
116};
117
118typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
119
120/* flags */
121
122#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
123 * waiting for reloads */
124#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
125
126/* dma buffer */
127
128typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
129
130struct s3c2410_dma_client {
131 char *name;
132};
133
134typedef struct s3c2410_dma_client s3c2410_dma_client_t;
135
136/* s3c2410_dma_buf_s
137 *
138 * internally used buffer structure to describe a queued or running
139 * buffer.
140*/
141
142struct s3c2410_dma_buf_s {
143 s3c2410_dma_buf_t *next;
144 int magic; /* magic */
145 int size; /* buffer size in bytes */
146 dma_addr_t data; /* start of DMA data */
147 dma_addr_t ptr; /* where the DMA got to [1] */
148 void *id; /* client's id */
149};
150
151/* [1] is this updated for both recv/send modes? */
152
153typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t;
154
155/* s3c2410_dma_cbfn_t
156 *
157 * buffer callback routine type
158*/
159
160typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size,
161 s3c2410_dma_buffresult_t result);
162
163typedef int (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *,
164 s3c2410_chan_op_t );
165
166struct s3c2410_dma_stats_s {
167 unsigned long loads;
168 unsigned long timeout_longest;
169 unsigned long timeout_shortest;
170 unsigned long timeout_avg;
171 unsigned long timeout_failed;
172};
173
174typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t;
175
176/* struct s3c2410_dma_chan_s
177 *
178 * full state information for each DMA channel
179*/
180
181struct s3c2410_dma_chan_s {
182 /* channel state flags and information */
183 unsigned char number; /* number of this dma channel */
184 unsigned char in_use; /* channel allocated */
185 unsigned char irq_claimed; /* irq claimed for channel */
186 unsigned char irq_enabled; /* irq enabled for channel */
187 unsigned char xfer_unit; /* size of an transfer */
188
189 /* channel state */
190
191 s3c2410_dma_state_t state;
192 s3c2410_dma_loadst_t load_state;
193 s3c2410_dma_client_t *client;
194
195 /* channel configuration */
196 s3c2410_dmasrc_t source;
197 unsigned long dev_addr;
198 unsigned long load_timeout;
199 unsigned int flags; /* channel flags */
200
201 /* channel's hardware position and configuration */
202 void __iomem *regs; /* channels registers */
203 void __iomem *addr_reg; /* data address register */
204 unsigned int irq; /* channel irq */
205 unsigned long dcon; /* default value of DCON */
206
207 /* driver handles */
208 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
209 s3c2410_dma_opfn_t op_fn; /* channel operation callback */
210
211 /* stats gathering */
212 s3c2410_dma_stats_t *stats;
213 s3c2410_dma_stats_t stats_store;
214
215 /* buffer list and information */
216 s3c2410_dma_buf_t *curr; /* current dma buffer */
217 s3c2410_dma_buf_t *next; /* next buffer to load */
218 s3c2410_dma_buf_t *end; /* end of queue */
219
220 /* system device */
221 struct sys_device dev;
222};
223
224/* the currently allocated channel information */
225extern s3c2410_dma_chan_t s3c2410_chans[];
226
227/* note, we don't really use dma_device_t at the moment */
228typedef unsigned long dma_device_t;
229
230/* functions --------------------------------------------------------------- */
231
232/* s3c2410_dma_request
233 *
234 * request a dma channel exclusivley
235*/
236
237extern int s3c2410_dma_request(dmach_t channel,
238 s3c2410_dma_client_t *, void *dev);
239
240
241/* s3c2410_dma_ctrl
242 *
243 * change the state of the dma channel
244*/
245
246extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op);
247
248/* s3c2410_dma_setflags
249 *
250 * set the channel's flags to a given state
251*/
252
253extern int s3c2410_dma_setflags(dmach_t channel,
254 unsigned int flags);
255
256/* s3c2410_dma_free
257 *
258 * free the dma channel (will also abort any outstanding operations)
259*/
260
261extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *);
262
263/* s3c2410_dma_enqueue
264 *
265 * place the given buffer onto the queue of operations for the channel.
266 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
267 * drained before the buffer is given to the DMA system.
268*/
269
270extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
271 dma_addr_t data, int size);
272
273/* s3c2410_dma_config
274 *
275 * configure the dma channel
276*/
277
278extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
279
280/* s3c2410_dma_devconfig
281 *
282 * configure the device we're talking to
283*/
284
285extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source,
286 int hwcfg, unsigned long devaddr);
287
288/* s3c2410_dma_getposition
289 *
290 * get the position that the dma transfer is currently at
291*/
292
293extern int s3c2410_dma_getposition(dmach_t channel,
294 dma_addr_t *src, dma_addr_t *dest);
295
296extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
297extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
298
299/* DMA Register definitions */
300
301#define S3C2410_DMA_DISRC (0x00)
302#define S3C2410_DMA_DISRCC (0x04)
303#define S3C2410_DMA_DIDST (0x08)
304#define S3C2410_DMA_DIDSTC (0x0C)
305#define S3C2410_DMA_DCON (0x10)
306#define S3C2410_DMA_DSTAT (0x14)
307#define S3C2410_DMA_DCSRC (0x18)
308#define S3C2410_DMA_DCDST (0x1C)
309#define S3C2410_DMA_DMASKTRIG (0x20)
310
311#define S3C2410_DISRCC_INC (1<<0)
312#define S3C2410_DISRCC_APB (1<<1)
313
314#define S3C2410_DMASKTRIG_STOP (1<<2)
315#define S3C2410_DMASKTRIG_ON (1<<1)
316#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
317
318#define S3C2410_DCON_DEMAND (0<<31)
319#define S3C2410_DCON_HANDSHAKE (1<<31)
320#define S3C2410_DCON_SYNC_PCLK (0<<30)
321#define S3C2410_DCON_SYNC_HCLK (1<<30)
322
323#define S3C2410_DCON_INTREQ (1<<29)
324
325#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
326#define S3C2410_DCON_CH0_UART0 (1<<24)
327#define S3C2410_DCON_CH0_SDI (2<<24)
328#define S3C2410_DCON_CH0_TIMER (3<<24)
329#define S3C2410_DCON_CH0_USBEP1 (4<<24)
330
331#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
332#define S3C2410_DCON_CH1_UART1 (1<<24)
333#define S3C2410_DCON_CH1_I2SSDI (2<<24)
334#define S3C2410_DCON_CH1_SPI (3<<24)
335#define S3C2410_DCON_CH1_USBEP2 (4<<24)
336
337#define S3C2410_DCON_CH2_I2SSDO (0<<24)
338#define S3C2410_DCON_CH2_I2SSDI (1<<24)
339#define S3C2410_DCON_CH2_SDI (2<<24)
340#define S3C2410_DCON_CH2_TIMER (3<<24)
341#define S3C2410_DCON_CH2_USBEP3 (4<<24)
342
343#define S3C2410_DCON_CH3_UART2 (0<<24)
344#define S3C2410_DCON_CH3_SDI (1<<24)
345#define S3C2410_DCON_CH3_SPI (2<<24)
346#define S3C2410_DCON_CH3_TIMER (3<<24)
347#define S3C2410_DCON_CH3_USBEP4 (4<<24)
348
349#define S3C2410_DCON_SRCSHIFT (24)
350#define S3C2410_DCON_SRCMASK (7<<24)
351
352#define S3C2410_DCON_BYTE (0<<20)
353#define S3C2410_DCON_HALFWORD (1<<20)
354#define S3C2410_DCON_WORD (2<<20)
355
356#define S3C2410_DCON_AUTORELOAD (0<<22)
357#define S3C2410_DCON_NORELOAD (1<<22)
358#define S3C2410_DCON_HWTRIG (1<<23)
359
360#ifdef CONFIG_CPU_S3C2440
361#define S3C2440_DIDSTC_CHKINT (1<<2)
362
363#define S3C2440_DCON_CH0_I2SSDO (5<<24)
364#define S3C2440_DCON_CH0_PCMIN (6<<24)
365
366#define S3C2440_DCON_CH1_PCMOUT (5<<24)
367#define S3C2440_DCON_CH1_SDI (6<<24)
368
369#define S3C2440_DCON_CH2_PCMIN (5<<24)
370#define S3C2440_DCON_CH2_MICIN (6<<24)
371
372#define S3C2440_DCON_CH3_MICIN (5<<24)
373#define S3C2440_DCON_CH3_PCMOUT (6<<24)
374#endif
375
376#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S
new file mode 100644
index 000000000000..b7d4d7f4422d
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/entry-macro.S
@@ -0,0 +1,119 @@
1/*
2 * include/asm-arm/arch-s3c2410/entry-macro.S
3 *
4 * Low-level IRQ helper macros for S3C2410-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9
10 * Modifications:
11 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
12 */
13
14
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16
17 mov \tmp, #S3C24XX_VA_IRQ
18 ldr \irqnr, [ \tmp, #0x14 ] @ get irq no
1930000:
20 teq \irqnr, #4
21 teqne \irqnr, #5
22 beq 1002f @ external irq reg
23
24 @ debug check to see if interrupt reported is the same
25 @ as the offset....
26
27 teq \irqnr, #0
28 beq 20002f
29 ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
30 mov \irqstat, \irqstat, lsr \irqnr
31 tst \irqstat, #1
32 bne 20002f
33
34 /* debug/warning if we get an invalud response from the
35 * INTOFFSET register */
36#if 1
37 stmfd r13!, { r0 - r4 , r8-r12, r14 }
38 ldr r1, [ \tmp, #0x14 ] @ INTOFFSET
39 ldr r2, [ \tmp, #0x10 ] @ INTPND
40 ldr r3, [ \tmp, #0x00 ] @ SRCPND
41 adr r0, 20003f
42 bl printk
43 b 20004f
44
4520003:
46 .ascii "<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n"
47 .byte 0
48 .align 4
4920004:
50 mov r1, #1
51 mov \tmp, #S3C24XX_VA_IRQ
52 ldmfd r13!, { r0 - r4 , r8-r12, r14 }
53#endif
54
55 @ try working out interrupt number for ourselves
56 mov \irqnr, #0
57 ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
5810021:
59 movs \irqstat, \irqstat, lsr#1
60 bcs 30000b @ try and re-start the proccess
61 add \irqnr, \irqnr, #1
62 cmp \irqnr, #32
63 ble 10021b
64
65 @ found no interrupt, set Z flag and leave
66 movs \irqnr, #0
67 b 1001f
68
6920005:
7020002: @ exit
71 @ we base the s3c2410x interrupts at 16 and above to allow
72 @ isa peripherals to have their standard interrupts, also
73 @ ensure that Z flag is un-set on exit
74
75 @ note, we cannot be sure if we get IRQ_EINT0 (0) that
76 @ there is simply no interrupt pending, so in all other
77 @ cases we jump to say we have found something, otherwise
78 @ we check to see if the interrupt really is assrted
79 adds \irqnr, \irqnr, #IRQ_EINT0
80 teq \irqnr, #IRQ_EINT0
81 bne 1001f @ exit
82 ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
83 teq \irqstat, #0
84 moveq \irqnr, #0
85 b 1001f
86
87 @ we get here from no main or external interrupts pending
881002:
89 add \tmp, \tmp, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
90 ldr \irqstat, [ \tmp, # 0xa8 ] @ EXTINTPEND
91 ldr \irqnr, [ \tmp, # 0xa4 ] @ EXTINTMASK
92
93 bic \irqstat, \irqstat, \irqnr @ clear masked irqs
94
95 mov \irqnr, #IRQ_EINT4 @ start extint nos
96 mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits
9710021:
98 movs \irqstat, \irqstat, lsr#1
99 bcs 1004f
100 add \irqnr, \irqnr, #1
101 cmp \irqnr, #IRQ_EINT23
102 ble 10021b
103
104 @ found no interrupt, set Z flag and leave
105 movs \irqnr, #0
106
1071004: @ ensure Z flag clear in case our MOVS shifted out the last bit
108 teq \irqnr, #0
1091001:
110 @ exit irq routine
111 .endm
112
113
114 /* currently don't need an disable_fiq macro */
115
116 .macro disable_fiq
117 .endm
118
119
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
new file mode 100644
index 000000000000..48a39918a760
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -0,0 +1,105 @@
1/* linux/include/asm-arm/arch-s3c2410/hardware.h
2 *
3 * (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - hardware
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 21-May-2003 BJD Created file
14 * 06-Jun-2003 BJD Added CPU frequency settings
15 * 03-Sep-2003 BJD Linux v2.6 support
16 * 12-Mar-2004 BJD Fixed include protection, fixed type of clock vars
17 * 14-Sep-2004 BJD Added misccr and getpin to gpio
18 * 01-Oct-2004 BJD Added the new gpio functions
19 * 16-Oct-2004 BJD Removed the clock variables
20*/
21
22#ifndef __ASM_ARCH_HARDWARE_H
23#define __ASM_ARCH_HARDWARE_H
24
25#ifndef __ASSEMBLY__
26
27/* external functions for GPIO support
28 *
29 * These allow various different clients to access the same GPIO
30 * registers without conflicting. If your driver only owns the entire
31 * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
32*/
33
34/* s3c2410_gpio_cfgpin
35 *
36 * set the configuration of the given pin to the value passed.
37 *
38 * eg:
39 * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
40 * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
41*/
42
43extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
44
45extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
46
47/* s3c2410_gpio_getirq
48 *
49 * turn the given pin number into the corresponding IRQ number
50 *
51 * returns:
52 * < 0 = no interrupt for this pin
53 * >=0 = interrupt number for the pin
54*/
55
56extern int s3c2410_gpio_getirq(unsigned int pin);
57
58/* s3c2410_gpio_irqfilter
59 *
60 * set the irq filtering on the given pin
61 *
62 * on = 0 => disable filtering
63 * 1 => enable filtering
64 *
65 * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
66 * width of filter (0 through 63)
67 *
68 *
69*/
70
71extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
72 unsigned int config);
73
74/* s3c2410_gpio_pullup
75 *
76 * configure the pull-up control on the given pin
77 *
78 * to = 1 => disable the pull-up
79 * 0 => enable the pull-up
80 *
81 * eg;
82 *
83 * s3c2410_gpio_pullup(S3C2410_GPB0, 0);
84 * s3c2410_gpio_pullup(S3C2410_GPE8, 0);
85*/
86
87extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
88
89extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
90
91extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
92
93extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
94
95#endif /* __ASSEMBLY__ */
96
97#include <asm/sizes.h>
98#include <asm/arch/map.h>
99
100/* machine specific hardware definitions should go after this */
101
102/* currently here until moved into config (todo) */
103#define CONFIG_NO_MULTIWORD_IO
104
105#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-s3c2410/idle.h b/include/asm-arm/arch-s3c2410/idle.h
new file mode 100644
index 000000000000..749227c09576
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/idle.h
@@ -0,0 +1,28 @@
1/* linux/include/asm-arm/arch-s3c2410/idle.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 CPU Idle controls
11 *
12 * Changelog:
13 * 28-Oct-2004 BJD Initial version
14 *
15*/
16
17#ifndef __ASM_ARCH_IDLE_H
18#define __ASM_ARCH_IDLE_H __FILE__
19
20/* This allows the over-ride of the default idle code, in case there
21 * is any other things to be done over idle (like DVS)
22*/
23
24extern void (*s3c24xx_idle)(void);
25
26extern void s3c24xx_default_idle(void);
27
28#endif /* __ASM_ARCH_IDLE_H */
diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/arch-s3c2410/iic.h
new file mode 100644
index 000000000000..518547f6d7a7
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/iic.h
@@ -0,0 +1,36 @@
1/* linux/include/asm-arm/arch-s3c2410/iic.h
2 *
3 * (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - I2C Controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 05-Oct-2004 BJD Created file
14 * 19-Oct-2004 BJD Updated for s3c2440
15*/
16
17#ifndef __ASM_ARCH_IIC_H
18#define __ASM_ARCH_IIC_H __FILE__
19
20#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
21
22/* Notes:
23 * 1) All frequencies are expressed in Hz
24 * 2) A value of zero is `do not care`
25*/
26
27struct s3c2410_platform_i2c {
28 unsigned int flags;
29 unsigned int slave_addr; /* slave address for controller */
30 unsigned long bus_freq; /* standard bus frequency */
31 unsigned long max_freq; /* max frequency for the bus */
32 unsigned long min_freq; /* min frequency for the bus */
33 unsigned int sda_delay; /* pclks (s3c2440 only) */
34};
35
36#endif /* __ASM_ARCH_IIC_H */
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h
new file mode 100644
index 000000000000..418233a7ee6f
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/io.h
@@ -0,0 +1,196 @@
1/*
2 * linux/include/asm-arm/arch-s3c2410/io.h
3 * from linux/include/asm-arm/arch-rpc/io.h
4 *
5 * Copyright (C) 1997 Russell King
6 * (C) 2003 Simtec Electronics
7 *
8 * Modifications:
9 * 06-Dec-1997 RMK Created.
10 * 02-Sep-2003 BJD Modified for S3C2410
11 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
12 *
13 */
14
15#ifndef __ASM_ARM_ARCH_IO_H
16#define __ASM_ARM_ARCH_IO_H
17
18#define IO_SPACE_LIMIT 0xffffffff
19
20/*
21 * We use two different types of addressing - PC style addresses, and ARM
22 * addresses. PC style accesses the PC hardware with the normal PC IO
23 * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28
24 * and are translated to the start of IO. Note that all addresses are
25 * not shifted left!
26 */
27
28#define __PORT_PCIO(x) ((x) < (1<<28))
29
30#define PCIO_BASE (S3C24XX_VA_ISA_WORD)
31#define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE)
32#define PCIO_BASE_w (S3C24XX_VA_ISA_WORD)
33#define PCIO_BASE_l (S3C24XX_VA_ISA_WORD)
34/*
35 * Dynamic IO functions - let the compiler
36 * optimize the expressions
37 */
38
39#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
40static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
41{ \
42 unsigned long temp; \
43 __asm__ __volatile__( \
44 "cmp %2, #(1<<28)\n\t" \
45 "mov %0, %2\n\t" \
46 "addcc %0, %0, %3\n\t" \
47 "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \
48 : "=&r" (temp) \
49 : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
50 : "cc"); \
51}
52
53
54#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
55static inline unsigned sz __in##fnsuffix (unsigned int port) \
56{ \
57 unsigned long temp, value; \
58 __asm__ __volatile__( \
59 "cmp %2, #(1<<28)\n\t" \
60 "mov %0, %2\n\t" \
61 "addcc %0, %0, %3\n\t" \
62 "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \
63 : "=&r" (temp), "=r" (value) \
64 : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
65 : "cc"); \
66 return (unsigned sz)value; \
67}
68
69static inline void __iomem *__ioaddr (unsigned long port)
70{
71 return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
72}
73
74#define DECLARE_IO(sz,fnsuffix,instr) \
75 DECLARE_DYN_IN(sz,fnsuffix,instr) \
76 DECLARE_DYN_OUT(sz,fnsuffix,instr)
77
78DECLARE_IO(char,b,"b")
79DECLARE_IO(short,w,"h")
80DECLARE_IO(int,l,"")
81
82#undef DECLARE_IO
83#undef DECLARE_DYN_IN
84
85/*
86 * Constant address IO functions
87 *
88 * These have to be macros for the 'J' constraint to work -
89 * +/-4096 immediate operand.
90 */
91#define __outbc(value,port) \
92({ \
93 if (__PORT_PCIO((port))) \
94 __asm__ __volatile__( \
95 "strb %0, [%1, %2] @ outbc" \
96 : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \
97 else \
98 __asm__ __volatile__( \
99 "strb %0, [%1, #0] @ outbc" \
100 : : "r" (value), "r" ((port))); \
101})
102
103#define __inbc(port) \
104({ \
105 unsigned char result; \
106 if (__PORT_PCIO((port))) \
107 __asm__ __volatile__( \
108 "ldrb %0, [%1, %2] @ inbc" \
109 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
110 else \
111 __asm__ __volatile__( \
112 "ldrb %0, [%1, #0] @ inbc" \
113 : "=r" (result) : "r" ((port))); \
114 result; \
115})
116
117#define __outwc(value,port) \
118({ \
119 unsigned long v = value; \
120 if (__PORT_PCIO((port))) \
121 __asm__ __volatile__( \
122 "strh %0, [%1, %2] @ outwc" \
123 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
124 else \
125 __asm__ __volatile__( \
126 "strh %0, [%1, #0] @ outwc" \
127 : : "r" (v), "r" ((port))); \
128})
129
130#define __inwc(port) \
131({ \
132 unsigned short result; \
133 if (__PORT_PCIO((port))) \
134 __asm__ __volatile__( \
135 "ldrh %0, [%1, %2] @ inwc" \
136 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
137 else \
138 __asm__ __volatile__( \
139 "ldrh %0, [%1, #0] @ inwc" \
140 : "=r" (result) : "r" ((port))); \
141 result; \
142})
143
144#define __outlc(value,port) \
145({ \
146 unsigned long v = value; \
147 if (__PORT_PCIO((port))) \
148 __asm__ __volatile__( \
149 "str %0, [%1, %2] @ outlc" \
150 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
151 else \
152 __asm__ __volatile__( \
153 "str %0, [%1, #0] @ outlc" \
154 : : "r" (v), "r" ((port))); \
155})
156
157#define __inlc(port) \
158({ \
159 unsigned long result; \
160 if (__PORT_PCIO((port))) \
161 __asm__ __volatile__( \
162 "ldr %0, [%1, %2] @ inlc" \
163 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
164 else \
165 __asm__ __volatile__( \
166 "ldr %0, [%1, #0] @ inlc" \
167 : "=r" (result) : "r" ((port))); \
168 result; \
169})
170
171#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
172
173#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
174#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
175#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
176#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
177#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
178#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
179#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
180/* the following macro is deprecated */
181#define ioaddr(port) __ioaddr((port))
182
183#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
184#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
185#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l)
186
187#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
188#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
189#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l)
190
191/*
192 * 1:1 mapping for ioremapped regions.
193 */
194#define __mem_pci(x) (x)
195
196#endif
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
new file mode 100644
index 000000000000..d9773d697268
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -0,0 +1,126 @@
1/* linux/include/asm-arm/arch-s3c2410/irqs.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Changelog:
11 * 12-May-2003 BJD Created file
12 * 08-Jan-2003 BJD Linux 2.6.0 version, moved BAST bits out
13 * 12-Mar-2004 BJD Fixed bug in header protection
14 * 10-Feb-2005 BJD Added camera IRQ from guillaume.gourat@nexvision.tv
15 * 28-Feb-2005 BJD Updated s3c2440 IRQs
16 */
17
18
19#ifndef __ASM_ARCH_IRQS_H
20#define __ASM_ARCH_IRQS_H __FILE__
21
22
23/* we keep the first set of CPU IRQs out of the range of
24 * the ISA space, so that the PC104 has them to itself
25 * and we don't end up having to do horrible things to the
26 * standard ISA drivers....
27 */
28
29#define S3C2410_CPUIRQ_OFFSET (16)
30
31#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
32
33/* main cpu interrupts */
34#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
35#define IRQ_EINT1 S3C2410_IRQ(1)
36#define IRQ_EINT2 S3C2410_IRQ(2)
37#define IRQ_EINT3 S3C2410_IRQ(3)
38#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
39#define IRQ_EINT8t23 S3C2410_IRQ(5)
40#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
41#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440 */
42#define IRQ_BATT_FLT S3C2410_IRQ(7)
43#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
44#define IRQ_WDT S3C2410_IRQ(9)
45#define IRQ_TIMER0 S3C2410_IRQ(10)
46#define IRQ_TIMER1 S3C2410_IRQ(11)
47#define IRQ_TIMER2 S3C2410_IRQ(12)
48#define IRQ_TIMER3 S3C2410_IRQ(13)
49#define IRQ_TIMER4 S3C2410_IRQ(14)
50#define IRQ_UART2 S3C2410_IRQ(15)
51#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
52#define IRQ_DMA0 S3C2410_IRQ(17)
53#define IRQ_DMA1 S3C2410_IRQ(18)
54#define IRQ_DMA2 S3C2410_IRQ(19)
55#define IRQ_DMA3 S3C2410_IRQ(20)
56#define IRQ_SDI S3C2410_IRQ(21)
57#define IRQ_SPI0 S3C2410_IRQ(22)
58#define IRQ_UART1 S3C2410_IRQ(23)
59#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
60#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
61#define IRQ_USBD S3C2410_IRQ(25)
62#define IRQ_USBH S3C2410_IRQ(26)
63#define IRQ_IIC S3C2410_IRQ(27)
64#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
65#define IRQ_SPI1 S3C2410_IRQ(29)
66#define IRQ_RTC S3C2410_IRQ(30)
67#define IRQ_ADCPARENT S3C2410_IRQ(31)
68
69/* interrupts generated from the external interrupts sources */
70#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
71#define IRQ_EINT5 S3C2410_IRQ(33)
72#define IRQ_EINT6 S3C2410_IRQ(34)
73#define IRQ_EINT7 S3C2410_IRQ(35)
74#define IRQ_EINT8 S3C2410_IRQ(36)
75#define IRQ_EINT9 S3C2410_IRQ(37)
76#define IRQ_EINT10 S3C2410_IRQ(38)
77#define IRQ_EINT11 S3C2410_IRQ(39)
78#define IRQ_EINT12 S3C2410_IRQ(40)
79#define IRQ_EINT13 S3C2410_IRQ(41)
80#define IRQ_EINT14 S3C2410_IRQ(42)
81#define IRQ_EINT15 S3C2410_IRQ(43)
82#define IRQ_EINT16 S3C2410_IRQ(44)
83#define IRQ_EINT17 S3C2410_IRQ(45)
84#define IRQ_EINT18 S3C2410_IRQ(46)
85#define IRQ_EINT19 S3C2410_IRQ(47)
86#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */
87#define IRQ_EINT21 S3C2410_IRQ(49)
88#define IRQ_EINT22 S3C2410_IRQ(50)
89#define IRQ_EINT23 S3C2410_IRQ(51)
90
91
92#define IRQ_EINT(x) S3C2410_IRQ((x >= 4) ? (IRQ_EINT4 + (x) - 4) : (S3C2410_IRQ(0) + (x)))
93
94#define IRQ_LCD_FIFO S3C2410_IRQ(52)
95#define IRQ_LCD_FRAME S3C2410_IRQ(53)
96
97/* IRQs for the interal UARTs, and ADC
98 * these need to be ordered in number of appearance in the
99 * SUBSRC mask register
100*/
101#define IRQ_S3CUART_RX0 S3C2410_IRQ(54) /* 70 */
102#define IRQ_S3CUART_TX0 S3C2410_IRQ(55) /* 71 */
103#define IRQ_S3CUART_ERR0 S3C2410_IRQ(56)
104
105#define IRQ_S3CUART_RX1 S3C2410_IRQ(57)
106#define IRQ_S3CUART_TX1 S3C2410_IRQ(58)
107#define IRQ_S3CUART_ERR1 S3C2410_IRQ(59)
108
109#define IRQ_S3CUART_RX2 S3C2410_IRQ(60)
110#define IRQ_S3CUART_TX2 S3C2410_IRQ(61)
111#define IRQ_S3CUART_ERR2 S3C2410_IRQ(62)
112
113#define IRQ_TC S3C2410_IRQ(63)
114#define IRQ_ADC S3C2410_IRQ(64)
115
116/* extra irqs for s3c2440 */
117
118#define IRQ_S3C2440_CAM_C S3C2410_IRQ(65)
119#define IRQ_S3C2440_CAM_P S3C2410_IRQ(66)
120#define IRQ_S3C2440_WDT S3C2410_IRQ(67)
121#define IRQ_S3C2440_AC97 S3C2410_IRQ(68)
122
123#define NR_IRQS (IRQ_S3C2440_AC97+1)
124
125
126#endif /* __ASM_ARCH_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
new file mode 100644
index 000000000000..1833ea5c4220
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -0,0 +1,192 @@
1/* linux/include/asm-arm/arch-s3c2410/map.h
2 *
3 * (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 12-May-2003 BJD Created file
14 * 06-Jan-2003 BJD Linux 2.6.0 version, moved bast specifics out
15 * 10-Feb-2005 BJD Added CAMIF definition from guillaume.gourat@nexvision.tv
16 * 10-Mar-2005 LCVR Added support to S3C2400, changed {VA,SZ} names
17*/
18
19#ifndef __ASM_ARCH_MAP_H
20#define __ASM_ARCH_MAP_H
21
22/* we have a bit of a tight squeeze to fit all our registers from
23 * 0xF00000000 upwards, since we use all of the nGCS space in some
24 * capacity, and also need to fit the S3C2410 registers in as well...
25 *
26 * we try to ensure stuff like the IRQ registers are available for
27 * an single MOVS instruction (ie, only 8 bits of set data)
28 *
29 * Note, we are trying to remove some of these from the implementation
30 * as they are only useful to certain drivers...
31 */
32
33#ifndef __ASSEMBLY__
34#define S3C2410_ADDR(x) ((void __iomem *)0xF0000000 + (x))
35#else
36#define S3C2410_ADDR(x) (0xF0000000 + (x))
37#endif
38
39#define S3C2400_ADDR(x) S3C2410_ADDR(x)
40
41/* interrupt controller is the first thing we put in, to make
42 * the assembly code for the irq detection easier
43 */
44#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
45#define S3C2400_PA_IRQ (0x14400000)
46#define S3C2410_PA_IRQ (0x4A000000)
47#define S3C24XX_SZ_IRQ SZ_1M
48
49/* memory controller registers */
50#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
51#define S3C2400_PA_MEMCTRL (0x14000000)
52#define S3C2410_PA_MEMCTRL (0x48000000)
53#define S3C24XX_SZ_MEMCTRL SZ_1M
54
55/* USB host controller */
56#define S3C24XX_VA_USBHOST S3C2410_ADDR(0x00200000)
57#define S3C2400_PA_USBHOST (0x14200000)
58#define S3C2410_PA_USBHOST (0x49000000)
59#define S3C24XX_SZ_USBHOST SZ_1M
60
61/* DMA controller */
62#define S3C24XX_VA_DMA S3C2410_ADDR(0x00300000)
63#define S3C2400_PA_DMA (0x14600000)
64#define S3C2410_PA_DMA (0x4B000000)
65#define S3C24XX_SZ_DMA SZ_1M
66
67/* Clock and Power management */
68#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00400000)
69#define S3C2400_PA_CLKPWR (0x14800000)
70#define S3C2410_PA_CLKPWR (0x4C000000)
71#define S3C24XX_SZ_CLKPWR SZ_1M
72
73/* LCD controller */
74#define S3C24XX_VA_LCD S3C2410_ADDR(0x00600000)
75#define S3C2400_PA_LCD (0x14A00000)
76#define S3C2410_PA_LCD (0x4D000000)
77#define S3C24XX_SZ_LCD SZ_1M
78
79/* NAND flash controller */
80#define S3C24XX_VA_NAND S3C2410_ADDR(0x00700000)
81#define S3C2410_PA_NAND (0x4E000000)
82#define S3C24XX_SZ_NAND SZ_1M
83
84/* MMC controller - available on the S3C2400 */
85#define S3C2400_VA_MMC S3C2400_ADDR(0x00700000)
86#define S3C2400_PA_MMC (0x15A00000)
87#define S3C2400_SZ_MMC SZ_1M
88
89/* UARTs */
90#define S3C24XX_VA_UART S3C2410_ADDR(0x00800000)
91#define S3C2400_PA_UART (0x15000000)
92#define S3C2410_PA_UART (0x50000000)
93#define S3C24XX_SZ_UART SZ_1M
94
95/* Timers */
96#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00900000)
97#define S3C2400_PA_TIMER (0x15100000)
98#define S3C2410_PA_TIMER (0x51000000)
99#define S3C24XX_SZ_TIMER SZ_1M
100
101/* USB Device port */
102#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00A00000)
103#define S3C2400_PA_USBDEV (0x15200140)
104#define S3C2410_PA_USBDEV (0x52000000)
105#define S3C24XX_SZ_USBDEV SZ_1M
106
107/* Watchdog */
108#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
109#define S3C2400_PA_WATCHDOG (0x15300000)
110#define S3C2410_PA_WATCHDOG (0x53000000)
111#define S3C24XX_SZ_WATCHDOG SZ_1M
112
113/* IIC hardware controller */
114#define S3C24XX_VA_IIC S3C2410_ADDR(0x00C00000)
115#define S3C2400_PA_IIC (0x15400000)
116#define S3C2410_PA_IIC (0x54000000)
117#define S3C24XX_SZ_IIC SZ_1M
118
119#define VA_IIC_BASE (S3C24XX_VA_IIC)
120
121/* IIS controller */
122#define S3C24XX_VA_IIS S3C2410_ADDR(0x00D00000)
123#define S3C2400_PA_IIS (0x15508000)
124#define S3C2410_PA_IIS (0x55000000)
125#define S3C24XX_SZ_IIS SZ_1M
126
127/* GPIO ports */
128#define S3C24XX_VA_GPIO S3C2410_ADDR(0x00E00000)
129#define S3C2400_PA_GPIO (0x15600000)
130#define S3C2410_PA_GPIO (0x56000000)
131#define S3C24XX_SZ_GPIO SZ_1M
132
133/* RTC */
134#define S3C24XX_VA_RTC S3C2410_ADDR(0x00F00000)
135#define S3C2400_PA_RTC (0x15700040)
136#define S3C2410_PA_RTC (0x57000000)
137#define S3C24XX_SZ_RTC SZ_1M
138
139/* ADC */
140#define S3C24XX_VA_ADC S3C2410_ADDR(0x01000000)
141#define S3C2400_PA_ADC (0x15800000)
142#define S3C2410_PA_ADC (0x58000000)
143#define S3C24XX_SZ_ADC SZ_1M
144
145/* SPI */
146#define S3C24XX_VA_SPI S3C2410_ADDR(0x01100000)
147#define S3C2400_PA_SPI (0x15900000)
148#define S3C2410_PA_SPI (0x59000000)
149#define S3C24XX_SZ_SPI SZ_1M
150
151/* SDI */
152#define S3C24XX_VA_SDI S3C2410_ADDR(0x01200000)
153#define S3C2410_PA_SDI (0x5A000000)
154#define S3C24XX_SZ_SDI SZ_1M
155
156/* CAMIF */
157#define S3C2440_PA_CAMIF (0x4F000000)
158#define S3C2440_SZ_CAMIF SZ_1M
159
160/* ISA style IO, for each machine to sort out mappings for, if it
161 * implements it. We reserve two 16M regions for ISA.
162 */
163
164#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
165#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
166
167/* physical addresses of all the chip-select areas */
168
169#define S3C2410_CS0 (0x00000000)
170#define S3C2410_CS1 (0x08000000)
171#define S3C2410_CS2 (0x10000000)
172#define S3C2410_CS3 (0x18000000)
173#define S3C2410_CS4 (0x20000000)
174#define S3C2410_CS5 (0x28000000)
175#define S3C2410_CS6 (0x30000000)
176#define S3C2410_CS7 (0x38000000)
177
178#define S3C2410_SDRAM_PA (S3C2410_CS6)
179
180#define S3C2400_CS0 (0x00000000)
181#define S3C2400_CS1 (0x02000000)
182#define S3C2400_CS2 (0x04000000)
183#define S3C2400_CS3 (0x06000000)
184#define S3C2400_CS4 (0x08000000)
185#define S3C2400_CS5 (0x0A000000)
186#define S3C2400_CS6 (0x0C000000)
187#define S3C2400_CS7 (0x0E000000)
188
189#define S3C2400_SDRAM_PA (S3C2400_CS6)
190
191
192#endif /* __ASM_ARCH_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
new file mode 100644
index 000000000000..3380ab1d0749
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -0,0 +1,44 @@
1/*
2 * linux/include/asm-arm/arch-s3c2410/memory.h
3 *
4 * from linux/include/asm-arm/arch-rpc/memory.h
5 *
6 * Copyright (C) 1996,1997,1998 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 20-Oct-1996 RMK Created
14 * 31-Dec-1997 RMK Fixed definitions to reduce warnings
15 * 11-Jan-1998 RMK Uninlined to reduce hits on cache
16 * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
17 * 21-Mar-1999 RMK Renamed to memory.h
18 * RMK Added TASK_SIZE and PAGE_OFFSET
19 * 05-Apr-2004 BJD Copied and altered for arch-s3c2410
20 * 17-Mar-2005 LCVR Modified for S3C2400
21*/
22
23#ifndef __ASM_ARCH_MEMORY_H
24#define __ASM_ARCH_MEMORY_H
25
26/*
27 * DRAM starts at 0x30000000 for S3C2410/S3C2440
28 * and at 0x0C000000 for S3C2400
29 */
30#ifdef CONFIG_CPU_S3C2400
31#define PHYS_OFFSET (0x0C000000UL)
32#else
33#define PHYS_OFFSET (0x30000000UL)
34#endif
35
36/*
37 * These are exactly the same on the S3C2410 as the
38 * physical memory view.
39*/
40
41#define __virt_to_bus(x) __virt_to_phys(x)
42#define __bus_to_virt(x) __phys_to_virt(x)
43
44#endif
diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/arch-s3c2410/nand.h
new file mode 100644
index 000000000000..9148ac045b0d
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/nand.h
@@ -0,0 +1,48 @@
1/* linux/include/asm-arm/arch-s3c2410/nand.h
2 *
3 * (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - NAND device controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 23-Sep-2004 BJD Created file
14*/
15
16/* struct s3c2410_nand_set
17 *
18 * define an set of one or more nand chips registered with an unique mtd
19 *
20 * nr_chips = number of chips in this set
21 * nr_partitions = number of partitions pointed to be partitoons (or zero)
22 * name = name of set (optional)
23 * nr_map = map for low-layer logical to physical chip numbers (option)
24 * partitions = mtd partition list
25*/
26
27struct s3c2410_nand_set {
28 int nr_chips;
29 int nr_partitions;
30 char *name;
31 int *nr_map;
32 struct mtd_partition *partitions;
33};
34
35struct s3c2410_platform_nand {
36 /* timing information for controller, all times in nanoseconds */
37
38 int tacls; /* time for active CLE/ALE to nWE/nOE */
39 int twrph0; /* active time for nWE/nOE */
40 int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
41
42 int nr_sets;
43 struct s3c2410_nand_set *sets;
44
45 void (*select_chip)(struct s3c2410_nand_set *,
46 int chip);
47};
48
diff --git a/include/asm-arm/arch-s3c2410/otom-map.h b/include/asm-arm/arch-s3c2410/otom-map.h
new file mode 100644
index 000000000000..e40c93429854
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/otom-map.h
@@ -0,0 +1,30 @@
1/* linux/include/asm-arm/arch-s3c2410/otom-map.h
2 *
3 * (c) 2005 Guillaume GOURAT / NexVision
4 * guillaume.gourat@nexvision.fr
5 *
6 * NexVision OTOM board memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* needs arch/map.h including with this */
14
15/* ok, we've used up to 0x01300000, now we need to find space for the
16 * peripherals that live in the nGCS[x] areas, which are quite numerous
17 * in their space.
18 */
19
20#ifndef __ASM_ARCH_OTOMMAP_H
21#define __ASM_ARCH_OTOMMAP_H
22
23#define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */
24#define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */
25
26/* physical offset addresses for the peripherals */
27
28#define OTOM_PA_FLASH0_BASE (S3C2410_CS0) /* Bank 0 */
29
30#endif /* __ASM_ARCH_OTOMMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/param.h b/include/asm-arm/arch-s3c2410/param.h
new file mode 100644
index 000000000000..483d3f149883
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/param.h
@@ -0,0 +1,27 @@
1/* linux/include/asm-arm/arch-s3c2410/param.h
2 *
3 * (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - Machine parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 02-Sep-2003 BJD Created file
14 * 12-Mar-2004 BJD Added include protection
15*/
16
17#ifndef __ASM_ARCH_PARAM_H
18#define __ASM_ARCH_PARAM_H
19
20/* we cannot get our timer down to 100Hz with the setup as is, but we can
21 * manage 200 clock ticks per second... if this is a problem, we can always
22 * add a software pre-scaler to the evil timer systems.
23*/
24
25#define HZ 200
26
27#endif /* __ASM_ARCH_PARAM_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/arch-s3c2410/regs-adc.h
new file mode 100644
index 000000000000..15bfc2f5754e
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-adc.h
@@ -0,0 +1,63 @@
1/* linux/include/asm/arch-s3c2410/regs-adc.h
2 *
3 * Copyright (c) 2004 Shannon Holland <holland@loser.net>
4 *
5 * This program is free software; yosu can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 ADC registers
10 *
11 * Changelog:
12 * 27-09-2004 SAH Created file
13*/
14
15#ifndef __ASM_ARCH_REGS_ADC_H
16#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
17
18#define S3C2410_ADCREG(x) (x)
19
20#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
21#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
22#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
23#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
24#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
25
26
27/* ADCCON Register Bits */
28#define S3C2410_ADCCON_ECFLG (1<<15)
29#define S3C2410_ADCCON_PRSCEN (1<<14)
30#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
31#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
32#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
33#define S3C2410_ADCCON_MUXMASK (0x7<<3)
34#define S3C2410_ADCCON_STDBM (1<<2)
35#define S3C2410_ADCCON_READ_START (1<<1)
36#define S3C2410_ADCCON_ENABLE_START (1<<0)
37#define S3C2410_ADCCON_STARTMASK (0x3<<0)
38
39
40/* ADCTSC Register Bits */
41#define S3C2410_ADCTSC_YM_SEN (1<<7)
42#define S3C2410_ADCTSC_YP_SEN (1<<6)
43#define S3C2410_ADCTSC_XM_SEN (1<<5)
44#define S3C2410_ADCTSC_XP_SEN (1<<4)
45#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
46#define S3C2410_ADCTSC_AUTO_PST (1<<2)
47#define S3C2410_ADCTSC_XY_PST (0x3<<0)
48
49/* ADCDAT0 Bits */
50#define S3C2410_ADCDAT0_UPDOWN (1<<15)
51#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
52#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
53#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
54
55/* ADCDAT1 Bits */
56#define S3C2410_ADCDAT1_UPDOWN (1<<15)
57#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
58#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
59#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
60
61#endif /* __ASM_ARCH_REGS_ADC_H */
62
63
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
new file mode 100644
index 000000000000..e5e938b79acc
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -0,0 +1,122 @@
1/* linux/include/asm/arch-s3c2410/regs-clock.h
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 clock register definitions
11 *
12 * Changelog:
13 * 18-Aug-2004 Ben Dooks Added 2440 definitions
14 * 08-Aug-2004 Herbert Pötzl Added CLKCON definitions
15 * 19-06-2003 Ben Dooks Created file
16 * 12-03-2004 Ben Dooks Updated include protection
17 * 29-Sep-2004 Ben Dooks Fixed usage for assembly inclusion
18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
20 */
21
22#ifndef __ASM_ARM_REGS_CLOCK
23#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
24
25#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
26
27#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
28
29#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
30#define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
31#define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
32#define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
33#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
34#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
35
36#define S3C2410_CLKCON_IDLE (1<<2)
37#define S3C2410_CLKCON_POWER (1<<3)
38#define S3C2410_CLKCON_NAND (1<<4)
39#define S3C2410_CLKCON_LCDC (1<<5)
40#define S3C2410_CLKCON_USBH (1<<6)
41#define S3C2410_CLKCON_USBD (1<<7)
42#define S3C2410_CLKCON_PWMT (1<<8)
43#define S3C2410_CLKCON_SDI (1<<9)
44#define S3C2410_CLKCON_UART0 (1<<10)
45#define S3C2410_CLKCON_UART1 (1<<11)
46#define S3C2410_CLKCON_UART2 (1<<12)
47#define S3C2410_CLKCON_GPIO (1<<13)
48#define S3C2410_CLKCON_RTC (1<<14)
49#define S3C2410_CLKCON_ADC (1<<15)
50#define S3C2410_CLKCON_IIC (1<<16)
51#define S3C2410_CLKCON_IIS (1<<17)
52#define S3C2410_CLKCON_SPI (1<<18)
53
54#define S3C2410_PLLCON_MDIVSHIFT 12
55#define S3C2410_PLLCON_PDIVSHIFT 4
56#define S3C2410_PLLCON_SDIVSHIFT 0
57#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
58#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
59#define S3C2410_PLLCON_SDIVMASK 3
60
61/* DCLKCON register addresses in gpio.h */
62
63#define S3C2410_DCLKCON_DCLK0EN (1<<0)
64#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
65#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
66#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
67#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
68
69#define S3C2410_DCLKCON_DCLK1EN (1<<16)
70#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
71#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
72#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
73
74#define S3C2410_CLKDIVN_PDIVN (1<<0)
75#define S3C2410_CLKDIVN_HDIVN (1<<1)
76
77#ifndef __ASSEMBLY__
78
79static inline unsigned int
80s3c2410_get_pll(int pllval, int baseclk)
81{
82 int mdiv, pdiv, sdiv;
83
84 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
85 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
86 sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
87
88 mdiv &= S3C2410_PLLCON_MDIVMASK;
89 pdiv &= S3C2410_PLLCON_PDIVMASK;
90 sdiv &= S3C2410_PLLCON_SDIVMASK;
91
92 return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
93}
94
95#endif /* __ASSEMBLY__ */
96
97#ifdef CONFIG_CPU_S3C2440
98
99/* extra registers */
100#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
101
102#define S3C2440_CLKCON_CAMERA (1<<19)
103#define S3C2440_CLKCON_AC97 (1<<20)
104
105#define S3C2440_CLKDIVN_PDIVN (1<<0)
106#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
107#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
108#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
109#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
110#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
111#define S3C2440_CLKDIVN_UCLK (1<<3)
112
113#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
114#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
115#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
116#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
117#define S3C2440_CAMDIVN_DVSEN (1<<12)
118
119#endif /* CONFIG_CPU_S3C2440 */
120
121
122#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
new file mode 100644
index 000000000000..a023b0434efe
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -0,0 +1,183 @@
1/* linux/include/asm/hardware/s3c2410/regs-dsc.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440 Signal Drive Strength Control
11 *
12 * Changelog:
13 * 11-Aug-2004 BJD Created file
14 * 25-Aug-2004 BJD Added the _SELECT_* defs for using with functions
15*/
16
17
18#ifndef __ASM_ARCH_REGS_DSC_H
19#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
20
21#ifdef CONFIG_CPU_S3C2440
22
23#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
24#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
25
26#define S3C2440_SELECT_DSC0 (0)
27#define S3C2440_SELECT_DSC1 (1<<31)
28
29#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
30
31#define S3C2440_DSC0_DISABLE (1<<31)
32
33#define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8)
34#define S3C2440_DSC0_ADDR_12mA (0<<8)
35#define S3C2440_DSC0_ADDR_10mA (1<<8)
36#define S3C2440_DSC0_ADDR_8mA (2<<8)
37#define S3C2440_DSC0_ADDR_6mA (3<<8)
38#define S3C2440_DSC0_ADDR_MASK (3<<8)
39
40/* D24..D31 */
41#define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6)
42#define S3C2440_DSC0_DATA3_12mA (0<<6)
43#define S3C2440_DSC0_DATA3_10mA (1<<6)
44#define S3C2440_DSC0_DATA3_8mA (2<<6)
45#define S3C2440_DSC0_DATA3_6mA (3<<6)
46#define S3C2440_DSC0_DATA3_MASK (3<<6)
47
48/* D16..D23 */
49#define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4)
50#define S3C2440_DSC0_DATA2_12mA (0<<4)
51#define S3C2440_DSC0_DATA2_10mA (1<<4)
52#define S3C2440_DSC0_DATA2_8mA (2<<4)
53#define S3C2440_DSC0_DATA2_6mA (3<<4)
54#define S3C2440_DSC0_DATA2_MASK (3<<4)
55
56/* D8..D15 */
57#define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2)
58#define S3C2440_DSC0_DATA1_12mA (0<<2)
59#define S3C2440_DSC0_DATA1_10mA (1<<2)
60#define S3C2440_DSC0_DATA1_8mA (2<<2)
61#define S3C2440_DSC0_DATA1_6mA (3<<2)
62#define S3C2440_DSC0_DATA1_MASK (3<<2)
63
64/* D0..D7 */
65#define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0)
66#define S3C2440_DSC0_DATA0_12mA (0<<0)
67#define S3C2440_DSC0_DATA0_10mA (1<<0)
68#define S3C2440_DSC0_DATA0_8mA (2<<0)
69#define S3C2440_DSC0_DATA0_6mA (3<<0)
70#define S3C2440_DSC0_DATA0_MASK (3<<0)
71
72#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28)
73#define S3C2440_DSC1_SCK1_12mA (0<<28)
74#define S3C2440_DSC1_SCK1_10mA (1<<28)
75#define S3C2440_DSC1_SCK1_8mA (2<<28)
76#define S3C2440_DSC1_SCK1_6mA (3<<28)
77#define S3C2440_DSC1_SCK1_MASK (3<<28)
78
79#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26)
80#define S3C2440_DSC1_SCK0_12mA (0<<26)
81#define S3C2440_DSC1_SCK0_10mA (1<<26)
82#define S3C2440_DSC1_SCK0_8mA (2<<26)
83#define S3C2440_DSC1_SCK0_6mA (3<<26)
84#define S3C2440_DSC1_SCK0_MASK (3<<26)
85
86#define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24)
87#define S3C2440_DSC1_SCKE_10mA (0<<24)
88#define S3C2440_DSC1_SCKE_8mA (1<<24)
89#define S3C2440_DSC1_SCKE_6mA (2<<24)
90#define S3C2440_DSC1_SCKE_4mA (3<<24)
91#define S3C2440_DSC1_SCKE_MASK (3<<24)
92
93/* SDRAM nRAS/nCAS */
94#define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22)
95#define S3C2440_DSC1_SDR_10mA (0<<22)
96#define S3C2440_DSC1_SDR_8mA (1<<22)
97#define S3C2440_DSC1_SDR_6mA (2<<22)
98#define S3C2440_DSC1_SDR_4mA (3<<22)
99#define S3C2440_DSC1_SDR_MASK (3<<22)
100
101/* NAND Flash Controller */
102#define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20)
103#define S3C2440_DSC1_NFC_10mA (0<<20)
104#define S3C2440_DSC1_NFC_8mA (1<<20)
105#define S3C2440_DSC1_NFC_6mA (2<<20)
106#define S3C2440_DSC1_NFC_4mA (3<<20)
107#define S3C2440_DSC1_NFC_MASK (3<<20)
108
109/* nBE[0..3] */
110#define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18)
111#define S3C2440_DSC1_nBE_10mA (0<<18)
112#define S3C2440_DSC1_nBE_8mA (1<<18)
113#define S3C2440_DSC1_nBE_6mA (2<<18)
114#define S3C2440_DSC1_nBE_4mA (3<<18)
115#define S3C2440_DSC1_nBE_MASK (3<<18)
116
117#define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16)
118#define S3C2440_DSC1_WOE_10mA (0<<16)
119#define S3C2440_DSC1_WOE_8mA (1<<16)
120#define S3C2440_DSC1_WOE_6mA (2<<16)
121#define S3C2440_DSC1_WOE_4mA (3<<16)
122#define S3C2440_DSC1_WOE_MASK (3<<16)
123
124#define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14)
125#define S3C2440_DSC1_CS7_10mA (0<<14)
126#define S3C2440_DSC1_CS7_8mA (1<<14)
127#define S3C2440_DSC1_CS7_6mA (2<<14)
128#define S3C2440_DSC1_CS7_4mA (3<<14)
129#define S3C2440_DSC1_CS7_MASK (3<<14)
130
131#define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12)
132#define S3C2440_DSC1_CS6_10mA (0<<12)
133#define S3C2440_DSC1_CS6_8mA (1<<12)
134#define S3C2440_DSC1_CS6_6mA (2<<12)
135#define S3C2440_DSC1_CS6_4mA (3<<12)
136#define S3C2440_DSC1_CS6_MASK (3<<12)
137
138#define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10)
139#define S3C2440_DSC1_CS5_10mA (0<<10)
140#define S3C2440_DSC1_CS5_8mA (1<<10)
141#define S3C2440_DSC1_CS5_6mA (2<<10)
142#define S3C2440_DSC1_CS5_4mA (3<<10)
143#define S3C2440_DSC1_CS5_MASK (3<<10)
144
145#define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8)
146#define S3C2440_DSC1_CS4_10mA (0<<8)
147#define S3C2440_DSC1_CS4_8mA (1<<8)
148#define S3C2440_DSC1_CS4_6mA (2<<8)
149#define S3C2440_DSC1_CS4_4mA (3<<8)
150#define S3C2440_DSC1_CS4_MASK (3<<8)
151
152#define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6)
153#define S3C2440_DSC1_CS3_10mA (0<<6)
154#define S3C2440_DSC1_CS3_8mA (1<<6)
155#define S3C2440_DSC1_CS3_6mA (2<<6)
156#define S3C2440_DSC1_CS3_4mA (3<<6)
157#define S3C2440_DSC1_CS3_MASK (3<<6)
158
159#define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4)
160#define S3C2440_DSC1_CS2_10mA (0<<4)
161#define S3C2440_DSC1_CS2_8mA (1<<4)
162#define S3C2440_DSC1_CS2_6mA (2<<4)
163#define S3C2440_DSC1_CS2_4mA (3<<4)
164#define S3C2440_DSC1_CS2_MASK (3<<4)
165
166#define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2)
167#define S3C2440_DSC1_CS1_10mA (0<<2)
168#define S3C2440_DSC1_CS1_8mA (1<<2)
169#define S3C2440_DSC1_CS1_6mA (2<<2)
170#define S3C2440_DSC1_CS1_4mA (3<<2)
171#define S3C2440_DSC1_CS1_MASK (3<<2)
172
173#define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0
174#define S3C2440_DSC1_CS0_10mA (0<<0)
175#define S3C2440_DSC1_CS0_8mA (1<<0)
176#define S3C2440_DSC1_CS0_6mA (2<<0)
177#define S3C2440_DSC1_CS0_4mA (3<<0)
178#define S3C2440_DSC1_CS0_MASK (3<<0)
179
180#endif /* CONFIG_CPU_S3C2440 */
181
182#endif /* __ASM_ARCH_REGS_DSC_H */
183
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
new file mode 100644
index 000000000000..2053cbacffc3
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -0,0 +1,831 @@
1/* linux/include/asm/hardware/s3c2410/regs-gpio.h
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 GPIO register definitions
11 *
12 * Changelog:
13 * 19-06-2003 BJD Created file
14 * 23-06-2003 BJD Updated GSTATUS registers
15 * 12-03-2004 BJD Updated include protection
16 * 20-07-2004 BJD Added GPIO pin numbers, added Port A definitions
17 * 04-10-2004 BJD Fixed number of bugs, added EXT IRQ filter defs
18 * 17-10-2004 BJD Added GSTATUS1 register definitions
19 * 18-11-2004 BJD Fixed definitions of GPE3, GPE4, GPE5 and GPE6
20 * 18-11-2004 BJD Added S3C2440 AC97 controls
21 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
22 * 28-Mar-2005 LCVR Fixed definition of GPB10
23*/
24
25
26#ifndef __ASM_ARCH_REGS_GPIO_H
27#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
28
29#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
30
31#define S3C2410_GPIO_BANKA (32*0)
32#define S3C2410_GPIO_BANKB (32*1)
33#define S3C2410_GPIO_BANKC (32*2)
34#define S3C2410_GPIO_BANKD (32*3)
35#define S3C2410_GPIO_BANKE (32*4)
36#define S3C2410_GPIO_BANKF (32*5)
37#define S3C2410_GPIO_BANKG (32*6)
38#define S3C2410_GPIO_BANKH (32*7)
39
40#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
41#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
42
43/* general configuration options */
44
45#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
46
47/* configure GPIO ports A..G */
48
49#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
50
51/* port A - 22bits, zero in bit X makes pin X output
52 * 1 makes port special function, this is default
53*/
54#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
55#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
56
57#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
58#define S3C2410_GPA0_OUT (0<<0)
59#define S3C2410_GPA0_ADDR0 (1<<0)
60
61#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
62#define S3C2410_GPA1_OUT (0<<1)
63#define S3C2410_GPA1_ADDR16 (1<<1)
64
65#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
66#define S3C2410_GPA2_OUT (0<<2)
67#define S3C2410_GPA2_ADDR17 (1<<2)
68
69#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
70#define S3C2410_GPA3_OUT (0<<3)
71#define S3C2410_GPA3_ADDR18 (1<<3)
72
73#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
74#define S3C2410_GPA4_OUT (0<<4)
75#define S3C2410_GPA4_ADDR19 (1<<4)
76
77#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
78#define S3C2410_GPA5_OUT (0<<5)
79#define S3C2410_GPA5_ADDR20 (1<<5)
80
81#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
82#define S3C2410_GPA6_OUT (0<<6)
83#define S3C2410_GPA6_ADDR21 (1<<6)
84
85#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
86#define S3C2410_GPA7_OUT (0<<7)
87#define S3C2410_GPA7_ADDR22 (1<<7)
88
89#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
90#define S3C2410_GPA8_OUT (0<<8)
91#define S3C2410_GPA8_ADDR23 (1<<8)
92
93#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
94#define S3C2410_GPA9_OUT (0<<9)
95#define S3C2410_GPA9_ADDR24 (1<<9)
96
97#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
98#define S3C2410_GPA10_OUT (0<<10)
99#define S3C2410_GPA10_ADDR25 (1<<10)
100
101#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
102#define S3C2410_GPA11_OUT (0<<11)
103#define S3C2410_GPA11_ADDR26 (1<<11)
104
105#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
106#define S3C2410_GPA12_OUT (0<<12)
107#define S3C2410_GPA12_nGCS1 (1<<12)
108
109#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
110#define S3C2410_GPA13_OUT (0<<13)
111#define S3C2410_GPA13_nGCS2 (1<<13)
112
113#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
114#define S3C2410_GPA14_OUT (0<<14)
115#define S3C2410_GPA14_nGCS3 (1<<14)
116
117#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
118#define S3C2410_GPA15_OUT (0<<15)
119#define S3C2410_GPA15_nGCS4 (1<<15)
120
121#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
122#define S3C2410_GPA16_OUT (0<<16)
123#define S3C2410_GPA16_nGCS5 (1<<16)
124
125#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
126#define S3C2410_GPA17_OUT (0<<17)
127#define S3C2410_GPA17_CLE (1<<17)
128
129#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
130#define S3C2410_GPA18_OUT (0<<18)
131#define S3C2410_GPA18_ALE (1<<18)
132
133#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
134#define S3C2410_GPA19_OUT (0<<19)
135#define S3C2410_GPA19_nFWE (1<<19)
136
137#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
138#define S3C2410_GPA20_OUT (0<<20)
139#define S3C2410_GPA20_nFRE (1<<20)
140
141#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
142#define S3C2410_GPA21_OUT (0<<21)
143#define S3C2410_GPA21_nRSTOUT (1<<21)
144
145#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
146#define S3C2410_GPA22_OUT (0<<22)
147#define S3C2410_GPA22_nFCE (1<<22)
148
149/* 0x08 and 0x0c are reserved */
150
151/* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
152 * 00 = input, 01 = output, 10=special function, 11=reserved
153 * bit 0,1 = pin 0, 2,3= pin 1...
154 *
155 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
156*/
157
158#define S3C2410_GPBCON S3C2410_GPIOREG(0x10)
159#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
160#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
161
162/* no i/o pin in port b can have value 3! */
163
164#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
165#define S3C2410_GPB0_INP (0x00 << 0)
166#define S3C2410_GPB0_OUTP (0x01 << 0)
167#define S3C2410_GPB0_TOUT0 (0x02 << 0)
168
169#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
170#define S3C2410_GPB1_INP (0x00 << 2)
171#define S3C2410_GPB1_OUTP (0x01 << 2)
172#define S3C2410_GPB1_TOUT1 (0x02 << 2)
173
174#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
175#define S3C2410_GPB2_INP (0x00 << 4)
176#define S3C2410_GPB2_OUTP (0x01 << 4)
177#define S3C2410_GPB2_TOUT2 (0x02 << 4)
178
179#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
180#define S3C2410_GPB3_INP (0x00 << 6)
181#define S3C2410_GPB3_OUTP (0x01 << 6)
182#define S3C2410_GPB3_TOUT3 (0x02 << 6)
183
184#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
185#define S3C2410_GPB4_INP (0x00 << 8)
186#define S3C2410_GPB4_OUTP (0x01 << 8)
187#define S3C2410_GPB4_TCLK0 (0x02 << 8)
188#define S3C2410_GPB4_MASK (0x03 << 8)
189
190#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
191#define S3C2410_GPB5_INP (0x00 << 10)
192#define S3C2410_GPB5_OUTP (0x01 << 10)
193#define S3C2410_GPB5_nXBACK (0x02 << 10)
194
195#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
196#define S3C2410_GPB6_INP (0x00 << 12)
197#define S3C2410_GPB6_OUTP (0x01 << 12)
198#define S3C2410_GPB6_nXBREQ (0x02 << 12)
199
200#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
201#define S3C2410_GPB7_INP (0x00 << 14)
202#define S3C2410_GPB7_OUTP (0x01 << 14)
203#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
204
205#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
206#define S3C2410_GPB8_INP (0x00 << 16)
207#define S3C2410_GPB8_OUTP (0x01 << 16)
208#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
209
210#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
211#define S3C2410_GPB9_INP (0x00 << 18)
212#define S3C2410_GPB9_OUTP (0x01 << 18)
213#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
214
215#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
216#define S3C2410_GPB10_INP (0x00 << 20)
217#define S3C2410_GPB10_OUTP (0x01 << 20)
218#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
219
220/* Port C consits of 16 GPIO/Special function
221 *
222 * almost identical setup to port b, but the special functions are mostly
223 * to do with the video system's sync/etc.
224*/
225
226#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
227#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
228#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
229
230#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
231#define S3C2410_GPC0_INP (0x00 << 0)
232#define S3C2410_GPC0_OUTP (0x01 << 0)
233#define S3C2410_GPC0_LEND (0x02 << 0)
234
235#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
236#define S3C2410_GPC1_INP (0x00 << 2)
237#define S3C2410_GPC1_OUTP (0x01 << 2)
238#define S3C2410_GPC1_VCLK (0x02 << 2)
239
240#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
241#define S3C2410_GPC2_INP (0x00 << 4)
242#define S3C2410_GPC2_OUTP (0x01 << 4)
243#define S3C2410_GPC2_VLINE (0x02 << 4)
244
245#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
246#define S3C2410_GPC3_INP (0x00 << 6)
247#define S3C2410_GPC3_OUTP (0x01 << 6)
248#define S3C2410_GPC3_VFRAME (0x02 << 6)
249
250#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
251#define S3C2410_GPC4_INP (0x00 << 8)
252#define S3C2410_GPC4_OUTP (0x01 << 8)
253#define S3C2410_GPC4_VM (0x02 << 8)
254
255#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
256#define S3C2410_GPC5_INP (0x00 << 10)
257#define S3C2410_GPC5_OUTP (0x01 << 10)
258#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
259
260#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
261#define S3C2410_GPC6_INP (0x00 << 12)
262#define S3C2410_GPC6_OUTP (0x01 << 12)
263#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
264
265#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
266#define S3C2410_GPC7_INP (0x00 << 14)
267#define S3C2410_GPC7_OUTP (0x01 << 14)
268#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
269
270#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
271#define S3C2410_GPC8_INP (0x00 << 16)
272#define S3C2410_GPC8_OUTP (0x01 << 16)
273#define S3C2410_GPC8_VD0 (0x02 << 16)
274
275#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
276#define S3C2410_GPC9_INP (0x00 << 18)
277#define S3C2410_GPC9_OUTP (0x01 << 18)
278#define S3C2410_GPC9_VD1 (0x02 << 18)
279
280#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
281#define S3C2410_GPC10_INP (0x00 << 20)
282#define S3C2410_GPC10_OUTP (0x01 << 20)
283#define S3C2410_GPC10_VD2 (0x02 << 20)
284
285#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
286#define S3C2410_GPC11_INP (0x00 << 22)
287#define S3C2410_GPC11_OUTP (0x01 << 22)
288#define S3C2410_GPC11_VD3 (0x02 << 22)
289
290#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
291#define S3C2410_GPC12_INP (0x00 << 24)
292#define S3C2410_GPC12_OUTP (0x01 << 24)
293#define S3C2410_GPC12_VD4 (0x02 << 24)
294
295#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
296#define S3C2410_GPC13_INP (0x00 << 26)
297#define S3C2410_GPC13_OUTP (0x01 << 26)
298#define S3C2410_GPC13_VD5 (0x02 << 26)
299
300#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
301#define S3C2410_GPC14_INP (0x00 << 28)
302#define S3C2410_GPC14_OUTP (0x01 << 28)
303#define S3C2410_GPC14_VD6 (0x02 << 28)
304
305#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
306#define S3C2410_GPC15_INP (0x00 << 30)
307#define S3C2410_GPC15_OUTP (0x01 << 30)
308#define S3C2410_GPC15_VD7 (0x02 << 30)
309
310/* Port D consists of 16 GPIO/Special function
311 *
312 * almost identical setup to port b, but the special functions are mostly
313 * to do with the video system's data.
314*/
315
316#define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
317#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
318#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
319
320#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
321#define S3C2410_GPD0_INP (0x00 << 0)
322#define S3C2410_GPD0_OUTP (0x01 << 0)
323#define S3C2410_GPD0_VD8 (0x02 << 0)
324
325#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
326#define S3C2410_GPD1_INP (0x00 << 2)
327#define S3C2410_GPD1_OUTP (0x01 << 2)
328#define S3C2410_GPD1_VD9 (0x02 << 2)
329
330#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
331#define S3C2410_GPD2_INP (0x00 << 4)
332#define S3C2410_GPD2_OUTP (0x01 << 4)
333#define S3C2410_GPD2_VD10 (0x02 << 4)
334
335#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
336#define S3C2410_GPD3_INP (0x00 << 6)
337#define S3C2410_GPD3_OUTP (0x01 << 6)
338#define S3C2410_GPD3_VD11 (0x02 << 6)
339
340#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
341#define S3C2410_GPD4_INP (0x00 << 8)
342#define S3C2410_GPD4_OUTP (0x01 << 8)
343#define S3C2410_GPD4_VD12 (0x02 << 8)
344
345#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
346#define S3C2410_GPD5_INP (0x00 << 10)
347#define S3C2410_GPD5_OUTP (0x01 << 10)
348#define S3C2410_GPD5_VD13 (0x02 << 10)
349
350#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
351#define S3C2410_GPD6_INP (0x00 << 12)
352#define S3C2410_GPD6_OUTP (0x01 << 12)
353#define S3C2410_GPD6_VD14 (0x02 << 12)
354
355#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
356#define S3C2410_GPD7_INP (0x00 << 14)
357#define S3C2410_GPD7_OUTP (0x01 << 14)
358#define S3C2410_GPD7_VD15 (0x02 << 14)
359
360#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
361#define S3C2410_GPD8_INP (0x00 << 16)
362#define S3C2410_GPD8_OUTP (0x01 << 16)
363#define S3C2410_GPD8_VD16 (0x02 << 16)
364
365#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
366#define S3C2410_GPD9_INP (0x00 << 18)
367#define S3C2410_GPD9_OUTP (0x01 << 18)
368#define S3C2410_GPD9_VD17 (0x02 << 18)
369
370#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
371#define S3C2410_GPD10_INP (0x00 << 20)
372#define S3C2410_GPD10_OUTP (0x01 << 20)
373#define S3C2410_GPD10_VD18 (0x02 << 20)
374
375#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
376#define S3C2410_GPD11_INP (0x00 << 22)
377#define S3C2410_GPD11_OUTP (0x01 << 22)
378#define S3C2410_GPD11_VD19 (0x02 << 22)
379
380#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
381#define S3C2410_GPD12_INP (0x00 << 24)
382#define S3C2410_GPD12_OUTP (0x01 << 24)
383#define S3C2410_GPD12_VD20 (0x02 << 24)
384
385#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
386#define S3C2410_GPD13_INP (0x00 << 26)
387#define S3C2410_GPD13_OUTP (0x01 << 26)
388#define S3C2410_GPD13_VD21 (0x02 << 26)
389
390#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
391#define S3C2410_GPD14_INP (0x00 << 28)
392#define S3C2410_GPD14_OUTP (0x01 << 28)
393#define S3C2410_GPD14_VD22 (0x02 << 28)
394
395#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
396#define S3C2410_GPD15_INP (0x00 << 30)
397#define S3C2410_GPD15_OUTP (0x01 << 30)
398#define S3C2410_GPD15_VD23 (0x02 << 30)
399
400/* Port E consists of 16 GPIO/Special function
401 *
402 * again, the same as port B, but dealing with I2S, SDI, and
403 * more miscellaneous functions
404*/
405
406#define S3C2410_GPECON S3C2410_GPIOREG(0x40)
407#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
408#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
409
410#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
411#define S3C2410_GPE0_INP (0x00 << 0)
412#define S3C2410_GPE0_OUTP (0x01 << 0)
413#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
414#define S3C2410_GPE0_MASK (0x03 << 0)
415
416#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
417#define S3C2410_GPE1_INP (0x00 << 2)
418#define S3C2410_GPE1_OUTP (0x01 << 2)
419#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
420#define S3C2410_GPE1_MASK (0x03 << 2)
421
422#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
423#define S3C2410_GPE2_INP (0x00 << 4)
424#define S3C2410_GPE2_OUTP (0x01 << 4)
425#define S3C2410_GPE2_CDCLK (0x02 << 4)
426
427#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
428#define S3C2410_GPE3_INP (0x00 << 6)
429#define S3C2410_GPE3_OUTP (0x01 << 6)
430#define S3C2410_GPE3_I2SSDI (0x02 << 6)
431#define S3C2410_GPE3_nSS0 (0x03 << 6)
432#define S3C2410_GPE3_MASK (0x03 << 6)
433
434#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
435#define S3C2410_GPE4_INP (0x00 << 8)
436#define S3C2410_GPE4_OUTP (0x01 << 8)
437#define S3C2410_GPE4_I2SSDO (0x02 << 8)
438#define S3C2410_GPE4_I2SSDI (0x03 << 8)
439#define S3C2410_GPE4_MASK (0x03 << 8)
440
441#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
442#define S3C2410_GPE5_INP (0x00 << 10)
443#define S3C2410_GPE5_OUTP (0x01 << 10)
444#define S3C2410_GPE5_SDCLK (0x02 << 10)
445
446#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
447#define S3C2410_GPE6_INP (0x00 << 12)
448#define S3C2410_GPE6_OUTP (0x01 << 12)
449#define S3C2410_GPE6_SDCMD (0x02 << 12)
450
451#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
452#define S3C2410_GPE7_INP (0x00 << 14)
453#define S3C2410_GPE7_OUTP (0x01 << 14)
454#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
455
456#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
457#define S3C2410_GPE8_INP (0x00 << 16)
458#define S3C2410_GPE8_OUTP (0x01 << 16)
459#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
460
461#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
462#define S3C2410_GPE9_INP (0x00 << 18)
463#define S3C2410_GPE9_OUTP (0x01 << 18)
464#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
465
466#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
467#define S3C2410_GPE10_INP (0x00 << 20)
468#define S3C2410_GPE10_OUTP (0x01 << 20)
469#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
470
471#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
472#define S3C2410_GPE11_INP (0x00 << 22)
473#define S3C2410_GPE11_OUTP (0x01 << 22)
474#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
475
476#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
477#define S3C2410_GPE12_INP (0x00 << 24)
478#define S3C2410_GPE12_OUTP (0x01 << 24)
479#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
480
481#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
482#define S3C2410_GPE13_INP (0x00 << 26)
483#define S3C2410_GPE13_OUTP (0x01 << 26)
484#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
485
486#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
487#define S3C2410_GPE14_INP (0x00 << 28)
488#define S3C2410_GPE14_OUTP (0x01 << 28)
489#define S3C2410_GPE14_IICSCL (0x02 << 28)
490#define S3C2410_GPE14_MASK (0x03 << 28)
491
492#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
493#define S3C2410_GPE15_INP (0x00 << 30)
494#define S3C2410_GPE15_OUTP (0x01 << 30)
495#define S3C2410_GPE15_IICSDA (0x02 << 30)
496#define S3C2410_GPE15_MASK (0x03 << 30)
497
498#define S3C2440_GPE0_ACSYNC (0x03 << 0)
499#define S3C2440_GPE1_ACBITCLK (0x03 << 2)
500#define S3C2440_GPE2_ACRESET (0x03 << 4)
501#define S3C2440_GPE3_ACIN (0x03 << 6)
502#define S3C2440_GPE4_ACOUT (0x03 << 8)
503
504#define S3C2410_GPE_PUPDIS(x) (1<<(x))
505
506/* Port F consists of 8 GPIO/Special function
507 *
508 * GPIO / interrupt inputs
509 *
510 * GPFCON has 2 bits for each of the input pins on port F
511 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
512 *
513 * pull up works like all other ports.
514*/
515
516#define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
517#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
518#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
519
520#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
521#define S3C2410_GPF0_INP (0x00 << 0)
522#define S3C2410_GPF0_OUTP (0x01 << 0)
523#define S3C2410_GPF0_EINT0 (0x02 << 0)
524
525#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
526#define S3C2410_GPF1_INP (0x00 << 2)
527#define S3C2410_GPF1_OUTP (0x01 << 2)
528#define S3C2410_GPF1_EINT1 (0x02 << 2)
529
530#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
531#define S3C2410_GPF2_INP (0x00 << 4)
532#define S3C2410_GPF2_OUTP (0x01 << 4)
533#define S3C2410_GPF2_EINT2 (0x02 << 4)
534
535#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
536#define S3C2410_GPF3_INP (0x00 << 6)
537#define S3C2410_GPF3_OUTP (0x01 << 6)
538#define S3C2410_GPF3_EINT3 (0x02 << 6)
539
540#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
541#define S3C2410_GPF4_INP (0x00 << 8)
542#define S3C2410_GPF4_OUTP (0x01 << 8)
543#define S3C2410_GPF4_EINT4 (0x02 << 8)
544
545#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
546#define S3C2410_GPF5_INP (0x00 << 10)
547#define S3C2410_GPF5_OUTP (0x01 << 10)
548#define S3C2410_GPF5_EINT5 (0x02 << 10)
549
550#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
551#define S3C2410_GPF6_INP (0x00 << 12)
552#define S3C2410_GPF6_OUTP (0x01 << 12)
553#define S3C2410_GPF6_EINT6 (0x02 << 12)
554
555#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
556#define S3C2410_GPF7_INP (0x00 << 14)
557#define S3C2410_GPF7_OUTP (0x01 << 14)
558#define S3C2410_GPF7_EINT7 (0x02 << 14)
559
560/* Port G consists of 8 GPIO/IRQ/Special function
561 *
562 * GPGCON has 2 bits for each of the input pins on port F
563 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
564 *
565 * pull up works like all other ports.
566*/
567
568#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
569#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
570#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
571
572#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
573#define S3C2410_GPG0_INP (0x00 << 0)
574#define S3C2410_GPG0_OUTP (0x01 << 0)
575#define S3C2410_GPG0_EINT8 (0x02 << 0)
576
577#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
578#define S3C2410_GPG1_INP (0x00 << 2)
579#define S3C2410_GPG1_OUTP (0x01 << 2)
580#define S3C2410_GPG1_EINT9 (0x02 << 2)
581
582#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
583#define S3C2410_GPG2_INP (0x00 << 4)
584#define S3C2410_GPG2_OUTP (0x01 << 4)
585#define S3C2410_GPG2_EINT10 (0x02 << 4)
586
587#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
588#define S3C2410_GPG3_INP (0x00 << 6)
589#define S3C2410_GPG3_OUTP (0x01 << 6)
590#define S3C2410_GPG3_EINT11 (0x02 << 6)
591
592#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
593#define S3C2410_GPG4_INP (0x00 << 8)
594#define S3C2410_GPG4_OUTP (0x01 << 8)
595#define S3C2410_GPG4_EINT12 (0x02 << 8)
596#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
597
598#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
599#define S3C2410_GPG5_INP (0x00 << 10)
600#define S3C2410_GPG5_OUTP (0x01 << 10)
601#define S3C2410_GPG5_EINT13 (0x02 << 10)
602#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
603
604#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
605#define S3C2410_GPG6_INP (0x00 << 12)
606#define S3C2410_GPG6_OUTP (0x01 << 12)
607#define S3C2410_GPG6_EINT14 (0x02 << 12)
608#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
609
610#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
611#define S3C2410_GPG7_INP (0x00 << 14)
612#define S3C2410_GPG7_OUTP (0x01 << 14)
613#define S3C2410_GPG7_EINT15 (0x02 << 14)
614#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
615
616#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
617#define S3C2410_GPG8_INP (0x00 << 16)
618#define S3C2410_GPG8_OUTP (0x01 << 16)
619#define S3C2410_GPG8_EINT16 (0x02 << 16)
620
621#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
622#define S3C2410_GPG9_INP (0x00 << 18)
623#define S3C2410_GPG9_OUTP (0x01 << 18)
624#define S3C2410_GPG9_EINT17 (0x02 << 18)
625
626#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
627#define S3C2410_GPG10_INP (0x00 << 20)
628#define S3C2410_GPG10_OUTP (0x01 << 20)
629#define S3C2410_GPG10_EINT18 (0x02 << 20)
630
631#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
632#define S3C2410_GPG11_INP (0x00 << 22)
633#define S3C2410_GPG11_OUTP (0x01 << 22)
634#define S3C2410_GPG11_EINT19 (0x02 << 22)
635#define S3C2410_GPG11_TCLK1 (0x03 << 22)
636
637#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
638#define S3C2410_GPG12_INP (0x00 << 24)
639#define S3C2410_GPG12_OUTP (0x01 << 24)
640#define S3C2410_GPG12_EINT20 (0x02 << 24)
641#define S3C2410_GPG12_XMON (0x03 << 24)
642
643#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
644#define S3C2410_GPG13_INP (0x00 << 26)
645#define S3C2410_GPG13_OUTP (0x01 << 26)
646#define S3C2410_GPG13_EINT21 (0x02 << 26)
647#define S3C2410_GPG13_nXPON (0x03 << 26)
648
649#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
650#define S3C2410_GPG14_INP (0x00 << 28)
651#define S3C2410_GPG14_OUTP (0x01 << 28)
652#define S3C2410_GPG14_EINT22 (0x02 << 28)
653#define S3C2410_GPG14_YMON (0x03 << 28)
654
655#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
656#define S3C2410_GPG15_INP (0x00 << 30)
657#define S3C2410_GPG15_OUTP (0x01 << 30)
658#define S3C2410_GPG15_EINT23 (0x02 << 30)
659#define S3C2410_GPG15_nYPON (0x03 << 30)
660
661
662#define S3C2410_GPG_PUPDIS(x) (1<<(x))
663
664/* Port H consists of11 GPIO/serial/Misc pins
665 *
666 * GPGCON has 2 bits for each of the input pins on port F
667 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
668 *
669 * pull up works like all other ports.
670*/
671
672#define S3C2410_GPHCON S3C2410_GPIOREG(0x70)
673#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
674#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
675
676#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
677#define S3C2410_GPH0_INP (0x00 << 0)
678#define S3C2410_GPH0_OUTP (0x01 << 0)
679#define S3C2410_GPH0_nCTS0 (0x02 << 0)
680
681#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
682#define S3C2410_GPH1_INP (0x00 << 2)
683#define S3C2410_GPH1_OUTP (0x01 << 2)
684#define S3C2410_GPH1_nRTS0 (0x02 << 2)
685
686#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
687#define S3C2410_GPH2_INP (0x00 << 4)
688#define S3C2410_GPH2_OUTP (0x01 << 4)
689#define S3C2410_GPH2_TXD0 (0x02 << 4)
690
691#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
692#define S3C2410_GPH3_INP (0x00 << 6)
693#define S3C2410_GPH3_OUTP (0x01 << 6)
694#define S3C2410_GPH3_RXD0 (0x02 << 6)
695
696#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
697#define S3C2410_GPH4_INP (0x00 << 8)
698#define S3C2410_GPH4_OUTP (0x01 << 8)
699#define S3C2410_GPH4_TXD1 (0x02 << 8)
700
701#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
702#define S3C2410_GPH5_INP (0x00 << 10)
703#define S3C2410_GPH5_OUTP (0x01 << 10)
704#define S3C2410_GPH5_RXD1 (0x02 << 10)
705
706#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
707#define S3C2410_GPH6_INP (0x00 << 12)
708#define S3C2410_GPH6_OUTP (0x01 << 12)
709#define S3C2410_GPH6_TXD2 (0x02 << 12)
710#define S3C2410_GPH6_nRTS1 (0x03 << 12)
711
712#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
713#define S3C2410_GPH7_INP (0x00 << 14)
714#define S3C2410_GPH7_OUTP (0x01 << 14)
715#define S3C2410_GPH7_RXD2 (0x02 << 14)
716#define S3C2410_GPH7_nCTS1 (0x03 << 14)
717
718#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
719#define S3C2410_GPH8_INP (0x00 << 16)
720#define S3C2410_GPH8_OUTP (0x01 << 16)
721#define S3C2410_GPH8_UCLK (0x02 << 16)
722
723#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
724#define S3C2410_GPH9_INP (0x00 << 18)
725#define S3C2410_GPH9_OUTP (0x01 << 18)
726#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
727
728#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
729#define S3C2410_GPH10_INP (0x00 << 20)
730#define S3C2410_GPH10_OUTP (0x01 << 20)
731#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
732
733/* miscellaneous control */
734
735#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
736#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
737
738/* see clock.h for dclk definitions */
739
740/* pullup control on databus */
741#define S3C2410_MISCCR_SPUCR_HEN (0)
742#define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
743#define S3C2410_MISCCR_SPUCR_LEN (0)
744#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
745
746#define S3C2410_MISCCR_USBDEV (0)
747#define S3C2410_MISCCR_USBHOST (1<<3)
748
749#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
750#define S3C2410_MISCCR_CLK0_UPLL (1<<4)
751#define S3C2410_MISCCR_CLK0_FCLK (2<<4)
752#define S3C2410_MISCCR_CLK0_HCLK (3<<4)
753#define S3C2410_MISCCR_CLK0_PCLK (4<<4)
754#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
755
756#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
757#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
758#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
759#define S3C2410_MISCCR_CLK1_HCLK (3<<8)
760#define S3C2410_MISCCR_CLK1_PCLK (4<<8)
761#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
762
763#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
764#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
765
766#define S3C2410_MISCCR_nRSTCON (1<<16)
767
768#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
769#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
770#define S3C2410_MISCCR_nEN_SCLKE (1<<19)
771#define S3C2410_MISCCR_SDSLEEP (7<<17)
772
773/* external interrupt control... */
774/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
775 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
776 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
777 *
778 * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
779 *
780 * Samsung datasheet p9-25
781*/
782
783#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
784#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
785#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
786
787/* values for S3C2410_EXTINT0/1/2 */
788#define S3C2410_EXTINT_LOWLEV (0x00)
789#define S3C2410_EXTINT_HILEV (0x01)
790#define S3C2410_EXTINT_FALLEDGE (0x02)
791#define S3C2410_EXTINT_RISEEDGE (0x04)
792#define S3C2410_EXTINT_BOTHEDGE (0x06)
793
794/* interrupt filtering conrrol for EINT16..EINT23 */
795#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
796#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
797#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
798#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
799
800/* values for interrupt filtering */
801#define S3C2410_EINTFLT_PCLK (0x00)
802#define S3C2410_EINTFLT_EXTCLK (1<<7)
803#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)
804
805/* removed EINTxxxx defs from here, not meant for this */
806
807/* GSTATUS have miscellaneous information in them
808 *
809 */
810
811#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
812#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
813#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
814#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
815#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
816
817#define S3C2410_GSTATUS0_nWAIT (1<<3)
818#define S3C2410_GSTATUS0_NCON (1<<2)
819#define S3C2410_GSTATUS0_RnB (1<<1)
820#define S3C2410_GSTATUS0_nBATTFLT (1<<0)
821
822#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
823#define S3C2410_GSTATUS1_2410 (0x32410000)
824#define S3C2410_GSTATUS1_2440 (0x32440000)
825
826#define S3C2410_GSTATUS2_WTRESET (1<<2)
827#define S3C2410_GSTATUS2_OFFRESET (1<<1)
828#define S3C2410_GSTATUS2_PONRESET (1<<0)
829
830#endif /* __ASM_ARCH_REGS_GPIO_H */
831
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
new file mode 100644
index 000000000000..3ad2324acc39
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h
@@ -0,0 +1,101 @@
1/* linux/include/asm/hardware/s3c2410/regs-gpioj.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440 GPIO J register definitions
11 *
12 * Changelog:
13 * 11-Aug-2004 BJD Created file
14 * 10-Feb-2005 BJD Fix GPJ12 definition (Guillaume Gourat)
15*/
16
17
18#ifndef __ASM_ARCH_REGS_GPIOJ_H
19#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
20
21/* Port J consists of 13 GPIO/Camera pins
22 *
23 * GPJCON has 2 bits for each of the input pins on port F
24 * 00 = 0 input, 1 output, 2 Camera
25 *
26 * pull up works like all other ports.
27*/
28
29#define S3C2440_GPIO_BANKJ (416)
30
31#define S3C2440_GPJCON S3C2410_GPIOREG(0xd0)
32#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
33#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
34
35#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
36#define S3C2440_GPJ0_INP (0x00 << 0)
37#define S3C2440_GPJ0_OUTP (0x01 << 0)
38#define S3C2440_GPJ0_CAMDATA0 (0x02 << 0)
39
40#define S3C2440_GPJ1 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1)
41#define S3C2440_GPJ1_INP (0x00 << 2)
42#define S3C2440_GPJ1_OUTP (0x01 << 2)
43#define S3C2440_GPJ1_CAMDATA1 (0x02 << 2)
44
45#define S3C2440_GPJ2 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2)
46#define S3C2440_GPJ2_INP (0x00 << 4)
47#define S3C2440_GPJ2_OUTP (0x01 << 4)
48#define S3C2440_GPJ2_CAMDATA2 (0x02 << 4)
49
50#define S3C2440_GPJ3 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3)
51#define S3C2440_GPJ3_INP (0x00 << 6)
52#define S3C2440_GPJ3_OUTP (0x01 << 6)
53#define S3C2440_GPJ3_CAMDATA3 (0x02 << 6)
54
55#define S3C2440_GPJ4 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4)
56#define S3C2440_GPJ4_INP (0x00 << 8)
57#define S3C2440_GPJ4_OUTP (0x01 << 8)
58#define S3C2440_GPJ4_CAMDATA4 (0x02 << 8)
59
60#define S3C2440_GPJ5 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5)
61#define S3C2440_GPJ5_INP (0x00 << 10)
62#define S3C2440_GPJ5_OUTP (0x01 << 10)
63#define S3C2440_GPJ5_CAMDATA5 (0x02 << 10)
64
65#define S3C2440_GPJ6 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6)
66#define S3C2440_GPJ6_INP (0x00 << 12)
67#define S3C2440_GPJ6_OUTP (0x01 << 12)
68#define S3C2440_GPJ6_CAMDATA6 (0x02 << 12)
69
70#define S3C2440_GPJ7 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7)
71#define S3C2440_GPJ7_INP (0x00 << 14)
72#define S3C2440_GPJ7_OUTP (0x01 << 14)
73#define S3C2440_GPJ7_CAMDATA7 (0x02 << 14)
74
75#define S3C2440_GPJ8 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8)
76#define S3C2440_GPJ8_INP (0x00 << 16)
77#define S3C2440_GPJ8_OUTP (0x01 << 16)
78#define S3C2440_GPJ8_CAMPCLK (0x02 << 16)
79
80#define S3C2440_GPJ9 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9)
81#define S3C2440_GPJ9_INP (0x00 << 18)
82#define S3C2440_GPJ9_OUTP (0x01 << 18)
83#define S3C2440_GPJ9_CAMVSYNC (0x02 << 18)
84
85#define S3C2440_GPJ10 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10)
86#define S3C2440_GPJ10_INP (0x00 << 20)
87#define S3C2440_GPJ10_OUTP (0x01 << 20)
88#define S3C2440_GPJ10_CAMHREF (0x02 << 20)
89
90#define S3C2440_GPJ11 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11)
91#define S3C2440_GPJ11_INP (0x00 << 22)
92#define S3C2440_GPJ11_OUTP (0x01 << 22)
93#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
94
95#define S3C2440_GPJ12 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12)
96#define S3C2440_GPJ12_INP (0x00 << 24)
97#define S3C2440_GPJ12_OUTP (0x01 << 24)
98#define S3C2440_GPJ12_CAMRESET (0x02 << 24)
99
100#endif /* __ASM_ARCH_REGS_GPIOJ_H */
101
diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/arch-s3c2410/regs-iic.h
new file mode 100644
index 000000000000..fed3288e2046
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-iic.h
@@ -0,0 +1,60 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-iic.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 I2C Controller
11 *
12 * Changelog:
13 * 03-Oct-2004 BJD Initial include for Linux
14 * 08-Nov-2004 BJD Added S3C2440 filter register
15*/
16
17#ifndef __ASM_ARCH_REGS_IIC_H
18#define __ASM_ARCH_REGS_IIC_H __FILE__
19
20/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
21
22#define S3C2410_IICREG(x) (x)
23
24#define S3C2410_IICCON S3C2410_IICREG(0x00)
25#define S3C2410_IICSTAT S3C2410_IICREG(0x04)
26#define S3C2410_IICADD S3C2410_IICREG(0x08)
27#define S3C2410_IICDS S3C2410_IICREG(0x0C)
28#define S3C2440_IICLC S3C2410_IICREG(0x10)
29
30#define S3C2410_IICCON_ACKEN (1<<7)
31#define S3C2410_IICCON_TXDIV_16 (0<<6)
32#define S3C2410_IICCON_TXDIV_512 (1<<6)
33#define S3C2410_IICCON_IRQEN (1<<5)
34#define S3C2410_IICCON_IRQPEND (1<<4)
35#define S3C2410_IICCON_SCALE(x) ((x)&15)
36#define S3C2410_IICCON_SCALEMASK (0xf)
37
38#define S3C2410_IICSTAT_MASTER_RX (2<<6)
39#define S3C2410_IICSTAT_MASTER_TX (3<<6)
40#define S3C2410_IICSTAT_SLAVE_RX (0<<6)
41#define S3C2410_IICSTAT_SLAVE_TX (1<<6)
42#define S3C2410_IICSTAT_MODEMASK (3<<6)
43
44#define S3C2410_IICSTAT_START (1<<5)
45#define S3C2410_IICSTAT_BUSBUSY (1<<5)
46#define S3C2410_IICSTAT_TXRXEN (1<<4)
47#define S3C2410_IICSTAT_ARBITR (1<<3)
48#define S3C2410_IICSTAT_ASSLAVE (1<<2)
49#define S3C2410_IICSTAT_ADDR0 (1<<1)
50#define S3C2410_IICSTAT_LASTBIT (1<<0)
51
52#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
53#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
54#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
55#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
56#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
57
58#define S3C2410_IICLC_FILTER_ON (1<<2)
59
60#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
new file mode 100644
index 000000000000..7ae8e1f45bc1
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -0,0 +1,72 @@
1/* linux/include/asm/arch-s3c2410/regs-iis.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 IIS register definition
11 *
12 * Changelog:
13 * 19-06-2003 BJD Created file
14 * 26-06-2003 BJD Finished off definitions for register addresses
15 * 12-03-2004 BJD Updated include protection
16 * 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL
17 */
18
19#ifndef __ASM_ARCH_REGS_IIS_H
20#define __ASM_ARCH_REGS_IIS_H
21
22#define S3C2410_IISCON (0x00)
23
24#define S3C2440_IISCON_MPLL (1<<9)
25#define S3C2410_IISCON_LRINDEX (1<<8)
26#define S3C2410_IISCON_TXFIFORDY (1<<7)
27#define S3C2410_IISCON_RXFIFORDY (1<<6)
28#define S3C2410_IISCON_TXDMAEN (1<<5)
29#define S3C2410_IISCON_RXDMAEN (1<<4)
30#define S3C2410_IISCON_TXIDLE (1<<3)
31#define S3C2410_IISCON_RXIDLE (1<<2)
32#define S3C2410_IISCON_IISEN (1<<0)
33
34#define S3C2410_IISMOD (0x04)
35
36#define S3C2410_IISMOD_SLAVE (1<<8)
37#define S3C2410_IISMOD_NOXFER (0<<6)
38#define S3C2410_IISMOD_RXMODE (1<<6)
39#define S3C2410_IISMOD_TXMODE (2<<6)
40#define S3C2410_IISMOD_TXRXMODE (3<<6)
41#define S3C2410_IISMOD_LR_LLOW (0<<5)
42#define S3C2410_IISMOD_LR_RLOW (1<<5)
43#define S3C2410_IISMOD_IIS (0<<4)
44#define S3C2410_IISMOD_MSB (1<<4)
45#define S3C2410_IISMOD_8BIT (0<<3)
46#define S3C2410_IISMOD_16BIT (1<<3)
47#define S3C2410_IISMOD_BITMASK (1<<3)
48#define S3C2410_IISMOD_256FS (0<<1)
49#define S3C2410_IISMOD_384FS (1<<1)
50#define S3C2410_IISMOD_16FS (0<<0)
51#define S3C2410_IISMOD_32FS (1<<0)
52#define S3C2410_IISMOD_48FS (2<<0)
53
54#define S3C2410_IISPSR (0x08)
55#define S3C2410_IISPSR_INTMASK (31<<5)
56#define S3C2410_IISPSR_INTSHIFT (5)
57#define S3C2410_IISPSR_EXTMASK (31<<0)
58#define S3C2410_IISPSR_EXTSHFIT (0)
59
60#define S3C2410_IISFCON (0x0c)
61
62#define S3C2410_IISFCON_TXDMA (1<<15)
63#define S3C2410_IISFCON_RXDMA (1<<14)
64#define S3C2410_IISFCON_TXENABLE (1<<13)
65#define S3C2410_IISFCON_RXENABLE (1<<12)
66#define S3C2410_IISFCON_TXMASK (0x3f << 6)
67#define S3C2410_IISFCON_TXSHIFT (6)
68#define S3C2410_IISFCON_RXMASK (0x3f)
69#define S3C2410_IISFCON_RXSHIFT (0)
70
71#define S3C2410_IISFIFO (0x10)
72#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-irq.h b/include/asm-arm/arch-s3c2410/regs-irq.h
new file mode 100644
index 000000000000..24b7292df79e
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-irq.h
@@ -0,0 +1,44 @@
1/* linux/include/asm/arch-s3c2410/regs-irq.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *
11 *
12 * Changelog:
13 * 19-06-2003 BJD Created file
14 * 12-03-2004 BJD Updated include protection
15 * 10-03-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
16 */
17
18
19#ifndef ___ASM_ARCH_REGS_IRQ_H
20#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
21
22/* interrupt controller */
23
24#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
25#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
26
27#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
28#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
29#define S3C2410_INTMSK S3C2410_IRQREG(0x008)
30#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C)
31#define S3C2410_INTPND S3C2410_IRQREG(0x010)
32#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014)
33#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
34#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
35
36/* mask: 0=enable, 1=disable
37 * 1 bit EINT, 4=EINT4, 23=EINT23
38 * EINT0,1,2,3 are not handled here.
39*/
40
41#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
42#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
43
44#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
new file mode 100644
index 000000000000..7f882ea92b2a
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -0,0 +1,114 @@
1/* linux/include/asm/arch-s3c2410/regs-lcd.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *
11 *
12 * Changelog:
13 * 12-06-2003 BJD Created file
14 * 26-06-2003 BJD Updated LCDCON register definitions
15 * 12-03-2004 BJD Updated include protection
16 * 10-03-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
17*/
18
19
20#ifndef ___ASM_ARCH_REGS_LCD_H
21#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
22
23#define S3C2410_LCDREG(x) ((x) + S3C24XX_VA_LCD)
24
25/* LCD control registers */
26#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
27#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04)
28#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08)
29#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C)
30#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10)
31
32#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
33#define S3C2410_LCDCON1_MMODE (1<<7)
34#define S3C2410_LCDCON1_DSCAN4 (0<<5)
35#define S3C2410_LCDCON1_STN4 (1<<5)
36#define S3C2410_LCDCON1_STN8 (2<<5)
37#define S3C2410_LCDCON1_TFT (3<<5)
38
39#define S3C2410_LCDCON1_STN1BPP (0<<1)
40#define S3C2410_LCDCON1_STN2GREY (1<<1)
41#define S3C2410_LCDCON1_STN4GREY (2<<1)
42#define S3C2410_LCDCON1_STN8BPP (3<<1)
43#define S3C2410_LCDCON1_STN12BPP (4<<1)
44
45#define S3C2410_LCDCON1_TFT1BPP (8<<1)
46#define S3C2410_LCDCON1_TFT2BPP (9<<1)
47#define S3C2410_LCDCON1_TFT4BPP (10<<1)
48#define S3C2410_LCDCON1_TFT8BPP (11<<1)
49#define S3C2410_LCDCON1_TFT16BPP (12<<1)
50#define S3C2410_LCDCON1_TFT24BPP (13<<1)
51
52#define S3C2410_LCDCON1_ENVID (1)
53
54#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
55#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
56#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
57#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
58
59#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
60#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
61#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
62#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
63#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
64
65#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
66#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
67#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
68
69#define S3C2410_LCDCON5_BPP24BL (1<<12)
70#define S3C2410_LCDCON5_FRM565 (1<<11)
71#define S3C2410_LCDCON5_INVVCLK (1<<10)
72#define S3C2410_LCDCON5_INVVLINE (1<<9)
73#define S3C2410_LCDCON5_INVVFRAME (1<<8)
74#define S3C2410_LCDCON5_INVVD (1<<7)
75#define S3C2410_LCDCON5_INVVDEN (1<<6)
76#define S3C2410_LCDCON5_INVPWREN (1<<5)
77#define S3C2410_LCDCON5_INVLEND (1<<4)
78#define S3C2410_LCDCON5_PWREN (1<<3)
79#define S3C2410_LCDCON5_ENLEND (1<<2)
80#define S3C2410_LCDCON5_BSWP (1<<1)
81#define S3C2410_LCDCON5_HWSWP (1<<0)
82
83/* framebuffer start addressed */
84#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14)
85#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18)
86#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C)
87
88#define S3C2410_LCDBANK(x) ((x) << 21)
89#define S3C2410_LCDBASEU(x) (x)
90
91#define S3C2410_OFFSIZE(x) ((x) << 11)
92#define S3C2410_PAGEWIDTH(x) (x)
93
94/* colour lookup and miscellaneous controls */
95
96#define S3C2410_REDLUT S3C2410_LCDREG(0x20)
97#define S3C2410_GREENLUT S3C2410_LCDREG(0x24)
98#define S3C2410_BLUELUT S3C2410_LCDREG(0x28)
99
100#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
101#define S3C2410_TPAL S3C2410_LCDREG(0x50)
102
103/* interrupt info */
104#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
105#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
106#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
107#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
108
109#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
110
111#endif /* ___ASM_ARCH_REGS_LCD_H */
112
113
114
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
new file mode 100644
index 000000000000..1a1328ac0d79
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -0,0 +1,212 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-mem.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Memory Control register definitions
11 *
12 * Changelog:
13 * 29-Sep-2004 BJD Initial include for Linux
14 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
15 *
16*/
17
18#ifndef __ASM_ARM_MEMREGS_H
19#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
20
21#ifndef S3C2410_MEMREG
22#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
23#endif
24
25/* bus width, and wait state control */
26#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
27
28/* bank zero config - note, pinstrapped from OM pins! */
29#define S3C2410_BWSCON_DW0_16 (1<<1)
30#define S3C2410_BWSCON_DW0_32 (2<<1)
31
32/* bank one configs */
33#define S3C2410_BWSCON_DW1_8 (0<<4)
34#define S3C2410_BWSCON_DW1_16 (1<<4)
35#define S3C2410_BWSCON_DW1_32 (2<<4)
36#define S3C2410_BWSCON_WS1 (1<<6)
37#define S3C2410_BWSCON_ST1 (1<<7)
38
39/* bank 2 configurations */
40#define S3C2410_BWSCON_DW2_8 (0<<8)
41#define S3C2410_BWSCON_DW2_16 (1<<8)
42#define S3C2410_BWSCON_DW2_32 (2<<8)
43#define S3C2410_BWSCON_WS2 (1<<10)
44#define S3C2410_BWSCON_ST2 (1<<11)
45
46/* bank 3 configurations */
47#define S3C2410_BWSCON_DW3_8 (0<<12)
48#define S3C2410_BWSCON_DW3_16 (1<<12)
49#define S3C2410_BWSCON_DW3_32 (2<<12)
50#define S3C2410_BWSCON_WS3 (1<<14)
51#define S3C2410_BWSCON_ST3 (1<<15)
52
53/* bank 4 configurations */
54#define S3C2410_BWSCON_DW4_8 (0<<16)
55#define S3C2410_BWSCON_DW4_16 (1<<16)
56#define S3C2410_BWSCON_DW4_32 (2<<16)
57#define S3C2410_BWSCON_WS4 (1<<18)
58#define S3C2410_BWSCON_ST4 (1<<19)
59
60/* bank 5 configurations */
61#define S3C2410_BWSCON_DW5_8 (0<<20)
62#define S3C2410_BWSCON_DW5_16 (1<<20)
63#define S3C2410_BWSCON_DW5_32 (2<<20)
64#define S3C2410_BWSCON_WS5 (1<<22)
65#define S3C2410_BWSCON_ST5 (1<<23)
66
67/* bank 6 configurations */
68#define S3C2410_BWSCON_DW6_8 (0<<24)
69#define S3C2410_BWSCON_DW6_16 (1<<24)
70#define S3C2410_BWSCON_DW6_32 (2<<24)
71#define S3C2410_BWSCON_WS6 (1<<26)
72#define S3C2410_BWSCON_ST6 (1<<27)
73
74/* bank 7 configurations */
75#define S3C2410_BWSCON_DW7_8 (0<<28)
76#define S3C2410_BWSCON_DW7_16 (1<<28)
77#define S3C2410_BWSCON_DW7_32 (2<<28)
78#define S3C2410_BWSCON_WS7 (1<<30)
79#define S3C2410_BWSCON_ST7 (1<<31)
80
81/* memory set (rom, ram) */
82#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
83#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
84#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
85#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
86#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
87#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
88#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
89#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
90
91/* bank configuration registers */
92
93#define S3C2410_BANKCON_PMCnorm (0x00)
94#define S3C2410_BANKCON_PMC4 (0x01)
95#define S3C2410_BANKCON_PMC8 (0x02)
96#define S3C2410_BANKCON_PMC16 (0x03)
97
98/* bank configurations for banks 0..7, note banks
99 * 6 and 7 have differnt configurations depending on
100 * the memory type bits */
101
102#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
103#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
104#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
105#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
106
107#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
108#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
109#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
110#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
111
112#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
113#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
114#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
115#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
116
117#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
118#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
119#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
120#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
121#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
122#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
123#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
124#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
125
126#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
127#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
128#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
129#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
130
131#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
132#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
133#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
134#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
135
136#define S3C2410_BANKCON_SRAM (0x0 << 15)
137#define S3C2400_BANKCON_EDODRAM (0x2 << 15)
138#define S3C2410_BANKCON_SDRAM (0x3 << 15)
139
140/* next bits only for EDO DRAM in 6,7 */
141#define S3C2400_BANKCON_EDO_Trdc1 (0x00 << 4)
142#define S3C2400_BANKCON_EDO_Trdc2 (0x01 << 4)
143#define S3C2400_BANKCON_EDO_Trdc3 (0x02 << 4)
144#define S3C2400_BANKCON_EDO_Trdc4 (0x03 << 4)
145
146/* CAS pulse width */
147#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3)
148#define S3C2400_BANKCON_EDO_PULSE2 (0x01 << 3)
149
150/* CAS pre-charge */
151#define S3C2400_BANKCON_EDO_TCP1 (0x00 << 2)
152#define S3C2400_BANKCON_EDO_TCP2 (0x01 << 2)
153
154/* control column address select */
155#define S3C2400_BANKCON_EDO_SCANb8 (0x00 << 0)
156#define S3C2400_BANKCON_EDO_SCANb9 (0x01 << 0)
157#define S3C2400_BANKCON_EDO_SCANb10 (0x02 << 0)
158#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0)
159
160/* next bits only for SDRAM in 6,7 */
161#define S3C2410_BANKCON_Trdc2 (0x00 << 2)
162#define S3C2410_BANKCON_Trdc3 (0x01 << 2)
163#define S3C2410_BANKCON_Trdc4 (0x02 << 2)
164
165/* control column address select */
166#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
167#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
168#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
169
170#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
171#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
172#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
173#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
174
175/* refresh control */
176
177#define S3C2410_REFRESH_REFEN (1<<23)
178#define S3C2410_REFRESH_SELF (1<<22)
179#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
180
181#define S3C2410_REFRESH_TRP_MASK (3<<20)
182#define S3C2410_REFRESH_TRP_2clk (0<<20)
183#define S3C2410_REFRESH_TRP_3clk (1<<20)
184#define S3C2410_REFRESH_TRP_4clk (2<<20)
185
186#define S3C2410_REFRESH_TSRC_MASK (3<<18)
187#define S3C2410_REFRESH_TSRC_4clk (0<<18)
188#define S3C2410_REFRESH_TSRC_5clk (1<<18)
189#define S3C2410_REFRESH_TSRC_6clk (2<<18)
190#define S3C2410_REFRESH_TSRC_7clk (3<<18)
191
192
193/* mode select register(s) */
194
195#define S3C2410_MRSRB_CL1 (0x00 << 4)
196#define S3C2410_MRSRB_CL2 (0x02 << 4)
197#define S3C2410_MRSRB_CL3 (0x03 << 4)
198
199/* bank size register */
200#define S3C2410_BANKSIZE_128M (0x2 << 0)
201#define S3C2410_BANKSIZE_64M (0x1 << 0)
202#define S3C2410_BANKSIZE_32M (0x0 << 0)
203#define S3C2410_BANKSIZE_16M (0x7 << 0)
204#define S3C2410_BANKSIZE_8M (0x6 << 0)
205#define S3C2410_BANKSIZE_4M (0x5 << 0)
206#define S3C2410_BANKSIZE_2M (0x4 << 0)
207#define S3C2410_BANKSIZE_MASK (0x7 << 0)
208#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
209#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
210#define S3C2410_BANKSIZE_BURST (1<<7)
211
212#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/arch-s3c2410/regs-nand.h
new file mode 100644
index 000000000000..c443ac834698
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-nand.h
@@ -0,0 +1,43 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 clock register definitions
11 *
12 * Changelog:
13 * 18-Aug-2004 BJD Copied file from 2.4 and updated
14*/
15
16#ifndef __ASM_ARM_REGS_NAND
17#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
18
19
20#define S3C2410_NFREG(x) (x)
21
22#define S3C2410_NFCONF S3C2410_NFREG(0x00)
23#define S3C2410_NFCMD S3C2410_NFREG(0x04)
24#define S3C2410_NFADDR S3C2410_NFREG(0x08)
25#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
26#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
27#define S3C2410_NFECC S3C2410_NFREG(0x14)
28
29#define S3C2410_NFCONF_EN (1<<15)
30#define S3C2410_NFCONF_512BYTE (1<<14)
31#define S3C2410_NFCONF_4STEP (1<<13)
32#define S3C2410_NFCONF_INITECC (1<<12)
33#define S3C2410_NFCONF_nFCE (1<<11)
34#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
35#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
36#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
37
38#define S3C2410_NFSTAT_BUSY (1<<0)
39
40/* think ECC can only be 8bit read? */
41
42#endif /* __ASM_ARM_REGS_NAND */
43
diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/arch-s3c2410/regs-rtc.h
new file mode 100644
index 000000000000..228983f89bc8
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-rtc.h
@@ -0,0 +1,66 @@
1/* linux/include/asm/arch-s3c2410/regs-rtc.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Internal RTC register definition
11 *
12 * Changelog:
13 * 19-06-2003 BJD Created file
14 * 12-03-2004 BJD Updated include protection
15 * 15-01-2005 LCVR Changed S3C2410_VA to S3C24XX_VA (s3c2400 support)
16*/
17
18#ifndef __ASM_ARCH_REGS_RTC_H
19#define __ASM_ARCH_REGS_RTC_H __FILE__
20
21#define S3C2410_RTCREG(x) ((x) + S3C24XX_VA_RTC)
22
23#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
24#define S3C2410_RTCCON_RTCEN (1<<0)
25#define S3C2410_RTCCON_CLKSEL (1<<1)
26#define S3C2410_RTCCON_CNTSEL (1<<2)
27#define S3C2410_RTCCON_CLKRST (1<<3)
28
29#define S3C2410_TICNT S3C2410_RTCREG(0x44)
30#define S3C2410_TICNT_ENABLE (1<<7)
31
32#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
33#define S3C2410_RTCALM_ALMEN (1<<6)
34#define S3C2410_RTCALM_YEAREN (1<<5)
35#define S3C2410_RTCALM_MONEN (1<<4)
36#define S3C2410_RTCALM_DAYEN (1<<3)
37#define S3C2410_RTCALM_HOUREN (1<<2)
38#define S3C2410_RTCALM_MINEN (1<<1)
39#define S3C2410_RTCALM_SECEN (1<<0)
40
41#define S3C2410_RTCALM_ALL \
42 S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
43 S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
44 S3C2410_RTCALM_SECEN
45
46
47#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
48#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
49#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
50
51#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
52#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
53#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
54
55#define S3C2410_RTCRST S3C2410_RTCREG(0x6c)
56
57#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
58#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
59#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
60#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
61#define S3C2410_RTCDAY S3C2410_RTCREG(0x80)
62#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
63#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
64
65
66#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-sdi.h b/include/asm-arm/arch-s3c2410/regs-sdi.h
new file mode 100644
index 000000000000..ca9a26fbecec
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-sdi.h
@@ -0,0 +1,118 @@
1/* linux/include/asm/arch-s3c2410/regs-sdi.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 MMC/SDIO register definitions
11 *
12 * Changelog:
13 * 18-Aug-2004 Ben Dooks Created initial file
14 * 29-Nov-2004 Koen Martens Added some missing defines, fixed duplicates
15 * 29-Nov-2004 Ben Dooks Updated Koen's patch
16*/
17
18#ifndef __ASM_ARM_REGS_SDI
19#define __ASM_ARM_REGS_SDI "regs-sdi.h"
20
21#define S3C2410_SDICON (0x00)
22#define S3C2410_SDIPRE (0x04)
23#define S3C2410_SDICMDARG (0x08)
24#define S3C2410_SDICMDCON (0x0C)
25#define S3C2410_SDICMDSTAT (0x10)
26#define S3C2410_SDIRSP0 (0x14)
27#define S3C2410_SDIRSP1 (0x18)
28#define S3C2410_SDIRSP2 (0x1C)
29#define S3C2410_SDIRSP3 (0x20)
30#define S3C2410_SDITIMER (0x24)
31#define S3C2410_SDIBSIZE (0x28)
32#define S3C2410_SDIDCON (0x2C)
33#define S3C2410_SDIDCNT (0x30)
34#define S3C2410_SDIDSTA (0x34)
35#define S3C2410_SDIFSTA (0x38)
36#define S3C2410_SDIDATA (0x3C)
37#define S3C2410_SDIIMSK (0x40)
38
39#define S3C2410_SDICON_BYTEORDER (1<<4)
40#define S3C2410_SDICON_SDIOIRQ (1<<3)
41#define S3C2410_SDICON_RWAITEN (1<<2)
42#define S3C2410_SDICON_FIFORESET (1<<1)
43#define S3C2410_SDICON_CLOCKTYPE (1<<0)
44
45#define S3C2410_SDICMDCON_ABORT (1<<12)
46#define S3C2410_SDICMDCON_WITHDATA (1<<11)
47#define S3C2410_SDICMDCON_LONGRSP (1<<10)
48#define S3C2410_SDICMDCON_WAITRSP (1<<9)
49#define S3C2410_SDICMDCON_CMDSTART (1<<8)
50#define S3C2410_SDICMDCON_INDEX (0xff)
51
52#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12)
53#define S3C2410_SDICMDSTAT_CMDSENT (1<<11)
54#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
55#define S3C2410_SDICMDSTAT_RSPFIN (1<<9)
56#define S3C2410_SDICMDSTAT_XFERING (1<<8)
57#define S3C2410_SDICMDSTAT_INDEX (0xff)
58
59#define S3C2410_SDIDCON_IRQPERIOD (1<<21)
60#define S3C2410_SDIDCON_TXAFTERRESP (1<<20)
61#define S3C2410_SDIDCON_RXAFTERCMD (1<<19)
62#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18)
63#define S3C2410_SDIDCON_BLOCKMODE (1<<17)
64#define S3C2410_SDIDCON_WIDEBUS (1<<16)
65#define S3C2410_SDIDCON_DMAEN (1<<15)
66#define S3C2410_SDIDCON_STOP (1<<14)
67#define S3C2410_SDIDCON_DATMODE (3<<12)
68#define S3C2410_SDIDCON_BLKNUM (0x7ff)
69
70/* constants for S3C2410_SDIDCON_DATMODE */
71#define S3C2410_SDIDCON_XFER_READY (0<<12)
72#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
73#define S3C2410_SDIDCON_XFER_RXSTART (2<<12)
74#define S3C2410_SDIDCON_XFER_TXSTART (3<<12)
75
76#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12)
77
78#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10)
79#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
80#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */
81#define S3C2410_SDIDSTA_CRCFAIL (1<<7)
82#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6)
83#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5)
84#define S3C2410_SDIDSTA_XFERFINISH (1<<4)
85#define S3C2410_SDIDSTA_BUSYFINISH (1<<3)
86#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */
87#define S3C2410_SDIDSTA_TXDATAON (1<<1)
88#define S3C2410_SDIDSTA_RXDATAON (1<<0)
89
90#define S3C2410_SDIFSTA_TFDET (1<<13)
91#define S3C2410_SDIFSTA_RFDET (1<<12)
92#define S3C2410_SDIFSTA_TXHALF (1<<11)
93#define S3C2410_SDIFSTA_TXEMPTY (1<<10)
94#define S3C2410_SDIFSTA_RFLAST (1<<9)
95#define S3C2410_SDIFSTA_RFFULL (1<<8)
96#define S3C2410_SDIFSTA_RFHALF (1<<7)
97#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
98
99#define S3C2410_SDIIMSK_RESPONSECRC (1<<17)
100#define S3C2410_SDIIMSK_CMDSENT (1<<16)
101#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15)
102#define S3C2410_SDIIMSK_RESPONSEND (1<<14)
103#define S3C2410_SDIIMSK_READWAIT (1<<13)
104#define S3C2410_SDIIMSK_SDIOIRQ (1<<12)
105#define S3C2410_SDIIMSK_FIFOFAIL (1<<11)
106#define S3C2410_SDIIMSK_CRCSTATUS (1<<10)
107#define S3C2410_SDIIMSK_DATACRC (1<<9)
108#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8)
109#define S3C2410_SDIIMSK_DATAFINISH (1<<7)
110#define S3C2410_SDIIMSK_BUSYFINISH (1<<6)
111#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */
112#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4)
113#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3)
114#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2)
115#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1)
116#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0)
117
118#endif /* __ASM_ARM_REGS_SDI */
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
new file mode 100644
index 000000000000..ce1bbbaad6d3
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-serial.h
@@ -0,0 +1,209 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-serial.h
2 *
3 * From linux/include/asm-arm/hardware/serial_s3c2410.h
4 *
5 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
6 *
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 *
9 * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
10 *
11 * Adapted from:
12 *
13 * Internal header file for MX1ADS serial ports (UART1 & 2)
14 *
15 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 *
31 * Modifications:
32 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA (s3c2400 support)
33 */
34
35#ifndef __ASM_ARM_REGS_SERIAL_H
36#define __ASM_ARM_REGS_SERIAL_H
37
38#define S3C24XX_VA_UART0 (S3C24XX_VA_UART)
39#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 )
40#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 )
41
42#define S3C2410_PA_UART0 (S3C2410_PA_UART)
43#define S3C2410_PA_UART1 (S3C2410_PA_UART + 0x4000 )
44#define S3C2410_PA_UART2 (S3C2410_PA_UART + 0x8000 )
45
46#define S3C2410_URXH (0x24)
47#define S3C2410_UTXH (0x20)
48#define S3C2410_ULCON (0x00)
49#define S3C2410_UCON (0x04)
50#define S3C2410_UFCON (0x08)
51#define S3C2410_UMCON (0x0C)
52#define S3C2410_UBRDIV (0x28)
53#define S3C2410_UTRSTAT (0x10)
54#define S3C2410_UERSTAT (0x14)
55#define S3C2410_UFSTAT (0x18)
56#define S3C2410_UMSTAT (0x1C)
57
58#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
59
60#define S3C2410_LCON_CS5 (0x0)
61#define S3C2410_LCON_CS6 (0x1)
62#define S3C2410_LCON_CS7 (0x2)
63#define S3C2410_LCON_CS8 (0x3)
64#define S3C2410_LCON_CSMASK (0x3)
65
66#define S3C2410_LCON_PNONE (0x0)
67#define S3C2410_LCON_PEVEN (0x5 << 3)
68#define S3C2410_LCON_PODD (0x4 << 3)
69#define S3C2410_LCON_PMASK (0x7 << 3)
70
71#define S3C2410_LCON_STOPB (1<<2)
72#define S3C2410_LCON_IRM (1<<6)
73
74#define S3C2440_UCON_CLKMASK (3<<10)
75#define S3C2440_UCON_PCLK (0<<10)
76#define S3C2440_UCON_UCLK (1<<10)
77#define S3C2440_UCON_PCLK2 (2<<10)
78#define S3C2440_UCON_FCLK (3<<10)
79#define S3C2440_UCON2_FCLK_EN (1<<15)
80#define S3C2440_UCON0_DIVMASK (15 << 12)
81#define S3C2440_UCON1_DIVMASK (15 << 12)
82#define S3C2440_UCON2_DIVMASK (7 << 12)
83#define S3C2440_UCON_DIVSHIFT (12)
84
85#define S3C2410_UCON_UCLK (1<<10)
86#define S3C2410_UCON_SBREAK (1<<4)
87
88#define S3C2410_UCON_TXILEVEL (1<<9)
89#define S3C2410_UCON_RXILEVEL (1<<8)
90#define S3C2410_UCON_TXIRQMODE (1<<2)
91#define S3C2410_UCON_RXIRQMODE (1<<0)
92#define S3C2410_UCON_RXFIFO_TOI (1<<7)
93
94#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
95 S3C2410_UCON_RXILEVEL | \
96 S3C2410_UCON_TXIRQMODE | \
97 S3C2410_UCON_RXIRQMODE | \
98 S3C2410_UCON_RXFIFO_TOI)
99
100#define S3C2410_UFCON_FIFOMODE (1<<0)
101#define S3C2410_UFCON_TXTRIG0 (0<<6)
102#define S3C2410_UFCON_RXTRIG8 (1<<4)
103#define S3C2410_UFCON_RXTRIG12 (2<<4)
104
105/* S3C2440 FIFO trigger levels */
106#define S3C2440_UFCON_RXTRIG1 (0<<4)
107#define S3C2440_UFCON_RXTRIG8 (1<<4)
108#define S3C2440_UFCON_RXTRIG16 (2<<4)
109#define S3C2440_UFCON_RXTRIG32 (3<<4)
110
111#define S3C2440_UFCON_TXTRIG0 (0<<6)
112#define S3C2440_UFCON_TXTRIG16 (1<<6)
113#define S3C2440_UFCON_TXTRIG32 (2<<6)
114#define S3C2440_UFCON_TXTRIG48 (3<<6)
115
116#define S3C2410_UFCON_RESETBOTH (3<<1)
117#define S3C2410_UFCON_RESETTX (1<<2)
118#define S3C2410_UFCON_RESETRX (1<<1)
119
120#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
121 S3C2410_UFCON_TXTRIG0 | \
122 S3C2410_UFCON_RXTRIG8 )
123
124#define S3C2410_UMCOM_AFC (1<<4)
125#define S3C2410_UMCOM_RTS_LOW (1<<0)
126
127#define S3C2410_UFSTAT_TXFULL (1<<9)
128#define S3C2410_UFSTAT_RXFULL (1<<8)
129#define S3C2410_UFSTAT_TXMASK (15<<4)
130#define S3C2410_UFSTAT_TXSHIFT (4)
131#define S3C2410_UFSTAT_RXMASK (15<<0)
132#define S3C2410_UFSTAT_RXSHIFT (0)
133
134#define S3C2440_UFSTAT_TXFULL (1<<14)
135#define S3C2440_UFSTAT_RXFULL (1<<6)
136#define S3C2440_UFSTAT_TXSHIFT (8)
137#define S3C2440_UFSTAT_RXSHIFT (0)
138#define S3C2440_UFSTAT_TXMASK (63<<8)
139#define S3C2440_UFSTAT_RXMASK (63)
140
141#define S3C2410_UTRSTAT_TXE (1<<2)
142#define S3C2410_UTRSTAT_TXFE (1<<1)
143#define S3C2410_UTRSTAT_RXDR (1<<0)
144
145#define S3C2410_UERSTAT_OVERRUN (1<<0)
146#define S3C2410_UERSTAT_FRAME (1<<2)
147#define S3C2410_UERSTAT_BREAK (1<<3)
148#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
149 S3C2410_UERSTAT_FRAME | \
150 S3C2410_UERSTAT_BREAK)
151
152#define S3C2410_UMSTAT_CTS (1<<0)
153#define S3C2410_UMSTAT_DeltaCTS (1<<2)
154
155#ifndef __ASSEMBLY__
156
157/* struct s3c24xx_uart_clksrc
158 *
159 * this structure defines a named clock source that can be used for the
160 * uart, so that the best clock can be selected for the requested baud
161 * rate.
162 *
163 * min_baud and max_baud define the range of baud-rates this clock is
164 * acceptable for, if they are both zero, it is assumed any baud rate that
165 * can be generated from this clock will be used.
166 *
167 * divisor gives the divisor from the clock to the one seen by the uart
168*/
169
170struct s3c24xx_uart_clksrc {
171 const char *name;
172 unsigned int divisor;
173 unsigned int min_baud;
174 unsigned int max_baud;
175};
176
177/* configuration structure for per-machine configurations for the
178 * serial port
179 *
180 * the pointer is setup by the machine specific initialisation from the
181 * arch/arm/mach-s3c2410/ directory.
182*/
183
184struct s3c2410_uartcfg {
185 unsigned char hwport; /* hardware port number */
186 unsigned char unused;
187 unsigned short flags;
188 unsigned long uart_flags; /* default uart flags */
189
190 unsigned long ucon; /* value of ucon for port */
191 unsigned long ulcon; /* value of ulcon for port */
192 unsigned long ufcon; /* value of ufcon for port */
193
194 struct s3c24xx_uart_clksrc *clocks;
195 unsigned int clocks_size;
196};
197
198/* s3c24xx_uart_devs
199 *
200 * this is exported from the core as we cannot use driver_register(),
201 * or platform_add_device() before the console_initcall()
202*/
203
204extern struct platform_device *s3c24xx_uart_devs[3];
205
206#endif /* __ASSEMBLY__ */
207
208#endif /* __ASM_ARM_REGS_SERIAL_H */
209
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/arch-s3c2410/regs-spi.h
new file mode 100644
index 000000000000..cb502a88158b
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-spi.h
@@ -0,0 +1,56 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-spi.h
2 *
3 * Copyright (c) 2004 Fetron GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 SPI register definition
10 *
11 * Changelog:
12 * 20-04-2004 KF Created file
13 * 04-10-2004 BJD Removed VA address (no longer mapped)
14 * tidied file for submission
15 */
16
17#ifndef __ASM_ARCH_REGS_SPI_H
18#define __ASM_ARCH_REGS_SPI_H
19
20
21#define S3C2410_SPCON (0x00)
22
23#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
24#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
25#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
26#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
27#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
28 0: slave, 1: master */
29#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
30#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
31
32#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
33#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
34
35#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
36
37
38#define S3C2410_SPSTA (0x04)
39
40#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
41#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
42#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
43
44
45#define S3C2410_SPPIN (0x08)
46
47#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
48#define S3C2410_SPPIN_RESERVED (1<<1)
49#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
50
51
52#define S3C2410_SPPRE (0x0C)
53#define S3C2410_SPTDAT (0x10)
54#define S3C2410_SPRDAT (0x14)
55
56#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/arch-s3c2410/regs-timer.h
new file mode 100644
index 000000000000..169064e27520
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-timer.h
@@ -0,0 +1,113 @@
1/* linux/include/asm/arch-s3c2410/regs-timer.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Timer configuration
11 *
12 * Changelog:
13 * 05-06-2003 BJD Created file
14 * 26-06-2003 BJD Added more timer definitions to mux / control
15 * 12-03-2004 BJD Updated include protection
16 * 10-02-2005 BJD Added S3C2410_TCFG1_MUX4_SHIFT (Guillaume Gourat)
17 * 10-03-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
18*/
19
20
21#ifndef __ASM_ARCH_REGS_TIMER_H
22#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
23
24#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))
25#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
26
27#define S3C2410_TCFG0 S3C2410_TIMERREG(0x00)
28#define S3C2410_TCFG1 S3C2410_TIMERREG(0x04)
29#define S3C2410_TCON S3C2410_TIMERREG(0x08)
30
31#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
32#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
33#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
34#define S3C2410_TCFG_DEADZONE_MASK (255<<16)
35#define S3C2410_TCFG_DEADZONE_SHIFT (16)
36
37#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
38#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
39#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
40#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
41#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
42#define S3C2410_TCFG1_MUX4_MASK (15<<16)
43#define S3C2410_TCFG1_MUX4_SHIFT (16)
44
45#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
46#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
47#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
48#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
49#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
50#define S3C2410_TCFG1_MUX3_MASK (15<<12)
51
52
53#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
54#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
55#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
56#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
57#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
58#define S3C2410_TCFG1_MUX2_MASK (15<<8)
59
60
61#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
62#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
63#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
64#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
65#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
66#define S3C2410_TCFG1_MUX1_MASK (15<<4)
67
68#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
69#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
70#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
71#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
72#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
73#define S3C2410_TCFG1_MUX0_MASK (15<<0)
74
75/* for each timer, we have an count buffer, an compare buffer and
76 * an observation buffer
77*/
78
79/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
80
81#define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00)
82#define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04)
83#define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
84
85#define S3C2410_TCON_T4RELOAD (1<<22)
86#define S3C2410_TCON_T4MANUALUPD (1<<21)
87#define S3C2410_TCON_T4START (1<<20)
88
89#define S3C2410_TCON_T3RELOAD (1<<19)
90#define S3C2410_TCON_T3INVERT (1<<18)
91#define S3C2410_TCON_T3MANUALUPD (1<<17)
92#define S3C2410_TCON_T3START (1<<16)
93
94#define S3C2410_TCON_T2RELOAD (1<<15)
95#define S3C2410_TCON_T2INVERT (1<<14)
96#define S3C2410_TCON_T2MANUALUPD (1<<13)
97#define S3C2410_TCON_T2START (1<<12)
98
99#define S3C2410_TCON_T1RELOAD (1<<11)
100#define S3C2410_TCON_T1INVERT (1<<10)
101#define S3C2410_TCON_T1MANUALUPD (1<<9)
102#define S3C2410_TCON_T1START (1<<8)
103
104#define S3C2410_TCON_T0DEADZONE (1<<4)
105#define S3C2410_TCON_T0RELOAD (1<<3)
106#define S3C2410_TCON_T0INVERT (1<<2)
107#define S3C2410_TCON_T0MANUALUPD (1<<1)
108#define S3C2410_TCON_T0START (1<<0)
109
110#endif /* __ASM_ARCH_REGS_TIMER_H */
111
112
113
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/arch-s3c2410/regs-udc.h
new file mode 100644
index 000000000000..bf315b763252
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-udc.h
@@ -0,0 +1,164 @@
1/* linux/include/asm/arch-s3c2410/regs-udc.h
2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 *
5 * This include file is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * Changelog:
11 * 01-08-2004 Initial creation
12 * 12-09-2004 Cleanup for submission
13 * 24-10-2004 Fixed S3C2410_UDC_MAXP_REG definition
14 * 10-03-2005 Changed S3C2410_VA to S3C24XX_VA
15 */
16
17#ifndef __ASM_ARCH_REGS_UDC_H
18#define __ASM_ARCH_REGS_UDC_H
19
20
21#define S3C2410_USBDREG(x) ((x) + S3C24XX_VA_USBDEV)
22
23#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
24#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
25#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
26
27#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
28#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
29
30#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
31
32#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
33#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
34
35#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
36#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
37#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
38#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
39#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
40
41#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
42#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
43#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
44#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
45#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
46#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
47
48#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
49#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
50#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
51#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
52#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
53#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
54
55#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
56#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
57#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
58#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
59#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
60#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
61
62#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
63#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
64#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
65#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
66#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
67#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
68
69#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
70
71/* indexed registers */
72
73#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
74
75#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
76
77#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
78#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
79
80#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
81#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
82#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
83#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
84
85
86
87#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
88#define S3C2410_UDC_PWR_RESET (1<<3) // R
89#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
90#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
91#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
92
93#define S3C2410_UDC_PWR_DEFAULT 0x00
94
95#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
96#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
97#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
98#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
99#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
100
101#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
102#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
103#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
104
105#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
106#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
107#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
108#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
109#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
110
111#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
112#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
113
114
115#define S3C2410_UDC_INDEX_EP0 (0x00)
116#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
117#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
118#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
119#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
120
121#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
122#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
123#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
124#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
125#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
126#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
127
128#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
129#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
130#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
131#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
132
133#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
134#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
135#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
136#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
137#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
138#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
139#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
140
141#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
142#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
143#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
144
145#define S3C2410_UDC_SETIX(x) \
146 __raw_writel(S3C2410_UDC_INDEX_ ## x, S3C2410_UDC_INDEX_REG);
147
148
149#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
150#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
151#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
152#define S3C2410_UDC_EP0_CSR_DE (1<<3)
153#define S3C2410_UDC_EP0_CSR_SE (1<<4)
154#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
155#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
156#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
157
158#define S3C2410_UDC_MAXP_8 (1<<0)
159#define S3C2410_UDC_MAXP_16 (1<<1)
160#define S3C2410_UDC_MAXP_32 (1<<2)
161#define S3C2410_UDC_MAXP_64 (1<<3)
162
163
164#endif
diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/arch-s3c2410/regs-watchdog.h
new file mode 100644
index 000000000000..d199ca6aff22
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-watchdog.h
@@ -0,0 +1,46 @@
1/* linux/include/asm/arch-s3c2410/regs0watchdog.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Watchdog timer control
11 *
12 * Changelog:
13 * 21-06-2003 BJD Created file
14 * 12-03-2004 BJD Updated include protection
15 * 10-03-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
16*/
17
18
19#ifndef __ASM_ARCH_REGS_WATCHDOG_H
20#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
21
22#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)
23
24#define S3C2410_WTCON S3C2410_WDOGREG(0x00)
25#define S3C2410_WTDAT S3C2410_WDOGREG(0x04)
26#define S3C2410_WTCNT S3C2410_WDOGREG(0x08)
27
28/* the watchdog can either generate a reset pulse, or an
29 * interrupt.
30 */
31
32#define S3C2410_WTCON_RSTEN (0x01)
33#define S3C2410_WTCON_INTEN (1<<2)
34#define S3C2410_WTCON_ENABLE (1<<5)
35
36#define S3C2410_WTCON_DIV16 (0<<3)
37#define S3C2410_WTCON_DIV32 (1<<3)
38#define S3C2410_WTCON_DIV64 (2<<3)
39#define S3C2410_WTCON_DIV128 (3<<3)
40
41#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
42#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
43
44#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
45
46
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
new file mode 100644
index 000000000000..9b0d85024cb4
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -0,0 +1,90 @@
1/* linux/include/asm-arm/arch-s3c2410/system.h
2 *
3 * (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - System function defines and includes
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 12-May-2003 BJD Created file
14 * 14-May-2003 BJD Removed idle to aid debugging
15 * 12-Jun-2003 BJD Added reset via watchdog
16 * 04-Sep-2003 BJD Moved to v2.6
17 * 28-Oct-2004 BJD Added over-ride for idle, and fixed reset panic()
18 */
19
20#include <asm/hardware.h>
21#include <asm/io.h>
22
23#include <asm/arch/map.h>
24#include <asm/arch/idle.h>
25
26#include <asm/arch/regs-watchdog.h>
27#include <asm/arch/regs-clock.h>
28
29void (*s3c24xx_idle)(void);
30
31void s3c24xx_default_idle(void)
32{
33 void __iomem *reg = S3C2410_CLKCON;
34 unsigned long tmp;
35 int i;
36
37 /* idle the system by using the idle mode which will wait for an
38 * interrupt to happen before restarting the system.
39 */
40
41 /* Warning: going into idle state upsets jtag scanning */
42
43 __raw_writel(__raw_readl(reg) | (1<<2), reg);
44
45 /* the samsung port seems to do a loop and then unset idle.. */
46 for (i = 0; i < 50; i++) {
47 tmp += __raw_readl(reg); /* ensure loop not optimised out */
48 }
49
50 /* this bit is not cleared on re-start... */
51
52 __raw_writel(__raw_readl(reg) & ~(1<<2), reg);
53}
54
55static void arch_idle(void)
56{
57 if (s3c24xx_idle != NULL)
58 (s3c24xx_idle)();
59 else
60 s3c24xx_default_idle();
61}
62
63
64static void
65arch_reset(char mode)
66{
67 if (mode == 's') {
68 cpu_reset(0);
69 }
70
71 printk("arch_reset: attempting watchdog reset\n");
72
73 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
74
75 /* put initial values into count and data */
76 __raw_writel(0x100, S3C2410_WTCNT);
77 __raw_writel(0x100, S3C2410_WTDAT);
78
79 /* set the watchdog to go and reset... */
80 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
81 S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
82
83 /* wait for reset to assert... */
84 mdelay(5000);
85
86 printk(KERN_ERR "Watchdog reset failed to assert reset\n");
87
88 /* we'll take a jump through zero as a poor second */
89 cpu_reset(0);
90}
diff --git a/include/asm-arm/arch-s3c2410/timex.h b/include/asm-arm/arch-s3c2410/timex.h
new file mode 100644
index 000000000000..3558a3a750bf
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/timex.h
@@ -0,0 +1,32 @@
1/* linux/include/asm-arm/arch-s3c2410/timex.h
2 *
3 * (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - time parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 02-Sep-2003 BJD Created file
14 * 05-Jan-2004 BJD Updated for Linux 2.6.0
15 * 22-Nov-2004 BJD Fixed CLOCK_TICK_RATE
16 * 10-Jan-2004 BJD Removed s3c2410_clock_tick_rate
17*/
18
19#ifndef __ASM_ARCH_TIMEX_H
20#define __ASM_ARCH_TIMEX_H
21
22/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
23 * a variable is useless. It seems as long as we make our timers an
24 * exact multiple of HZ, any value that makes a 1->1 correspondence
25 * for the time conversion functions to/from jiffies is acceptable.
26*/
27
28
29#define CLOCK_TICK_RATE 12000000
30
31
32#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
new file mode 100644
index 000000000000..ad4252e27799
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -0,0 +1,158 @@
1/* linux/include/asm-arm/arch-s3c2410/uncompress.h
2 *
3 * (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 22-May-2003 BJD Created
14 * 08-Sep-2003 BJD Moved to linux v2.6
15 * 12-Mar-2004 BJD Updated header protection
16 * 12-Oct-2004 BJD Take account of debug uart configuration
17 * 15-Nov-2004 BJD Fixed uart configuration
18 * 22-Feb-2005 BJD Added watchdog to uncompress
19*/
20
21#ifndef __ASM_ARCH_UNCOMPRESS_H
22#define __ASM_ARCH_UNCOMPRESS_H
23
24#include <linux/config.h>
25
26/* defines for UART registers */
27#include "asm/arch/regs-serial.h"
28#include "asm/arch/regs-gpio.h"
29#include "asm/arch/regs-watchdog.h"
30
31#include <asm/arch/map.h>
32
33/* working in physical space... */
34#undef S3C2410_GPIOREG
35#undef S3C2410_WDOGREG
36
37#define S3C2410_GPIOREG(x) ((S3C2410_PA_GPIO + (x)))
38#define S3C2410_WDOGREG(x) ((S3C2410_PA_WATCHDOG + (x)))
39
40/* how many bytes we allow into the FIFO at a time in FIFO mode */
41#define FIFO_MAX (14)
42
43#define uart_base S3C2410_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)
44
45static __inline__ void
46uart_wr(unsigned int reg, unsigned int val)
47{
48 volatile unsigned int *ptr;
49
50 ptr = (volatile unsigned int *)(reg + uart_base);
51 *ptr = val;
52}
53
54static __inline__ unsigned int
55uart_rd(unsigned int reg)
56{
57 volatile unsigned int *ptr;
58
59 ptr = (volatile unsigned int *)(reg + uart_base);
60 return *ptr;
61}
62
63
64/* we can deal with the case the UARTs are being run
65 * in FIFO mode, so that we don't hold up our execution
66 * waiting for tx to happen...
67*/
68
69static void
70putc(char ch)
71{
72 int cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
73
74 cpuid &= S3C2410_GSTATUS1_IDMASK;
75
76 if (ch == '\n')
77 putc('\r'); /* expand newline to \r\n */
78
79 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
80 int level;
81
82 while (1) {
83 level = uart_rd(S3C2410_UFSTAT);
84
85 if (cpuid == S3C2410_GSTATUS1_2440) {
86 level &= S3C2440_UFSTAT_TXMASK;
87 level >>= S3C2440_UFSTAT_TXSHIFT;
88 } else {
89 level &= S3C2410_UFSTAT_TXMASK;
90 level >>= S3C2410_UFSTAT_TXSHIFT;
91 }
92
93 if (level < FIFO_MAX)
94 break;
95 }
96
97 } else {
98 /* not using fifos */
99
100 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE);
101 }
102
103 /* write byte to transmission register */
104 uart_wr(S3C2410_UTXH, ch);
105}
106
107static void
108putstr(const char *ptr)
109{
110 for (; *ptr != '\0'; ptr++) {
111 putc(*ptr);
112 }
113}
114
115/* CONFIG_S3C2410_BOOT_WATCHDOG
116 *
117 * Simple boot-time watchdog setup, to reboot the system if there is
118 * any problem with the boot process
119*/
120
121#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
122
123#define WDOG_COUNT (0xff00)
124
125#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
126
127static inline void arch_decomp_wdog(void)
128{
129 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
130}
131
132static void arch_decomp_wdog_start(void)
133{
134 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
135 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
136 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
137}
138
139#else
140#define arch_decomp_wdog_start()
141#define arch_decomp_wdog()
142#endif
143
144static void error(char *err);
145
146static void
147arch_decomp_setup(void)
148{
149 /* we may need to setup the uart(s) here if we are not running
150 * on an BAST... the BAST will have left the uarts configured
151 * after calling linux.
152 */
153
154 arch_decomp_wdog_start();
155}
156
157
158#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-s3c2410/usb-control.h b/include/asm-arm/arch-s3c2410/usb-control.h
new file mode 100644
index 000000000000..1cc85a096b23
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/usb-control.h
@@ -0,0 +1,45 @@
1/* linux/include/asm-arm/arch-s3c2410/usb-control.h
2 *
3 * (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - usb port information
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 11-Sep-2004 BJD Created file
14 * 21-Sep-2004 BJD Updated port info
15*/
16
17#ifndef __ASM_ARCH_USBCONTROL_H
18#define __ASM_ARCH_USBCONTROL_H "include/asm-arm/arch-s3c2410/usb-control.h"
19
20#define S3C_HCDFLG_USED (1)
21
22struct s3c2410_hcd_port {
23 unsigned char flags;
24 unsigned char power;
25 unsigned char oc_status;
26 unsigned char oc_changed;
27};
28
29struct s3c2410_hcd_info {
30 struct usb_hcd *hcd;
31 struct s3c2410_hcd_port port[2];
32
33 void (*power_control)(int port, int to);
34 void (*enable_oc)(struct s3c2410_hcd_info *, int on);
35 void (*report_oc)(struct s3c2410_hcd_info *, int ports);
36};
37
38static void inline s3c2410_report_oc(struct s3c2410_hcd_info *info, int ports)
39{
40 if (info->report_oc != NULL) {
41 (info->report_oc)(info, ports);
42 }
43}
44
45#endif /*__ASM_ARCH_USBCONTROL_H */
diff --git a/include/asm-arm/arch-s3c2410/vmalloc.h b/include/asm-arm/arch-s3c2410/vmalloc.h
new file mode 100644
index 000000000000..5fe72ad70904
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/vmalloc.h
@@ -0,0 +1,36 @@
1/* linux/include/asm-arm/arch-s3c2410/vmalloc.h
2 *
3 * from linux/include/asm-arm/arch-iop3xx/vmalloc.h
4 *
5 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
6 * http://www.simtec.co.uk/products/SWLINUX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * S3C2410 vmalloc definition
13 *
14 * Changelog:
15 * 12-Mar-2004 BJD Fixed header, added include protection
16 * 12=Mar-2004 BJD Fixed VMALLOC_END definitions
17 */
18
19#ifndef __ASM_ARCH_VMALLOC_H
20#define __ASM_ARCH_VMALLOC_H
21
22/*
23 * Just any arbitrary offset to the start of the vmalloc VM area: the
24 * current 8MB value just means that there will be a 8MB "hole" after the
25 * physical memory until the kernel virtual memory starts. That means that
26 * any out-of-bounds memory accesses will hopefully be caught.
27 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
28 * area for the same reason. ;)
29 */
30
31#define VMALLOC_OFFSET (8*1024*1024)
32#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
33#define VMALLOC_VMADDR(x) ((unsigned long)(x))
34#define VMALLOC_END (0xE0000000)
35
36#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/include/asm-arm/arch-s3c2410/vr1000-cpld.h b/include/asm-arm/arch-s3c2410/vr1000-cpld.h
new file mode 100644
index 000000000000..0ee373ac60d4
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/vr1000-cpld.h
@@ -0,0 +1,22 @@
1/* linux/include/asm-arm/arch-s3c2410/vr1000-cpld.h
2 *
3 * (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * VR1000 - CPLD control constants
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 25-May-2003 BJD Created file, added CTRL1 registers
14 * 19-Mar-2004 BJD Added VR1000 CPLD definitions
15*/
16
17#ifndef __ASM_ARCH_VR1000CPLD_H
18#define __ASM_ARCH_VR1000CPLD_H
19
20#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
21
22#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/vr1000-irq.h b/include/asm-arm/arch-s3c2410/vr1000-irq.h
new file mode 100644
index 000000000000..694f7715d2da
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/vr1000-irq.h
@@ -0,0 +1,30 @@
1/* linux/include/asm-arm/arch-s3c2410/vr1000-irq.h
2 *
3 * (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine VR1000 - IRQ Number definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 06-Jan-2003 BJD Linux 2.6.0 version
14 * 19-Mar-2004 BJD Updates for VR1000
15 */
16
17#ifndef __ASM_ARCH_VR1000IRQ_H
18#define __ASM_ARCH_VR1000IRQ_H
19
20/* irq numbers to onboard peripherals */
21
22#define IRQ_USBOC IRQ_EINT19
23#define IRQ_IDE0 IRQ_EINT16
24#define IRQ_IDE1 IRQ_EINT17
25#define IRQ_VR1000_SERIAL IRQ_EINT12
26#define IRQ_VR1000_DM9000A IRQ_EINT10
27#define IRQ_VR1000_DM9000N IRQ_EINT9
28#define IRQ_SMALERT IRQ_EINT8
29
30#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/vr1000-map.h b/include/asm-arm/arch-s3c2410/vr1000-map.h
new file mode 100644
index 000000000000..867c9355fd39
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/vr1000-map.h
@@ -0,0 +1,116 @@
1/* linux/include/asm-arm/arch-s3c2410/vr1000-map.h
2 *
3 * (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine VR1000 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 06-Jan-2003 BJD Linux 2.6.0 version, split specifics from arch/map.h
14 * 12-Mar-2004 BJD Fixed header include protection
15 * 19-Mar-2004 BJD Copied to VR1000 machine headers.
16 * 19-Jan-2005 BJD Updated map definitions
17*/
18
19/* needs arch/map.h including with this */
20
21/* ok, we've used up to 0x13000000, now we need to find space for the
22 * peripherals that live in the nGCS[x] areas, which are quite numerous
23 * in their space. We also have the board's CPLD to find register space
24 * for.
25 */
26
27#ifndef __ASM_ARCH_VR1000MAP_H
28#define __ASM_ARCH_VR1000MAP_H
29
30#include <asm/arch/bast-map.h>
31
32#define VR1000_IOADDR(x) BAST_IOADDR(x)
33
34/* we put the CPLD registers next, to get them out of the way */
35
36#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
37#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
38
39#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
40#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
41
42#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
43#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
44
45#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
46#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
47
48/* next, we have the PC104 ISA interrupt registers */
49
50#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
51#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
52
53#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
54#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
55
56#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
57#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
58
59/* 0xE0000000 contains the IO space that is split by speed and
60 * wether the access is for 8 or 16bit IO... this ensures that
61 * the correct access is made
62 *
63 * 0x10000000 of space, partitioned as so:
64 *
65 * 0x00000000 to 0x04000000 8bit, slow
66 * 0x04000000 to 0x08000000 16bit, slow
67 * 0x08000000 to 0x0C000000 16bit, net
68 * 0x0C000000 to 0x10000000 16bit, fast
69 *
70 * each of these spaces has the following in:
71 *
72 * 0x02000000 to 0x02100000 1MB IDE primary channel
73 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
74 * 0x02200000 to 0x02400000 1MB IDE secondary channel
75 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
76 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
77 * 0x02600000 to 0x02700000 1MB
78 *
79 * the phyiscal layout of the zones are:
80 * nGCS2 - 8bit, slow
81 * nGCS3 - 16bit, slow
82 * nGCS4 - 16bit, net
83 * nGCS5 - 16bit, fast
84 */
85
86#define VR1000_VA_MULTISPACE (0xE0000000)
87
88#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
89#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
90#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
91#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
92#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
93#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
94#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
95#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
96#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
97
98/* physical offset addresses for the peripherals */
99
100#define VR1000_PA_IDEPRI (0x02000000)
101#define VR1000_PA_IDEPRIAUX (0x02800000)
102#define VR1000_PA_IDESEC (0x03000000)
103#define VR1000_PA_IDESECAUX (0x03800000)
104#define VR1000_PA_DM9000 (0x05000000)
105
106#define VR1000_PA_SERIAL (0x11800000)
107#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
108
109/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
110#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
111
112/* some configurations for the peripherals */
113
114#define VR1000_DM9000_CS VR1000_VAM_CS4
115
116#endif /* __ASM_ARCH_VR1000MAP_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 07:24:46 -0500