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Diffstat (limited to 'include/asm-arm/arch-s3c2410')
-rw-r--r--include/asm-arm/arch-s3c2410/debug-macro.S2
-rw-r--r--include/asm-arm/arch-s3c2410/dma.h1
-rw-r--r--include/asm-arm/arch-s3c2410/hardware.h28
-rw-r--r--include/asm-arm/arch-s3c2410/irqs.h3
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h2
-rw-r--r--include/asm-arm/arch-s3c2410/regs-dsc.h2
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h6
-rw-r--r--include/asm-arm/arch-s3c2410/regs-mem.h6
-rw-r--r--include/asm-arm/arch-s3c2410/regs-power.h3
-rw-r--r--include/asm-arm/arch-s3c2410/system.h20
10 files changed, 65 insertions, 8 deletions
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 9c8cd9abb82b..89076c322726 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -92,11 +92,9 @@
92#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) 92#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
93#define fifo_full fifo_full_s3c2410 93#define fifo_full fifo_full_s3c2410
94#define fifo_level fifo_level_s3c2410 94#define fifo_level fifo_level_s3c2410
95#warning 2410only
96#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) 95#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
97#define fifo_full fifo_full_s3c24xx 96#define fifo_full fifo_full_s3c24xx
98#define fifo_level fifo_level_s3c24xx 97#define fifo_level fifo_level_s3c24xx
99#warning generic
100#endif 98#endif
101 99
102/* include the reset of the code which will do the work */ 100/* include the reset of the code which will do the work */
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index c6e8d8f64938..4f291d9b7d93 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -214,6 +214,7 @@ struct s3c2410_dma_chan {
214 unsigned long dev_addr; 214 unsigned long dev_addr;
215 unsigned long load_timeout; 215 unsigned long load_timeout;
216 unsigned int flags; /* channel flags */ 216 unsigned int flags; /* channel flags */
217 unsigned int hw_cfg; /* last hw config */
217 218
218 struct s3c24xx_dma_map *map; /* channel hw maps */ 219 struct s3c24xx_dma_map *map; /* channel hw maps */
219 220
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
index 6dadf58ff984..29592c3ebf22 100644
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -50,6 +50,17 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
50 50
51extern int s3c2410_gpio_getirq(unsigned int pin); 51extern int s3c2410_gpio_getirq(unsigned int pin);
52 52
53/* s3c2410_gpio_irq2pin
54 *
55 * turn the given irq number into the corresponding GPIO number
56 *
57 * returns:
58 * < 0 = no pin
59 * >=0 = gpio pin number
60*/
61
62extern int s3c2410_gpio_irq2pin(unsigned int irq);
63
53#ifdef CONFIG_CPU_S3C2400 64#ifdef CONFIG_CPU_S3C2400
54 65
55extern int s3c2400_gpio_getirq(unsigned int pin); 66extern int s3c2400_gpio_getirq(unsigned int pin);
@@ -87,6 +98,18 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
87 98
88extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); 99extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
89 100
101/* s3c2410_gpio_getpull
102 *
103 * Read the state of the pull-up on a given pin
104 *
105 * return:
106 * < 0 => error code
107 * 0 => enabled
108 * 1 => disabled
109*/
110
111extern int s3c2410_gpio_getpull(unsigned int pin);
112
90extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); 113extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
91 114
92extern unsigned int s3c2410_gpio_getpin(unsigned int pin); 115extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
@@ -99,6 +122,11 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
99 122
100#endif /* CONFIG_CPU_S3C2440 */ 123#endif /* CONFIG_CPU_S3C2440 */
101 124
125#ifdef CONFIG_CPU_S3C2412
126
127extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
128
129#endif /* CONFIG_CPU_S3C2412 */
102 130
103#endif /* __ASSEMBLY__ */ 131#endif /* __ASSEMBLY__ */
104 132
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
index 996f65488d2d..d858b3eb5547 100644
--- a/include/asm-arm/arch-s3c2410/irqs.h
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -160,4 +160,7 @@
160#define NR_IRQS (IRQ_S3C2440_AC97+1) 160#define NR_IRQS (IRQ_S3C2440_AC97+1)
161#endif 161#endif
162 162
163/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
164#define FIQ_START IRQ_EINT0
165
163#endif /* __ASM_ARCH_IRQ_H */ 166#endif /* __ASM_ARCH_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index e39656b7a086..dba9df9d8713 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -138,6 +138,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
138#define S3C2412_CLKDIVN_PDIVN (1<<2) 138#define S3C2412_CLKDIVN_PDIVN (1<<2)
139#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) 139#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
140#define S3C2421_CLKDIVN_ARMDIVN (1<<3) 140#define S3C2421_CLKDIVN_ARMDIVN (1<<3)
141#define S3C2412_CLKDIVN_DVSEN (1<<4)
142#define S3C2412_CLKDIVN_HALFHCLK (1<<5)
141#define S3C2412_CLKDIVN_USB48DIV (1<<6) 143#define S3C2412_CLKDIVN_USB48DIV (1<<6)
142#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8) 144#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
143#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8) 145#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index c0748511edbc..1235df70f34e 100644
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -19,7 +19,7 @@
19#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) 19#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
20#endif 20#endif
21 21
22#if defined(CONFIG_CPU_S3C2440) 22#if defined(CONFIG_CPU_S3C244X)
23 23
24#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) 24#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
25#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) 25#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index b693158b2d3c..0ad75d716ded 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -1133,12 +1133,16 @@
1133#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) 1133#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
1134#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) 1134#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
1135#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) 1135#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
1136#define S3C2412_GPESLPCON S3C2410_GPIOREG(0x4C)
1137#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) 1136#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
1138#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) 1137#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
1139#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) 1138#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
1140 1139
1141/* definitions for each pin bit */ 1140/* definitions for each pin bit */
1141#define S3C2412_GPIO_SLPCON_LOW ( 0x00 )
1142#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
1143#define S3C2412_GPIO_SLPCON_IN ( 0x02 )
1144#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
1145
1142#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) 1146#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
1143#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) 1147#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))
1144#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) 1148#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index e4d82341f7ba..312ff93b63c6 100644
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -98,16 +98,19 @@
98#define S3C2410_BANKCON_Tacp3 (0x1 << 2) 98#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
99#define S3C2410_BANKCON_Tacp4 (0x2 << 2) 99#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
100#define S3C2410_BANKCON_Tacp6 (0x3 << 2) 100#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
101#define S3C2410_BANKCON_Tacp_SHIFT (2)
101 102
102#define S3C2410_BANKCON_Tcah0 (0x0 << 4) 103#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
103#define S3C2410_BANKCON_Tcah1 (0x1 << 4) 104#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
104#define S3C2410_BANKCON_Tcah2 (0x2 << 4) 105#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
105#define S3C2410_BANKCON_Tcah4 (0x3 << 4) 106#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
107#define S3C2410_BANKCON_Tcah_SHIFT (4)
106 108
107#define S3C2410_BANKCON_Tcoh0 (0x0 << 6) 109#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
108#define S3C2410_BANKCON_Tcoh1 (0x1 << 6) 110#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
109#define S3C2410_BANKCON_Tcoh2 (0x2 << 6) 111#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
110#define S3C2410_BANKCON_Tcoh4 (0x3 << 6) 112#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
113#define S3C2410_BANKCON_Tcoh_SHIFT (6)
111 114
112#define S3C2410_BANKCON_Tacc1 (0x0 << 8) 115#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
113#define S3C2410_BANKCON_Tacc2 (0x1 << 8) 116#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
@@ -117,16 +120,19 @@
117#define S3C2410_BANKCON_Tacc8 (0x5 << 8) 120#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
118#define S3C2410_BANKCON_Tacc10 (0x6 << 8) 121#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
119#define S3C2410_BANKCON_Tacc14 (0x7 << 8) 122#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
123#define S3C2410_BANKCON_Tacc_SHIFT (8)
120 124
121#define S3C2410_BANKCON_Tcos0 (0x0 << 11) 125#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
122#define S3C2410_BANKCON_Tcos1 (0x1 << 11) 126#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
123#define S3C2410_BANKCON_Tcos2 (0x2 << 11) 127#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
124#define S3C2410_BANKCON_Tcos4 (0x3 << 11) 128#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
129#define S3C2410_BANKCON_Tcos_SHIFT (11)
125 130
126#define S3C2410_BANKCON_Tacs0 (0x0 << 13) 131#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
127#define S3C2410_BANKCON_Tacs1 (0x1 << 13) 132#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
128#define S3C2410_BANKCON_Tacs2 (0x2 << 13) 133#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
129#define S3C2410_BANKCON_Tacs4 (0x3 << 13) 134#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
135#define S3C2410_BANKCON_Tacs_SHIFT (13)
130 136
131#define S3C2410_BANKCON_SRAM (0x0 << 15) 137#define S3C2410_BANKCON_SRAM (0x0 << 15)
132#define S3C2400_BANKCON_EDODRAM (0x2 << 15) 138#define S3C2400_BANKCON_EDODRAM (0x2 << 15)
diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h
index f79987be55e8..13d13b7cfe98 100644
--- a/include/asm-arm/arch-s3c2410/regs-power.h
+++ b/include/asm-arm/arch-s3c2410/regs-power.h
@@ -23,7 +23,8 @@
23#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) 23#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
24#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) 24#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
25 25
26#define S3C2412_PWRCFG_BATF_IGNORE (0<<0) 26#define S3C2412_PWRCFG_BATF_IRQ (1<<0)
27#define S3C2412_PWRCFG_BATF_IGNORE (2<<0)
27#define S3C2412_PWRCFG_BATF_SLEEP (3<<0) 28#define S3C2412_PWRCFG_BATF_SLEEP (3<<0)
28#define S3C2412_PWRCFG_BATF_MASK (3<<0) 29#define S3C2412_PWRCFG_BATF_MASK (3<<0)
29 30
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 63891786dfa0..14de4e596f87 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -20,6 +20,9 @@
20#include <asm/plat-s3c/regs-watchdog.h> 20#include <asm/plat-s3c/regs-watchdog.h>
21#include <asm/arch/regs-clock.h> 21#include <asm/arch/regs-clock.h>
22 22
23#include <linux/clk.h>
24#include <linux/err.h>
25
23void (*s3c24xx_idle)(void); 26void (*s3c24xx_idle)(void);
24void (*s3c24xx_reset_hook)(void); 27void (*s3c24xx_reset_hook)(void);
25 28
@@ -59,6 +62,8 @@ static void arch_idle(void)
59static void 62static void
60arch_reset(char mode) 63arch_reset(char mode)
61{ 64{
65 struct clk *wdtclk;
66
62 if (mode == 's') { 67 if (mode == 's') {
63 cpu_reset(0); 68 cpu_reset(0);
64 } 69 }
@@ -70,19 +75,28 @@ arch_reset(char mode)
70 75
71 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ 76 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
72 77
78 wdtclk = clk_get(NULL, "watchdog");
79 if (!IS_ERR(wdtclk)) {
80 clk_enable(wdtclk);
81 } else
82 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
83
73 /* put initial values into count and data */ 84 /* put initial values into count and data */
74 __raw_writel(0x100, S3C2410_WTCNT); 85 __raw_writel(0x80, S3C2410_WTCNT);
75 __raw_writel(0x100, S3C2410_WTDAT); 86 __raw_writel(0x80, S3C2410_WTDAT);
76 87
77 /* set the watchdog to go and reset... */ 88 /* set the watchdog to go and reset... */
78 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | 89 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
79 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); 90 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
80 91
81 /* wait for reset to assert... */ 92 /* wait for reset to assert... */
82 mdelay(5000); 93 mdelay(500);
83 94
84 printk(KERN_ERR "Watchdog reset failed to assert reset\n"); 95 printk(KERN_ERR "Watchdog reset failed to assert reset\n");
85 96
97 /* delay to allow the serial port to show the message */
98 mdelay(50);
99
86 /* we'll take a jump through zero as a poor second */ 100 /* we'll take a jump through zero as a poor second */
87 cpu_reset(0); 101 cpu_reset(0);
88} 102}