diff options
Diffstat (limited to 'include/asm-arm/arch-s3c2410')
-rw-r--r-- | include/asm-arm/arch-s3c2410/gpio.h | 74 | ||||
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-clock.h | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-sdi.h | 20 |
3 files changed, 31 insertions, 65 deletions
diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h index 7583895fd336..18e10d2c35ea 100644 --- a/include/asm-arm/arch-s3c2410/gpio.h +++ b/include/asm-arm/arch-s3c2410/gpio.h | |||
@@ -1,68 +1,18 @@ | |||
1 | /* | 1 | /* linux/include/asm-arm/arch-s3c2410/gpio.h |
2 | * linux/include/asm-arm/arch-s3c2410/gpio.h | ||
3 | * | 2 | * |
4 | * S3C2410 GPIO wrappers for arch-neutral GPIO calls | 3 | * Copyright (c) 2008 Simtec Electronics |
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | 6 | * |
6 | * Written by Philipp Zabel <philipp.zabel@gmail.com> | 7 | * S3C2410 - GPIO lib support |
7 | * | 8 | * |
8 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | 10 | * it under the terms of the GNU General Public License version 2 as |
10 | * the Free Software Foundation; either version 2 of the License, or | 11 | * published by the Free Software Foundation. |
11 | * (at your option) any later version. | 12 | */ |
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | * | ||
22 | */ | ||
23 | |||
24 | #ifndef __ASM_ARCH_S3C2410_GPIO_H | ||
25 | #define __ASM_ARCH_S3C2410_GPIO_H | ||
26 | |||
27 | #include <asm/irq.h> | ||
28 | #include <asm/hardware.h> | ||
29 | #include <asm/arch/regs-gpio.h> | ||
30 | |||
31 | static inline int gpio_request(unsigned gpio, const char *label) | ||
32 | { | ||
33 | return 0; | ||
34 | } | ||
35 | |||
36 | static inline void gpio_free(unsigned gpio) | ||
37 | { | ||
38 | return; | ||
39 | } | ||
40 | |||
41 | static inline int gpio_direction_input(unsigned gpio) | ||
42 | { | ||
43 | s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_INPUT); | ||
44 | return 0; | ||
45 | } | ||
46 | |||
47 | static inline int gpio_direction_output(unsigned gpio, int value) | ||
48 | { | ||
49 | s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_OUTPUT); | ||
50 | /* REVISIT can we write the value first, to avoid glitching? */ | ||
51 | s3c2410_gpio_setpin(gpio, value); | ||
52 | return 0; | ||
53 | } | ||
54 | |||
55 | #define gpio_get_value(gpio) s3c2410_gpio_getpin(gpio) | ||
56 | #define gpio_set_value(gpio,value) s3c2410_gpio_setpin(gpio, value) | ||
57 | |||
58 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
59 | |||
60 | #ifdef CONFIG_CPU_S3C2400 | ||
61 | #define gpio_to_irq(gpio) s3c2400_gpio_getirq(gpio) | ||
62 | #else | ||
63 | #define gpio_to_irq(gpio) s3c2410_gpio_getirq(gpio) | ||
64 | #endif | ||
65 | 13 | ||
66 | /* FIXME implement irq_to_gpio() */ | 14 | #define gpio_get_value __gpio_get_value |
15 | #define gpio_set_value __gpio_set_value | ||
16 | #define gpio_cansleep __gpio_cansleep | ||
67 | 17 | ||
68 | #endif | 18 | #include <asm-generic/gpio.h> |
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index ecae9e7f5e45..37661358b42b 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h | |||
@@ -189,6 +189,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) | |||
189 | #define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) | 189 | #define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) |
190 | #define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) | 190 | #define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) |
191 | #define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) | 191 | #define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) |
192 | #define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12) | ||
193 | #define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14) | ||
192 | 194 | ||
193 | #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ | 195 | #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ |
194 | 196 | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-sdi.h b/include/asm-arm/arch-s3c2410/regs-sdi.h index bb9d30b72952..bfb222fa4abb 100644 --- a/include/asm-arm/arch-s3c2410/regs-sdi.h +++ b/include/asm-arm/arch-s3c2410/regs-sdi.h | |||
@@ -28,9 +28,15 @@ | |||
28 | #define S3C2410_SDIDCNT (0x30) | 28 | #define S3C2410_SDIDCNT (0x30) |
29 | #define S3C2410_SDIDSTA (0x34) | 29 | #define S3C2410_SDIDSTA (0x34) |
30 | #define S3C2410_SDIFSTA (0x38) | 30 | #define S3C2410_SDIFSTA (0x38) |
31 | |||
31 | #define S3C2410_SDIDATA (0x3C) | 32 | #define S3C2410_SDIDATA (0x3C) |
32 | #define S3C2410_SDIIMSK (0x40) | 33 | #define S3C2410_SDIIMSK (0x40) |
33 | 34 | ||
35 | #define S3C2440_SDIDATA (0x40) | ||
36 | #define S3C2440_SDIIMSK (0x3C) | ||
37 | |||
38 | #define S3C2440_SDICON_SDRESET (1<<8) | ||
39 | #define S3C2440_SDICON_MMCCLOCK (1<<5) | ||
34 | #define S3C2410_SDICON_BYTEORDER (1<<4) | 40 | #define S3C2410_SDICON_BYTEORDER (1<<4) |
35 | #define S3C2410_SDICON_SDIOIRQ (1<<3) | 41 | #define S3C2410_SDICON_SDIOIRQ (1<<3) |
36 | #define S3C2410_SDICON_RWAITEN (1<<2) | 42 | #define S3C2410_SDICON_RWAITEN (1<<2) |
@@ -42,7 +48,8 @@ | |||
42 | #define S3C2410_SDICMDCON_LONGRSP (1<<10) | 48 | #define S3C2410_SDICMDCON_LONGRSP (1<<10) |
43 | #define S3C2410_SDICMDCON_WAITRSP (1<<9) | 49 | #define S3C2410_SDICMDCON_WAITRSP (1<<9) |
44 | #define S3C2410_SDICMDCON_CMDSTART (1<<8) | 50 | #define S3C2410_SDICMDCON_CMDSTART (1<<8) |
45 | #define S3C2410_SDICMDCON_INDEX (0xff) | 51 | #define S3C2410_SDICMDCON_SENDERHOST (1<<6) |
52 | #define S3C2410_SDICMDCON_INDEX (0x3f) | ||
46 | 53 | ||
47 | #define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) | 54 | #define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) |
48 | #define S3C2410_SDICMDSTAT_CMDSENT (1<<11) | 55 | #define S3C2410_SDICMDSTAT_CMDSENT (1<<11) |
@@ -51,6 +58,9 @@ | |||
51 | #define S3C2410_SDICMDSTAT_XFERING (1<<8) | 58 | #define S3C2410_SDICMDSTAT_XFERING (1<<8) |
52 | #define S3C2410_SDICMDSTAT_INDEX (0xff) | 59 | #define S3C2410_SDICMDSTAT_INDEX (0xff) |
53 | 60 | ||
61 | #define S3C2440_SDIDCON_DS_BYTE (0<<22) | ||
62 | #define S3C2440_SDIDCON_DS_HALFWORD (1<<22) | ||
63 | #define S3C2440_SDIDCON_DS_WORD (2<<22) | ||
54 | #define S3C2410_SDIDCON_IRQPERIOD (1<<21) | 64 | #define S3C2410_SDIDCON_IRQPERIOD (1<<21) |
55 | #define S3C2410_SDIDCON_TXAFTERRESP (1<<20) | 65 | #define S3C2410_SDIDCON_TXAFTERRESP (1<<20) |
56 | #define S3C2410_SDIDCON_RXAFTERCMD (1<<19) | 66 | #define S3C2410_SDIDCON_RXAFTERCMD (1<<19) |
@@ -59,6 +69,7 @@ | |||
59 | #define S3C2410_SDIDCON_WIDEBUS (1<<16) | 69 | #define S3C2410_SDIDCON_WIDEBUS (1<<16) |
60 | #define S3C2410_SDIDCON_DMAEN (1<<15) | 70 | #define S3C2410_SDIDCON_DMAEN (1<<15) |
61 | #define S3C2410_SDIDCON_STOP (1<<14) | 71 | #define S3C2410_SDIDCON_STOP (1<<14) |
72 | #define S3C2440_SDIDCON_DATSTART (1<<14) | ||
62 | #define S3C2410_SDIDCON_DATMODE (3<<12) | 73 | #define S3C2410_SDIDCON_DATMODE (3<<12) |
63 | #define S3C2410_SDIDCON_BLKNUM (0x7ff) | 74 | #define S3C2410_SDIDCON_BLKNUM (0x7ff) |
64 | 75 | ||
@@ -68,6 +79,7 @@ | |||
68 | #define S3C2410_SDIDCON_XFER_RXSTART (2<<12) | 79 | #define S3C2410_SDIDCON_XFER_RXSTART (2<<12) |
69 | #define S3C2410_SDIDCON_XFER_TXSTART (3<<12) | 80 | #define S3C2410_SDIDCON_XFER_TXSTART (3<<12) |
70 | 81 | ||
82 | #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) | ||
71 | #define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) | 83 | #define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) |
72 | 84 | ||
73 | #define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) | 85 | #define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) |
@@ -82,10 +94,12 @@ | |||
82 | #define S3C2410_SDIDSTA_TXDATAON (1<<1) | 94 | #define S3C2410_SDIDSTA_TXDATAON (1<<1) |
83 | #define S3C2410_SDIDSTA_RXDATAON (1<<0) | 95 | #define S3C2410_SDIDSTA_RXDATAON (1<<0) |
84 | 96 | ||
97 | #define S3C2440_SDIFSTA_FIFORESET (1<<16) | ||
98 | #define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ | ||
85 | #define S3C2410_SDIFSTA_TFDET (1<<13) | 99 | #define S3C2410_SDIFSTA_TFDET (1<<13) |
86 | #define S3C2410_SDIFSTA_RFDET (1<<12) | 100 | #define S3C2410_SDIFSTA_RFDET (1<<12) |
87 | #define S3C2410_SDIFSTA_TXHALF (1<<11) | 101 | #define S3C2410_SDIFSTA_TFHALF (1<<11) |
88 | #define S3C2410_SDIFSTA_TXEMPTY (1<<10) | 102 | #define S3C2410_SDIFSTA_TFEMPTY (1<<10) |
89 | #define S3C2410_SDIFSTA_RFLAST (1<<9) | 103 | #define S3C2410_SDIFSTA_RFLAST (1<<9) |
90 | #define S3C2410_SDIFSTA_RFFULL (1<<8) | 104 | #define S3C2410_SDIFSTA_RFFULL (1<<8) |
91 | #define S3C2410_SDIFSTA_RFHALF (1<<7) | 105 | #define S3C2410_SDIFSTA_RFHALF (1<<7) |