diff options
Diffstat (limited to 'include/asm-arm/arch-s3c2410/vr1000-map.h')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/vr1000-map.h | 110 |
1 files changed, 0 insertions, 110 deletions
diff --git a/include/asm-arm/arch-s3c2410/vr1000-map.h b/include/asm-arm/arch-s3c2410/vr1000-map.h deleted file mode 100644 index 92a56a724a8c..000000000000 --- a/include/asm-arm/arch-s3c2410/vr1000-map.h +++ /dev/null | |||
| @@ -1,110 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/vr1000-map.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * Machine VR1000 - Memory map definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* needs arch/map.h including with this */ | ||
| 14 | |||
| 15 | /* ok, we've used up to 0x13000000, now we need to find space for the | ||
| 16 | * peripherals that live in the nGCS[x] areas, which are quite numerous | ||
| 17 | * in their space. We also have the board's CPLD to find register space | ||
| 18 | * for. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_VR1000MAP_H | ||
| 22 | #define __ASM_ARCH_VR1000MAP_H | ||
| 23 | |||
| 24 | #include <asm/arch/bast-map.h> | ||
| 25 | |||
| 26 | #define VR1000_IOADDR(x) BAST_IOADDR(x) | ||
| 27 | |||
| 28 | /* we put the CPLD registers next, to get them out of the way */ | ||
| 29 | |||
| 30 | #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */ | ||
| 31 | #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000) | ||
| 32 | |||
| 33 | #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */ | ||
| 34 | #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000) | ||
| 35 | |||
| 36 | #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */ | ||
| 37 | #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000) | ||
| 38 | |||
| 39 | #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */ | ||
| 40 | #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000) | ||
| 41 | |||
| 42 | /* next, we have the PC104 ISA interrupt registers */ | ||
| 43 | |||
| 44 | #define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ | ||
| 45 | #define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000) | ||
| 46 | |||
| 47 | #define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ | ||
| 48 | #define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000) | ||
| 49 | |||
| 50 | #define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ | ||
| 51 | #define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000) | ||
| 52 | |||
| 53 | /* 0xE0000000 contains the IO space that is split by speed and | ||
| 54 | * wether the access is for 8 or 16bit IO... this ensures that | ||
| 55 | * the correct access is made | ||
| 56 | * | ||
| 57 | * 0x10000000 of space, partitioned as so: | ||
| 58 | * | ||
| 59 | * 0x00000000 to 0x04000000 8bit, slow | ||
| 60 | * 0x04000000 to 0x08000000 16bit, slow | ||
| 61 | * 0x08000000 to 0x0C000000 16bit, net | ||
| 62 | * 0x0C000000 to 0x10000000 16bit, fast | ||
| 63 | * | ||
| 64 | * each of these spaces has the following in: | ||
| 65 | * | ||
| 66 | * 0x02000000 to 0x02100000 1MB IDE primary channel | ||
| 67 | * 0x02100000 to 0x02200000 1MB IDE primary channel aux | ||
| 68 | * 0x02200000 to 0x02400000 1MB IDE secondary channel | ||
| 69 | * 0x02300000 to 0x02400000 1MB IDE secondary channel aux | ||
| 70 | * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers | ||
| 71 | * 0x02600000 to 0x02700000 1MB | ||
| 72 | * | ||
| 73 | * the phyiscal layout of the zones are: | ||
| 74 | * nGCS2 - 8bit, slow | ||
| 75 | * nGCS3 - 16bit, slow | ||
| 76 | * nGCS4 - 16bit, net | ||
| 77 | * nGCS5 - 16bit, fast | ||
| 78 | */ | ||
| 79 | |||
| 80 | #define VR1000_VA_MULTISPACE (0xE0000000) | ||
| 81 | |||
| 82 | #define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000) | ||
| 83 | #define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000) | ||
| 84 | #define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000) | ||
| 85 | #define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000) | ||
| 86 | #define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000) | ||
| 87 | #define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000) | ||
| 88 | #define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000) | ||
| 89 | #define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000) | ||
| 90 | #define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000) | ||
| 91 | |||
| 92 | /* physical offset addresses for the peripherals */ | ||
| 93 | |||
| 94 | #define VR1000_PA_IDEPRI (0x02000000) | ||
| 95 | #define VR1000_PA_IDEPRIAUX (0x02800000) | ||
| 96 | #define VR1000_PA_IDESEC (0x03000000) | ||
| 97 | #define VR1000_PA_IDESECAUX (0x03800000) | ||
| 98 | #define VR1000_PA_DM9000 (0x05000000) | ||
| 99 | |||
| 100 | #define VR1000_PA_SERIAL (0x11800000) | ||
| 101 | #define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000)) | ||
| 102 | |||
| 103 | /* VR1000 ram is in CS1, with A26..A24 = 2_101 */ | ||
| 104 | #define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000) | ||
| 105 | |||
| 106 | /* some configurations for the peripherals */ | ||
| 107 | |||
| 108 | #define VR1000_DM9000_CS VR1000_VAM_CS4 | ||
| 109 | |||
| 110 | #endif /* __ASM_ARCH_VR1000MAP_H */ | ||