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Diffstat (limited to 'include/asm-arm/arch-s3c2410/uncompress.h')
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h145
1 files changed, 16 insertions, 129 deletions
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index dcb2cef38f50..48a5731ee988 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -1,6 +1,7 @@
1/* linux/include/asm-arm/arch-s3c2410/uncompress.h 1/* linux/include/asm-arm/arch-s3c2410/uncompress.h
2 * 2 *
3 * Copyright (c) 2003 Simtec Electronics 3 * Copyright (c) 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
5 * 6 *
6 * S3C2410 - uncompress code 7 * S3C2410 - uncompress code
@@ -13,153 +14,39 @@
13#ifndef __ASM_ARCH_UNCOMPRESS_H 14#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H 15#define __ASM_ARCH_UNCOMPRESS_H
15 16
16typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ 17#include <asm/arch/regs-gpio.h>
17
18/* defines for UART registers */
19#include "asm/arch/regs-serial.h"
20#include "asm/arch/regs-gpio.h"
21#include "asm/arch/regs-watchdog.h"
22
23#include <asm/arch/map.h> 18#include <asm/arch/map.h>
24 19
25/* working in physical space... */ 20/* working in physical space... */
26#undef S3C2410_GPIOREG 21#undef S3C2410_GPIOREG
27#undef S3C2410_WDOGREG
28
29#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) 22#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
30#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
31 23
32/* how many bytes we allow into the FIFO at a time in FIFO mode */ 24#include <asm/plat-s3c/uncompress.h>
33#define FIFO_MAX (14)
34 25
35#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT) 26static inline int is_arm926(void)
36
37static __inline__ void
38uart_wr(unsigned int reg, unsigned int val)
39{ 27{
40 volatile unsigned int *ptr; 28 unsigned int cpuid;
41
42 ptr = (volatile unsigned int *)(reg + uart_base);
43 *ptr = val;
44}
45 29
46static __inline__ unsigned int 30 asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
47uart_rd(unsigned int reg)
48{
49 volatile unsigned int *ptr;
50 31
51 ptr = (volatile unsigned int *)(reg + uart_base); 32 return ((cpuid & 0xff0) == 0x260);
52 return *ptr;
53} 33}
54 34
55 35static void arch_detect_cpu(void)
56/* we can deal with the case the UARTs are being run
57 * in FIFO mode, so that we don't hold up our execution
58 * waiting for tx to happen...
59*/
60
61static void putc(int ch)
62{ 36{
63 int cpuid = S3C2410_GSTATUS1_2410; 37 unsigned int cpuid;
64 38
65#ifndef CONFIG_CPU_S3C2400
66 cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); 39 cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
67 cpuid &= S3C2410_GSTATUS1_IDMASK; 40 cpuid &= S3C2410_GSTATUS1_IDMASK;
68#endif
69
70 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
71 int level;
72
73 while (1) {
74 level = uart_rd(S3C2410_UFSTAT);
75
76 if (cpuid == S3C2410_GSTATUS1_2440 ||
77 cpuid == S3C2410_GSTATUS1_2442) {
78 level &= S3C2440_UFSTAT_TXMASK;
79 level >>= S3C2440_UFSTAT_TXSHIFT;
80 } else {
81 level &= S3C2410_UFSTAT_TXMASK;
82 level >>= S3C2410_UFSTAT_TXSHIFT;
83 }
84
85 if (level < FIFO_MAX)
86 break;
87 }
88 41
42 if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
43 cpuid == S3C2410_GSTATUS1_2442) {
44 fifo_mask = S3C2440_UFSTAT_TXMASK;
45 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
89 } else { 46 } else {
90 /* not using fifos */ 47 fifo_mask = S3C2410_UFSTAT_TXMASK;
91 48 fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
92 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
93 barrier();
94 } 49 }
95
96 /* write byte to transmission register */
97 uart_wr(S3C2410_UTXH, ch);
98} 50}
99 51
100static inline void flush(void)
101{
102}
103
104#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
105
106/* CONFIG_S3C2410_BOOT_WATCHDOG
107 *
108 * Simple boot-time watchdog setup, to reboot the system if there is
109 * any problem with the boot process
110*/
111
112#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
113
114#define WDOG_COUNT (0xff00)
115
116static inline void arch_decomp_wdog(void)
117{
118 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
119}
120
121static void arch_decomp_wdog_start(void)
122{
123 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
124 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
125 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
126}
127
128#else
129#define arch_decomp_wdog_start()
130#define arch_decomp_wdog()
131#endif
132
133#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
134
135static void arch_decomp_error(const char *x)
136{
137 putstr("\n\n");
138 putstr(x);
139 putstr("\n\n -- System resetting\n");
140
141 __raw_writel(0x4000, S3C2410_WTDAT);
142 __raw_writel(0x4000, S3C2410_WTCNT);
143 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
144
145 while(1);
146}
147
148#define arch_error arch_decomp_error
149#endif
150
151static void error(char *err);
152
153static void
154arch_decomp_setup(void)
155{
156 /* we may need to setup the uart(s) here if we are not running
157 * on an BAST... the BAST will have left the uarts configured
158 * after calling linux.
159 */
160
161 arch_decomp_wdog_start();
162}
163
164
165#endif /* __ASM_ARCH_UNCOMPRESS_H */ 52#endif /* __ASM_ARCH_UNCOMPRESS_H */