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-rw-r--r--include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h195
1 files changed, 0 insertions, 195 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
deleted file mode 100644
index c1414658d1c5..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
+++ /dev/null
@@ -1,195 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2443 clock register definitions
12*/
13
14#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
15#define __ASM_ARM_REGS_S3C2443_CLOCK
16
17#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
18
19#define S3C2443_PLLCON_MDIVSHIFT 16
20#define S3C2443_PLLCON_PDIVSHIFT 8
21#define S3C2443_PLLCON_SDIVSHIFT 0
22#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
23#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
24#define S3C2443_PLLCON_SDIVMASK (3)
25
26#define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
27#define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
28#define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
29#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
30#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
31#define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
32#define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
33#define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
34#define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
35#define S3C2443_SWRST S3C2443_CLKREG(0x44)
36#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
37#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
38#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
39#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
40
41#define S3C2443_SWRST_RESET (0x533c2443)
42
43#define S3C2443_PLLCON_OFF (1<<24)
44
45#define S3C2443_CLKSRC_I2S_EXT (1<<14)
46#define S3C2443_CLKSRC_I2S_EPLLDIV (0<<14)
47#define S3C2443_CLKSRC_I2S_EPLLREF (2<<14)
48#define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14)
49#define S3C2443_CLKSRC_I2S_MASK (3<<14)
50
51#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<8)
52#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<8)
53#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<8)
54#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8)
55#define S3C2443_CLKSRC_EPLLREF_MASK (3<<8)
56
57#define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6)
58#define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4)
59#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
60
61#define S3C2443_CLKDIV0_DVS (1<<13)
62#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
63#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
64
65#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
66
67#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
68#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
69
70#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
71#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
72
73#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
74#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
75#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
76#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
77#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
78#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
79#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
80#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
81#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
82#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
83
84/* S3C2443_CLKDIV1 */
85
86#define S3C2443_CLKDIV1_CAMDIV_MASK (15<<26)
87#define S3C2443_CLKDIV1_CAMDIV_SHIFT (26)
88
89#define S3C2443_CLKDIV1_HSSPIDIV_MASK (3<<24)
90#define S3C2443_CLKDIV1_HSSPIDIV_SHIFT (24)
91
92#define S3C2443_CLKDIV1_DISPDIV_MASK (0xff<<16)
93#define S3C2443_CLKDIV1_DISPDIV_SHIFT (16)
94
95#define S3C2443_CLKDIV1_I2SDIV_MASK (15<<12)
96#define S3C2443_CLKDIV1_I2SDIV_SHIFT (12)
97
98#define S3C2443_CLKDIV1_UARTDIV_MASK (15<<8)
99#define S3C2443_CLKDIV1_UARTDIV_SHIFT (8)
100
101#define S3C2443_CLKDIV1_HSMMCDIV_MASK (3<<6)
102#define S3C2443_CLKDIV1_HSMMCDIV_SHIFT (6)
103
104#define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4)
105#define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4)
106
107#define S3C2443_CLKCON_NAND
108
109#define S3C2443_HCLKCON_DMA0 (1<<0)
110#define S3C2443_HCLKCON_DMA1 (1<<1)
111#define S3C2443_HCLKCON_DMA2 (1<<2)
112#define S3C2443_HCLKCON_DMA3 (1<<3)
113#define S3C2443_HCLKCON_DMA4 (1<<4)
114#define S3C2443_HCLKCON_DMA5 (1<<5)
115#define S3C2443_HCLKCON_CAMIF (1<<8)
116#define S3C2443_HCLKCON_DISP (1<<9)
117#define S3C2443_HCLKCON_LCDC (1<<10)
118#define S3C2443_HCLKCON_USBH (1<<11)
119#define S3C2443_HCLKCON_USBD (1<<12)
120#define S3C2443_HCLKCON_HSMMC (1<<16)
121#define S3C2443_HCLKCON_CFC (1<<17)
122#define S3C2443_HCLKCON_SSMC (1<<18)
123#define S3C2443_HCLKCON_DRAMC (1<<19)
124
125#define S3C2443_PCLKCON_UART0 (1<<0)
126#define S3C2443_PCLKCON_UART1 (1<<1)
127#define S3C2443_PCLKCON_UART2 (1<<2)
128#define S3C2443_PCLKCON_UART3 (1<<3)
129#define S3C2443_PCLKCON_IIC (1<<4)
130#define S3C2443_PCLKCON_SDI (1<<5)
131#define S3C2443_PCLKCON_ADC (1<<7)
132#define S3C2443_PCLKCON_AC97 (1<<8)
133#define S3C2443_PCLKCON_IIS (1<<9)
134#define S3C2443_PCLKCON_PWMT (1<<10)
135#define S3C2443_PCLKCON_WDT (1<<11)
136#define S3C2443_PCLKCON_RTC (1<<12)
137#define S3C2443_PCLKCON_GPIO (1<<13)
138#define S3C2443_PCLKCON_SPI0 (1<<14)
139#define S3C2443_PCLKCON_SPI1 (1<<15)
140
141#define S3C2443_SCLKCON_DDRCLK (1<<16)
142#define S3C2443_SCLKCON_SSMCCLK (1<<15)
143#define S3C2443_SCLKCON_HSSPICLK (1<<14)
144#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
145#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
146#define S3C2443_SCLKCON_CAMCLK (1<<11)
147#define S3C2443_SCLKCON_DISPCLK (1<<10)
148#define S3C2443_SCLKCON_I2SCLK (1<<9)
149#define S3C2443_SCLKCON_UARTCLK (1<<8)
150#define S3C2443_SCLKCON_USBHOST (1<<1)
151
152#include <asm/div64.h>
153
154static inline unsigned int
155s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
156{
157 unsigned int mdiv, pdiv, sdiv;
158 uint64_t fvco;
159
160 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
161 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
162 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
163
164 mdiv &= S3C2443_PLLCON_MDIVMASK;
165 pdiv &= S3C2443_PLLCON_PDIVMASK;
166 sdiv &= S3C2443_PLLCON_SDIVMASK;
167
168 fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
169 do_div(fvco, pdiv << sdiv);
170
171 return (unsigned int)fvco;
172}
173
174static inline unsigned int
175s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
176{
177 unsigned int mdiv, pdiv, sdiv;
178 uint64_t fvco;
179
180 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
181 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
182 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
183
184 mdiv &= S3C2443_PLLCON_MDIVMASK;
185 pdiv &= S3C2443_PLLCON_PDIVMASK;
186 sdiv &= S3C2443_PLLCON_SDIVMASK;
187
188 fvco = (uint64_t)baseclk * (mdiv + 8);
189 do_div(fvco, (pdiv + 2) << sdiv);
190
191 return (unsigned int)fvco;
192}
193
194#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
195
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