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Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-lcd.h')
-rw-r--r--include/asm-arm/arch-s3c2410/regs-lcd.h32
1 files changed, 31 insertions, 1 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index b306d6e3135d..b7faeb04c0ff 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -1,4 +1,4 @@
1/* linux/include/asm/arch-s3c2410/regs-lcd.h 1/* linux/include/asm-arm/arch-s3c2410/regs-lcd.h
2 * 2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/ 4 * http://www.simtec.co.uk/products/SWLINUX/
@@ -63,6 +63,8 @@
63#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) 63#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
64#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) 64#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
65 65
66/* LDCCON4 changes for STN mode on the S3C2412 */
67
66#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) 68#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
67#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) 69#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
68#define S3C2410_LCDCON4_WLH(x) ((x) << 0) 70#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
@@ -113,10 +115,38 @@
113#define S3C2410_LCDINT_FRSYNC (1<<1) 115#define S3C2410_LCDINT_FRSYNC (1<<1)
114#define S3C2410_LCDINT_FICNT (1<<0) 116#define S3C2410_LCDINT_FICNT (1<<0)
115 117
118/* s3c2442 extra stn registers */
119
120#define S3C2442_REDLUT S3C2410_LCDREG(0x20)
121#define S3C2442_GREENLUT S3C2410_LCDREG(0x24)
122#define S3C2442_BLUELUT S3C2410_LCDREG(0x28)
123#define S3C2442_DITHMODE S3C2410_LCDREG(0x20)
124
116#define S3C2410_LPCSEL S3C2410_LCDREG(0x60) 125#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
117 126
118#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) 127#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
119 128
129/* S3C2412 registers */
130
131#define S3C2412_TPAL S3C2410_LCDREG(0x20)
132
133#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
134#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
135#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
136
137#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
138
139#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
140#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
141#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
142#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
143
144#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
145#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
146#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
147
148#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
149
120#endif /* ___ASM_ARCH_REGS_LCD_H */ 150#endif /* ___ASM_ARCH_REGS_LCD_H */
121 151
122 152