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-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h197
1 files changed, 0 insertions, 197 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
deleted file mode 100644
index 37661358b42b..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ /dev/null
@@ -1,197 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-clock.h
2 *
3 * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 clock register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_CLOCK
14#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
15
16#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
19
20#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
21#define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
22#define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
23#define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
24#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
25#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
26
27#define S3C2410_CLKCON_IDLE (1<<2)
28#define S3C2410_CLKCON_POWER (1<<3)
29#define S3C2410_CLKCON_NAND (1<<4)
30#define S3C2410_CLKCON_LCDC (1<<5)
31#define S3C2410_CLKCON_USBH (1<<6)
32#define S3C2410_CLKCON_USBD (1<<7)
33#define S3C2410_CLKCON_PWMT (1<<8)
34#define S3C2410_CLKCON_SDI (1<<9)
35#define S3C2410_CLKCON_UART0 (1<<10)
36#define S3C2410_CLKCON_UART1 (1<<11)
37#define S3C2410_CLKCON_UART2 (1<<12)
38#define S3C2410_CLKCON_GPIO (1<<13)
39#define S3C2410_CLKCON_RTC (1<<14)
40#define S3C2410_CLKCON_ADC (1<<15)
41#define S3C2410_CLKCON_IIC (1<<16)
42#define S3C2410_CLKCON_IIS (1<<17)
43#define S3C2410_CLKCON_SPI (1<<18)
44
45#define S3C2410_PLLCON_MDIVSHIFT 12
46#define S3C2410_PLLCON_PDIVSHIFT 4
47#define S3C2410_PLLCON_SDIVSHIFT 0
48#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
49#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
50#define S3C2410_PLLCON_SDIVMASK 3
51
52/* DCLKCON register addresses in gpio.h */
53
54#define S3C2410_DCLKCON_DCLK0EN (1<<0)
55#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
56#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
57#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
58#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
59#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
60#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
61
62#define S3C2410_DCLKCON_DCLK1EN (1<<16)
63#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
64#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
65#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
66#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
67#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
68#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
69
70#define S3C2410_CLKDIVN_PDIVN (1<<0)
71#define S3C2410_CLKDIVN_HDIVN (1<<1)
72
73#define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
74#define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
75#define S3C2410_CLKSLOW_SLOW (1<<4)
76#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
77#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
78
79#ifndef __ASSEMBLY__
80
81#include <asm/div64.h>
82
83static inline unsigned int
84s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
85{
86 unsigned int mdiv, pdiv, sdiv;
87 uint64_t fvco;
88
89 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
90 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
91 sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
92
93 mdiv &= S3C2410_PLLCON_MDIVMASK;
94 pdiv &= S3C2410_PLLCON_PDIVMASK;
95 sdiv &= S3C2410_PLLCON_SDIVMASK;
96
97 fvco = (uint64_t)baseclk * (mdiv + 8);
98 do_div(fvco, (pdiv + 2) << sdiv);
99
100 return (unsigned int)fvco;
101}
102
103#endif /* __ASSEMBLY__ */
104
105#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
106
107/* extra registers */
108#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
109
110#define S3C2440_CLKCON_CAMERA (1<<19)
111#define S3C2440_CLKCON_AC97 (1<<20)
112
113#define S3C2440_CLKDIVN_PDIVN (1<<0)
114#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
115#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
116#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
117#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
118#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
119#define S3C2440_CLKDIVN_UCLK (1<<3)
120
121#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
122#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
123#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
124#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
125#define S3C2440_CAMDIVN_DVSEN (1<<12)
126
127#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
128
129#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
130
131#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
132
133#define S3C2412_OSCSET S3C2410_CLKREG(0x18)
134#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
135
136#define S3C2412_PLLCON_OFF (1<<20)
137
138#define S3C2412_CLKDIVN_PDIVN (1<<2)
139#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
140#define S3C2412_CLKDIVN_ARMDIVN (1<<3)
141#define S3C2412_CLKDIVN_DVSEN (1<<4)
142#define S3C2412_CLKDIVN_HALFHCLK (1<<5)
143#define S3C2412_CLKDIVN_USB48DIV (1<<6)
144#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
145#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
146#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
147#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
148#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
149#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
150
151#define S3C2412_CLKCON_WDT (1<<28)
152#define S3C2412_CLKCON_SPI (1<<27)
153#define S3C2412_CLKCON_IIS (1<<26)
154#define S3C2412_CLKCON_IIC (1<<25)
155#define S3C2412_CLKCON_ADC (1<<24)
156#define S3C2412_CLKCON_RTC (1<<23)
157#define S3C2412_CLKCON_GPIO (1<<22)
158#define S3C2412_CLKCON_UART2 (1<<21)
159#define S3C2412_CLKCON_UART1 (1<<20)
160#define S3C2412_CLKCON_UART0 (1<<19)
161#define S3C2412_CLKCON_SDI (1<<18)
162#define S3C2412_CLKCON_PWMT (1<<17)
163#define S3C2412_CLKCON_USBD (1<<16)
164#define S3C2412_CLKCON_CAMCLK (1<<15)
165#define S3C2412_CLKCON_UARTCLK (1<<14)
166/* missing 13 */
167#define S3C2412_CLKCON_USB_HOST48 (1<<12)
168#define S3C2412_CLKCON_USB_DEV48 (1<<11)
169#define S3C2412_CLKCON_HCLKdiv2 (1<<10)
170#define S3C2412_CLKCON_HCLKx2 (1<<9)
171#define S3C2412_CLKCON_SDRAM (1<<8)
172/* missing 7 */
173#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH
174#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC
175#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND
176#define S3C2412_CLKCON_DMA3 (1<<3)
177#define S3C2412_CLKCON_DMA2 (1<<2)
178#define S3C2412_CLKCON_DMA1 (1<<1)
179#define S3C2412_CLKCON_DMA0 (1<<0)
180
181/* clock sourec controls */
182
183#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0)
184#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0)
185#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3)
186#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4)
187#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5)
188#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8)
189#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
190#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
191#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
192#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
193#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
194
195#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
196
197#endif /* __ASM_ARM_REGS_CLOCK */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 22:31:40 -0500