diff options
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-adc.h')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-adc.h | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/arch-s3c2410/regs-adc.h deleted file mode 100644 index c7f231963e76..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-adc.h +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-adc.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Shannon Holland <holland@loser.net> | ||
| 4 | * | ||
| 5 | * This program is free software; yosu can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * S3C2410 ADC registers | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_REGS_ADC_H | ||
| 13 | #define __ASM_ARCH_REGS_ADC_H "regs-adc.h" | ||
| 14 | |||
| 15 | #define S3C2410_ADCREG(x) (x) | ||
| 16 | |||
| 17 | #define S3C2410_ADCCON S3C2410_ADCREG(0x00) | ||
| 18 | #define S3C2410_ADCTSC S3C2410_ADCREG(0x04) | ||
| 19 | #define S3C2410_ADCDLY S3C2410_ADCREG(0x08) | ||
| 20 | #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) | ||
| 21 | #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) | ||
| 22 | |||
| 23 | |||
| 24 | /* ADCCON Register Bits */ | ||
| 25 | #define S3C2410_ADCCON_ECFLG (1<<15) | ||
| 26 | #define S3C2410_ADCCON_PRSCEN (1<<14) | ||
| 27 | #define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) | ||
| 28 | #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) | ||
| 29 | #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) | ||
| 30 | #define S3C2410_ADCCON_MUXMASK (0x7<<3) | ||
| 31 | #define S3C2410_ADCCON_STDBM (1<<2) | ||
| 32 | #define S3C2410_ADCCON_READ_START (1<<1) | ||
| 33 | #define S3C2410_ADCCON_ENABLE_START (1<<0) | ||
| 34 | #define S3C2410_ADCCON_STARTMASK (0x3<<0) | ||
| 35 | |||
| 36 | |||
| 37 | /* ADCTSC Register Bits */ | ||
| 38 | #define S3C2410_ADCTSC_YM_SEN (1<<7) | ||
| 39 | #define S3C2410_ADCTSC_YP_SEN (1<<6) | ||
| 40 | #define S3C2410_ADCTSC_XM_SEN (1<<5) | ||
| 41 | #define S3C2410_ADCTSC_XP_SEN (1<<4) | ||
| 42 | #define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) | ||
| 43 | #define S3C2410_ADCTSC_AUTO_PST (1<<2) | ||
| 44 | #define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) | ||
| 45 | |||
| 46 | /* ADCDAT0 Bits */ | ||
| 47 | #define S3C2410_ADCDAT0_UPDOWN (1<<15) | ||
| 48 | #define S3C2410_ADCDAT0_AUTO_PST (1<<14) | ||
| 49 | #define S3C2410_ADCDAT0_XY_PST (0x3<<12) | ||
| 50 | #define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) | ||
| 51 | |||
| 52 | /* ADCDAT1 Bits */ | ||
| 53 | #define S3C2410_ADCDAT1_UPDOWN (1<<15) | ||
| 54 | #define S3C2410_ADCDAT1_AUTO_PST (1<<14) | ||
| 55 | #define S3C2410_ADCDAT1_XY_PST (0x3<<12) | ||
| 56 | #define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) | ||
| 57 | |||
| 58 | #endif /* __ASM_ARCH_REGS_ADC_H */ | ||
| 59 | |||
| 60 | |||