aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm/arch-s3c2410/map.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm/arch-s3c2410/map.h')
-rw-r--r--include/asm-arm/arch-s3c2410/map.h192
1 files changed, 192 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
new file mode 100644
index 000000000000..1833ea5c4220
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -0,0 +1,192 @@
1/* linux/include/asm-arm/arch-s3c2410/map.h
2 *
3 * (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 12-May-2003 BJD Created file
14 * 06-Jan-2003 BJD Linux 2.6.0 version, moved bast specifics out
15 * 10-Feb-2005 BJD Added CAMIF definition from guillaume.gourat@nexvision.tv
16 * 10-Mar-2005 LCVR Added support to S3C2400, changed {VA,SZ} names
17*/
18
19#ifndef __ASM_ARCH_MAP_H
20#define __ASM_ARCH_MAP_H
21
22/* we have a bit of a tight squeeze to fit all our registers from
23 * 0xF00000000 upwards, since we use all of the nGCS space in some
24 * capacity, and also need to fit the S3C2410 registers in as well...
25 *
26 * we try to ensure stuff like the IRQ registers are available for
27 * an single MOVS instruction (ie, only 8 bits of set data)
28 *
29 * Note, we are trying to remove some of these from the implementation
30 * as they are only useful to certain drivers...
31 */
32
33#ifndef __ASSEMBLY__
34#define S3C2410_ADDR(x) ((void __iomem *)0xF0000000 + (x))
35#else
36#define S3C2410_ADDR(x) (0xF0000000 + (x))
37#endif
38
39#define S3C2400_ADDR(x) S3C2410_ADDR(x)
40
41/* interrupt controller is the first thing we put in, to make
42 * the assembly code for the irq detection easier
43 */
44#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
45#define S3C2400_PA_IRQ (0x14400000)
46#define S3C2410_PA_IRQ (0x4A000000)
47#define S3C24XX_SZ_IRQ SZ_1M
48
49/* memory controller registers */
50#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
51#define S3C2400_PA_MEMCTRL (0x14000000)
52#define S3C2410_PA_MEMCTRL (0x48000000)
53#define S3C24XX_SZ_MEMCTRL SZ_1M
54
55/* USB host controller */
56#define S3C24XX_VA_USBHOST S3C2410_ADDR(0x00200000)
57#define S3C2400_PA_USBHOST (0x14200000)
58#define S3C2410_PA_USBHOST (0x49000000)
59#define S3C24XX_SZ_USBHOST SZ_1M
60
61/* DMA controller */
62#define S3C24XX_VA_DMA S3C2410_ADDR(0x00300000)
63#define S3C2400_PA_DMA (0x14600000)
64#define S3C2410_PA_DMA (0x4B000000)
65#define S3C24XX_SZ_DMA SZ_1M
66
67/* Clock and Power management */
68#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00400000)
69#define S3C2400_PA_CLKPWR (0x14800000)
70#define S3C2410_PA_CLKPWR (0x4C000000)
71#define S3C24XX_SZ_CLKPWR SZ_1M
72
73/* LCD controller */
74#define S3C24XX_VA_LCD S3C2410_ADDR(0x00600000)
75#define S3C2400_PA_LCD (0x14A00000)
76#define S3C2410_PA_LCD (0x4D000000)
77#define S3C24XX_SZ_LCD SZ_1M
78
79/* NAND flash controller */
80#define S3C24XX_VA_NAND S3C2410_ADDR(0x00700000)
81#define S3C2410_PA_NAND (0x4E000000)
82#define S3C24XX_SZ_NAND SZ_1M
83
84/* MMC controller - available on the S3C2400 */
85#define S3C2400_VA_MMC S3C2400_ADDR(0x00700000)
86#define S3C2400_PA_MMC (0x15A00000)
87#define S3C2400_SZ_MMC SZ_1M
88
89/* UARTs */
90#define S3C24XX_VA_UART S3C2410_ADDR(0x00800000)
91#define S3C2400_PA_UART (0x15000000)
92#define S3C2410_PA_UART (0x50000000)
93#define S3C24XX_SZ_UART SZ_1M
94
95/* Timers */
96#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00900000)
97#define S3C2400_PA_TIMER (0x15100000)
98#define S3C2410_PA_TIMER (0x51000000)
99#define S3C24XX_SZ_TIMER SZ_1M
100
101/* USB Device port */
102#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00A00000)
103#define S3C2400_PA_USBDEV (0x15200140)
104#define S3C2410_PA_USBDEV (0x52000000)
105#define S3C24XX_SZ_USBDEV SZ_1M
106
107/* Watchdog */
108#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
109#define S3C2400_PA_WATCHDOG (0x15300000)
110#define S3C2410_PA_WATCHDOG (0x53000000)
111#define S3C24XX_SZ_WATCHDOG SZ_1M
112
113/* IIC hardware controller */
114#define S3C24XX_VA_IIC S3C2410_ADDR(0x00C00000)
115#define S3C2400_PA_IIC (0x15400000)
116#define S3C2410_PA_IIC (0x54000000)
117#define S3C24XX_SZ_IIC SZ_1M
118
119#define VA_IIC_BASE (S3C24XX_VA_IIC)
120
121/* IIS controller */
122#define S3C24XX_VA_IIS S3C2410_ADDR(0x00D00000)
123#define S3C2400_PA_IIS (0x15508000)
124#define S3C2410_PA_IIS (0x55000000)
125#define S3C24XX_SZ_IIS SZ_1M
126
127/* GPIO ports */
128#define S3C24XX_VA_GPIO S3C2410_ADDR(0x00E00000)
129#define S3C2400_PA_GPIO (0x15600000)
130#define S3C2410_PA_GPIO (0x56000000)
131#define S3C24XX_SZ_GPIO SZ_1M
132
133/* RTC */
134#define S3C24XX_VA_RTC S3C2410_ADDR(0x00F00000)
135#define S3C2400_PA_RTC (0x15700040)
136#define S3C2410_PA_RTC (0x57000000)
137#define S3C24XX_SZ_RTC SZ_1M
138
139/* ADC */
140#define S3C24XX_VA_ADC S3C2410_ADDR(0x01000000)
141#define S3C2400_PA_ADC (0x15800000)
142#define S3C2410_PA_ADC (0x58000000)
143#define S3C24XX_SZ_ADC SZ_1M
144
145/* SPI */
146#define S3C24XX_VA_SPI S3C2410_ADDR(0x01100000)
147#define S3C2400_PA_SPI (0x15900000)
148#define S3C2410_PA_SPI (0x59000000)
149#define S3C24XX_SZ_SPI SZ_1M
150
151/* SDI */
152#define S3C24XX_VA_SDI S3C2410_ADDR(0x01200000)
153#define S3C2410_PA_SDI (0x5A000000)
154#define S3C24XX_SZ_SDI SZ_1M
155
156/* CAMIF */
157#define S3C2440_PA_CAMIF (0x4F000000)
158#define S3C2440_SZ_CAMIF SZ_1M
159
160/* ISA style IO, for each machine to sort out mappings for, if it
161 * implements it. We reserve two 16M regions for ISA.
162 */
163
164#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
165#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
166
167/* physical addresses of all the chip-select areas */
168
169#define S3C2410_CS0 (0x00000000)
170#define S3C2410_CS1 (0x08000000)
171#define S3C2410_CS2 (0x10000000)
172#define S3C2410_CS3 (0x18000000)
173#define S3C2410_CS4 (0x20000000)
174#define S3C2410_CS5 (0x28000000)
175#define S3C2410_CS6 (0x30000000)
176#define S3C2410_CS7 (0x38000000)
177
178#define S3C2410_SDRAM_PA (S3C2410_CS6)
179
180#define S3C2400_CS0 (0x00000000)
181#define S3C2400_CS1 (0x02000000)
182#define S3C2400_CS2 (0x04000000)
183#define S3C2400_CS3 (0x06000000)
184#define S3C2400_CS4 (0x08000000)
185#define S3C2400_CS5 (0x0A000000)
186#define S3C2400_CS6 (0x0C000000)
187#define S3C2400_CS7 (0x0E000000)
188
189#define S3C2400_SDRAM_PA (S3C2400_CS6)
190
191
192#endif /* __ASM_ARCH_MAP_H */