aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm/arch-s3c2410/dma.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm/arch-s3c2410/dma.h')
-rw-r--r--include/asm-arm/arch-s3c2410/dma.h80
1 files changed, 36 insertions, 44 deletions
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index 7463fd5252ce..46e65409fcc5 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -35,14 +35,14 @@
35 35
36/* types */ 36/* types */
37 37
38typedef enum { 38enum s3c2410_dma_state {
39 S3C2410_DMA_IDLE, 39 S3C2410_DMA_IDLE,
40 S3C2410_DMA_RUNNING, 40 S3C2410_DMA_RUNNING,
41 S3C2410_DMA_PAUSED 41 S3C2410_DMA_PAUSED
42} s3c2410_dma_state_t; 42};
43 43
44 44
45/* s3c2410_dma_loadst_t 45/* enum s3c2410_dma_loadst
46 * 46 *
47 * This represents the state of the DMA engine, wrt to the loaded / running 47 * This represents the state of the DMA engine, wrt to the loaded / running
48 * transfers. Since we don't have any way of knowing exactly the state of 48 * transfers. Since we don't have any way of knowing exactly the state of
@@ -70,34 +70,32 @@ typedef enum {
70 * currently running. 70 * currently running.
71*/ 71*/
72 72
73typedef enum { 73enum s3c2410_dma_loadst {
74 S3C2410_DMALOAD_NONE, 74 S3C2410_DMALOAD_NONE,
75 S3C2410_DMALOAD_1LOADED, 75 S3C2410_DMALOAD_1LOADED,
76 S3C2410_DMALOAD_1RUNNING, 76 S3C2410_DMALOAD_1RUNNING,
77 S3C2410_DMALOAD_1LOADED_1RUNNING, 77 S3C2410_DMALOAD_1LOADED_1RUNNING,
78} s3c2410_dma_loadst_t; 78};
79 79
80typedef enum { 80enum s3c2410_dma_buffresult {
81 S3C2410_RES_OK, 81 S3C2410_RES_OK,
82 S3C2410_RES_ERR, 82 S3C2410_RES_ERR,
83 S3C2410_RES_ABORT 83 S3C2410_RES_ABORT
84} s3c2410_dma_buffresult_t; 84};
85
86 85
87typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
88 86
89enum s3c2410_dmasrc_e { 87enum s3c2410_dmasrc {
90 S3C2410_DMASRC_HW, /* source is memory */ 88 S3C2410_DMASRC_HW, /* source is memory */
91 S3C2410_DMASRC_MEM /* source is hardware */ 89 S3C2410_DMASRC_MEM /* source is hardware */
92}; 90};
93 91
94/* enum s3c2410_chan_op_e 92/* enum s3c2410_chan_op
95 * 93 *
96 * operation codes passed to the DMA code by the user, and also used 94 * operation codes passed to the DMA code by the user, and also used
97 * to inform the current channel owner of any changes to the system state 95 * to inform the current channel owner of any changes to the system state
98*/ 96*/
99 97
100enum s3c2410_chan_op_e { 98enum s3c2410_chan_op {
101 S3C2410_DMAOP_START, 99 S3C2410_DMAOP_START,
102 S3C2410_DMAOP_STOP, 100 S3C2410_DMAOP_STOP,
103 S3C2410_DMAOP_PAUSE, 101 S3C2410_DMAOP_PAUSE,
@@ -107,8 +105,6 @@ enum s3c2410_chan_op_e {
107 S3C2410_DMAOP_STARTED, /* indicate channel started */ 105 S3C2410_DMAOP_STARTED, /* indicate channel started */
108}; 106};
109 107
110typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
111
112/* flags */ 108/* flags */
113 109
114#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about 110#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
@@ -117,22 +113,19 @@ typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
117 113
118/* dma buffer */ 114/* dma buffer */
119 115
120typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
121
122struct s3c2410_dma_client { 116struct s3c2410_dma_client {
123 char *name; 117 char *name;
124}; 118};
125 119
126typedef struct s3c2410_dma_client s3c2410_dma_client_t;
127
128/* s3c2410_dma_buf_s 120/* s3c2410_dma_buf_s
129 * 121 *
130 * internally used buffer structure to describe a queued or running 122 * internally used buffer structure to describe a queued or running
131 * buffer. 123 * buffer.
132*/ 124*/
133 125
134struct s3c2410_dma_buf_s { 126struct s3c2410_dma_buf;
135 s3c2410_dma_buf_t *next; 127struct s3c2410_dma_buf {
128 struct s3c2410_dma_buf *next;
136 int magic; /* magic */ 129 int magic; /* magic */
137 int size; /* buffer size in bytes */ 130 int size; /* buffer size in bytes */
138 dma_addr_t data; /* start of DMA data */ 131 dma_addr_t data; /* start of DMA data */
@@ -142,20 +135,21 @@ struct s3c2410_dma_buf_s {
142 135
143/* [1] is this updated for both recv/send modes? */ 136/* [1] is this updated for both recv/send modes? */
144 137
145typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t; 138struct s3c2410_dma_chan;
146 139
147/* s3c2410_dma_cbfn_t 140/* s3c2410_dma_cbfn_t
148 * 141 *
149 * buffer callback routine type 142 * buffer callback routine type
150*/ 143*/
151 144
152typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size, 145typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
153 s3c2410_dma_buffresult_t result); 146 void *buf, int size,
147 enum s3c2410_dma_buffresult result);
154 148
155typedef int (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *, 149typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
156 s3c2410_chan_op_t ); 150 enum s3c2410_chan_op );
157 151
158struct s3c2410_dma_stats_s { 152struct s3c2410_dma_stats {
159 unsigned long loads; 153 unsigned long loads;
160 unsigned long timeout_longest; 154 unsigned long timeout_longest;
161 unsigned long timeout_shortest; 155 unsigned long timeout_shortest;
@@ -163,14 +157,12 @@ struct s3c2410_dma_stats_s {
163 unsigned long timeout_failed; 157 unsigned long timeout_failed;
164}; 158};
165 159
166typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t; 160/* struct s3c2410_dma_chan
167
168/* struct s3c2410_dma_chan_s
169 * 161 *
170 * full state information for each DMA channel 162 * full state information for each DMA channel
171*/ 163*/
172 164
173struct s3c2410_dma_chan_s { 165struct s3c2410_dma_chan {
174 /* channel state flags and information */ 166 /* channel state flags and information */
175 unsigned char number; /* number of this dma channel */ 167 unsigned char number; /* number of this dma channel */
176 unsigned char in_use; /* channel allocated */ 168 unsigned char in_use; /* channel allocated */
@@ -180,12 +172,12 @@ struct s3c2410_dma_chan_s {
180 172
181 /* channel state */ 173 /* channel state */
182 174
183 s3c2410_dma_state_t state; 175 enum s3c2410_dma_state state;
184 s3c2410_dma_loadst_t load_state; 176 enum s3c2410_dma_loadst load_state;
185 s3c2410_dma_client_t *client; 177 struct s3c2410_dma_client *client;
186 178
187 /* channel configuration */ 179 /* channel configuration */
188 s3c2410_dmasrc_t source; 180 enum s3c2410_dmasrc source;
189 unsigned long dev_addr; 181 unsigned long dev_addr;
190 unsigned long load_timeout; 182 unsigned long load_timeout;
191 unsigned int flags; /* channel flags */ 183 unsigned int flags; /* channel flags */
@@ -201,20 +193,20 @@ struct s3c2410_dma_chan_s {
201 s3c2410_dma_opfn_t op_fn; /* channel operation callback */ 193 s3c2410_dma_opfn_t op_fn; /* channel operation callback */
202 194
203 /* stats gathering */ 195 /* stats gathering */
204 s3c2410_dma_stats_t *stats; 196 struct s3c2410_dma_stats *stats;
205 s3c2410_dma_stats_t stats_store; 197 struct s3c2410_dma_stats stats_store;
206 198
207 /* buffer list and information */ 199 /* buffer list and information */
208 s3c2410_dma_buf_t *curr; /* current dma buffer */ 200 struct s3c2410_dma_buf *curr; /* current dma buffer */
209 s3c2410_dma_buf_t *next; /* next buffer to load */ 201 struct s3c2410_dma_buf *next; /* next buffer to load */
210 s3c2410_dma_buf_t *end; /* end of queue */ 202 struct s3c2410_dma_buf *end; /* end of queue */
211 203
212 /* system device */ 204 /* system device */
213 struct sys_device dev; 205 struct sys_device dev;
214}; 206};
215 207
216/* the currently allocated channel information */ 208/* the currently allocated channel information */
217extern s3c2410_dma_chan_t s3c2410_chans[]; 209extern struct s3c2410_dma_chan s3c2410_chans[];
218 210
219/* note, we don't really use dma_device_t at the moment */ 211/* note, we don't really use dma_device_t at the moment */
220typedef unsigned long dma_device_t; 212typedef unsigned long dma_device_t;
@@ -227,7 +219,7 @@ typedef unsigned long dma_device_t;
227*/ 219*/
228 220
229extern int s3c2410_dma_request(dmach_t channel, 221extern int s3c2410_dma_request(dmach_t channel,
230 s3c2410_dma_client_t *, void *dev); 222 struct s3c2410_dma_client *, void *dev);
231 223
232 224
233/* s3c2410_dma_ctrl 225/* s3c2410_dma_ctrl
@@ -235,7 +227,7 @@ extern int s3c2410_dma_request(dmach_t channel,
235 * change the state of the dma channel 227 * change the state of the dma channel
236*/ 228*/
237 229
238extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op); 230extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
239 231
240/* s3c2410_dma_setflags 232/* s3c2410_dma_setflags
241 * 233 *
@@ -250,7 +242,7 @@ extern int s3c2410_dma_setflags(dmach_t channel,
250 * free the dma channel (will also abort any outstanding operations) 242 * free the dma channel (will also abort any outstanding operations)
251*/ 243*/
252 244
253extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *); 245extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
254 246
255/* s3c2410_dma_enqueue 247/* s3c2410_dma_enqueue
256 * 248 *
@@ -274,7 +266,7 @@ extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
274 * configure the device we're talking to 266 * configure the device we're talking to
275*/ 267*/
276 268
277extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source, 269extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
278 int hwcfg, unsigned long devaddr); 270 int hwcfg, unsigned long devaddr);
279 271
280/* s3c2410_dma_getposition 272/* s3c2410_dma_getposition