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-rw-r--r--include/asm-arm/arch-realview/platform.h170
1 files changed, 10 insertions, 160 deletions
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 6e0eab95a3a2..4fd351b5e4a2 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -18,8 +18,8 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20 20
21#ifndef __address_h 21#ifndef __ASM_ARCH_PLATFORM_H
22#define __address_h 1 22#define __ASM_ARCH_PLATFORM_H
23 23
24/* 24/*
25 * Memory definitions 25 * Memory definitions
@@ -81,11 +81,12 @@
81#define REALVIEW_SYS_24MHz_OFFSET 0x5C 81#define REALVIEW_SYS_24MHz_OFFSET 0x5C
82#define REALVIEW_SYS_MISC_OFFSET 0x60 82#define REALVIEW_SYS_MISC_OFFSET 0x60
83#define REALVIEW_SYS_IOSEL_OFFSET 0x70 83#define REALVIEW_SYS_IOSEL_OFFSET 0x70
84#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 84#define REALVIEW_SYS_PROCID_OFFSET 0x84
85#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 85#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
86#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 86#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
87#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C 87#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
88#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 88#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
89#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
89 90
90#define REALVIEW_SYS_BASE 0x10000000 91#define REALVIEW_SYS_BASE 0x10000000
91#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) 92#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
@@ -114,6 +115,7 @@
114#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) 115#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
115#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) 116#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
116#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) 117#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
118#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
117#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) 119#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
118#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) 120#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
119#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) 121#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
@@ -203,30 +205,8 @@
203 /* Reserved 0x1001A000 - 0x1001FFFF */ 205 /* Reserved 0x1001A000 - 0x1001FFFF */
204#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ 206#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
205#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ 207#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
206#ifndef CONFIG_REALVIEW_MPCORE
207#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ 208#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
208#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ 209#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
209#else
210#ifdef CONFIG_REALVIEW_MPCORE_REVB
211#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
212#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
213#define REALVIEW_TWD_BASE 0x10100700
214#define REALVIEW_TWD_SIZE 0x00000100
215#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
216#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */
217#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
218#else
219#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
220#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
221#define REALVIEW_TWD_BASE 0x1F000700
222#define REALVIEW_TWD_SIZE 0x00000100
223#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
224#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */
225#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
226#endif
227#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
228#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
229#endif
230#define REALVIEW_SMC_BASE 0x10080000 /* SMC */ 210#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
231 /* Reserved 0x10090000 - 0x100EFFFF */ 211 /* Reserved 0x10090000 - 0x100EFFFF */
232 212
@@ -283,134 +263,6 @@
283#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ 263#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
284#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ 264#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
285 265
286/* ------------------------------------------------------------------------
287 * Interrupts - bit assignment (primary)
288 * ------------------------------------------------------------------------
289 */
290#ifndef CONFIG_REALVIEW_MPCORE
291#define INT_WDOGINT 0 /* Watchdog timer */
292#define INT_SOFTINT 1 /* Software interrupt */
293#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
294#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
295#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
296#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
297#define INT_GPIOINT0 6 /* GPIO 0 */
298#define INT_GPIOINT1 7 /* GPIO 1 */
299#define INT_GPIOINT2 8 /* GPIO 2 */
300/* 9 reserved */
301#define INT_RTCINT 10 /* Real Time Clock */
302#define INT_SSPINT 11 /* Synchronous Serial Port */
303#define INT_UARTINT0 12 /* UART 0 on development chip */
304#define INT_UARTINT1 13 /* UART 1 on development chip */
305#define INT_UARTINT2 14 /* UART 2 on development chip */
306#define INT_UARTINT3 15 /* UART 3 on development chip */
307#define INT_SCIINT 16 /* Smart Card Interface */
308#define INT_MMCI0A 17 /* Multimedia Card 0A */
309#define INT_MMCI0B 18 /* Multimedia Card 0B */
310#define INT_AACI 19 /* Audio Codec */
311#define INT_KMI0 20 /* Keyboard/Mouse port 0 */
312#define INT_KMI1 21 /* Keyboard/Mouse port 1 */
313#define INT_CHARLCD 22 /* Character LCD */
314#define INT_CLCDINT 23 /* CLCD controller */
315#define INT_DMAINT 24 /* DMA controller */
316#define INT_PWRFAILINT 25 /* Power failure */
317#define INT_PISMO 26
318#define INT_DoC 27 /* Disk on Chip memory controller */
319#define INT_ETH 28 /* Ethernet controller */
320#define INT_USB 29 /* USB controller */
321#define INT_TSPENINT 30 /* Touchscreen pen */
322#define INT_TSKPADINT 31 /* Touchscreen keypad */
323
324#else
325
326#define MAX_GIC_NR 2
327
328#define INT_AACI 0
329#define INT_TIMERINT0_1 1
330#define INT_TIMERINT2_3 2
331#define INT_USB 3
332#define INT_UARTINT0 4
333#define INT_UARTINT1 5
334#define INT_RTCINT 6
335#define INT_KMI0 7
336#define INT_KMI1 8
337#define INT_ETH 9
338#define INT_EB_IRQ1 10 /* main GIC */
339#define INT_EB_IRQ2 11 /* tile GIC */
340#define INT_EB_FIQ1 12 /* main GIC */
341#define INT_EB_FIQ2 13 /* tile GIC */
342#define INT_MMCI0A 14
343#define INT_MMCI0B 15
344
345#define INT_PMU_CPU0 17
346#define INT_PMU_CPU1 18
347#define INT_PMU_CPU2 19
348#define INT_PMU_CPU3 20
349#define INT_PMU_SCU0 21
350#define INT_PMU_SCU1 22
351#define INT_PMU_SCU2 23
352#define INT_PMU_SCU3 24
353#define INT_PMU_SCU4 25
354#define INT_PMU_SCU5 26
355#define INT_PMU_SCU6 27
356#define INT_PMU_SCU7 28
357
358#define INT_L220_EVENT 29
359#define INT_L220_SLAVE 30
360#define INT_L220_DECODE 31
361
362#define INT_UARTINT2 -1
363#define INT_UARTINT3 -1
364#define INT_CLCDINT -1
365#define INT_DMAINT -1
366#define INT_WDOGINT -1
367#define INT_GPIOINT0 -1
368#define INT_GPIOINT1 -1
369#define INT_GPIOINT2 -1
370#define INT_SCIINT -1
371#define INT_SSPINT -1
372#endif
373
374/*
375 * Interrupt bit positions
376 *
377 */
378#define INTMASK_WDOGINT (1 << INT_WDOGINT)
379#define INTMASK_SOFTINT (1 << INT_SOFTINT)
380#define INTMASK_COMMRx (1 << INT_COMMRx)
381#define INTMASK_COMMTx (1 << INT_COMMTx)
382#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
383#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
384#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
385#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
386#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
387#define INTMASK_RTCINT (1 << INT_RTCINT)
388#define INTMASK_SSPINT (1 << INT_SSPINT)
389#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
390#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
391#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
392#define INTMASK_UARTINT3 (1 << INT_UARTINT3)
393#define INTMASK_SCIINT (1 << INT_SCIINT)
394#define INTMASK_MMCI0A (1 << INT_MMCI0A)
395#define INTMASK_MMCI0B (1 << INT_MMCI0B)
396#define INTMASK_AACI (1 << INT_AACI)
397#define INTMASK_KMI0 (1 << INT_KMI0)
398#define INTMASK_KMI1 (1 << INT_KMI1)
399#define INTMASK_CHARLCD (1 << INT_CHARLCD)
400#define INTMASK_CLCDINT (1 << INT_CLCDINT)
401#define INTMASK_DMAINT (1 << INT_DMAINT)
402#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
403#define INTMASK_PISMO (1 << INT_PISMO)
404#define INTMASK_DoC (1 << INT_DoC)
405#define INTMASK_ETH (1 << INT_ETH)
406#define INTMASK_USB (1 << INT_USB)
407#define INTMASK_TSPENINT (1 << INT_TSPENINT)
408#define INTMASK_TSKPADINT (1 << INT_TSKPADINT)
409
410#define MAXIRQNUM 31
411#define MAXFIQNUM 31
412#define MAXSWINUM 31
413
414/* 266/*
415 * Application Flash 267 * Application Flash
416 * 268 *
@@ -463,6 +315,4 @@
463#define REALVIEW_CSR_BASE 0x10000000 315#define REALVIEW_CSR_BASE 0x10000000
464#define REALVIEW_CSR_SIZE 0x10000000 316#define REALVIEW_CSR_SIZE 0x10000000
465 317
466#endif 318#endif /* __ASM_ARCH_PLATFORM_H */
467
468/* END */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 20:42:40 -0500