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-rw-r--r--include/asm-arm/arch-realview/entry-macro.S25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 2712ba77bb3a..6288fad0dc41 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -47,3 +47,28 @@
47 cmpcs \irqnr, \irqnr 47 cmpcs \irqnr, \irqnr
48 48
49 .endm 49 .endm
50
51 /* We assume that irqstat (the raw value of the IRQ acknowledge
52 * register) is preserved from the macro above.
53 * If there is an IPI, we immediately signal end of interrupt on the
54 * controller, since this requires the original irqstat value which
55 * we won't easily be able to recreate later.
56 */
57
58 .macro test_for_ipi, irqnr, irqstat, base, tmp
59 bic \irqnr, \irqstat, #0x1c00
60 cmp \irqnr, #16
61 strcc \irqstat, [\base, #GIC_CPU_EOI]
62 cmpcs \irqnr, \irqnr
63 .endm
64
65 /* As above, this assumes that irqstat and base are preserved.. */
66
67 .macro test_for_ltirq, irqnr, irqstat, base, tmp
68 bic \irqnr, \irqstat, #0x1c00
69 mov \tmp, #0
70 cmp \irqnr, #29
71 moveq \tmp, #1
72 streq \irqstat, [\base, #GIC_CPU_EOI]
73 cmp \tmp, #0
74 .endm