diff options
Diffstat (limited to 'include/asm-arm/arch-pxa')
-rw-r--r-- | include/asm-arm/arch-pxa/hardware.h | 4 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/io.h | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/irda.h | 17 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/memory.h | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 42 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/uncompress.h | 1 |
6 files changed, 63 insertions, 5 deletions
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index cf35721cfa45..3e70bd95472c 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h | |||
@@ -44,12 +44,12 @@ | |||
44 | 44 | ||
45 | #ifndef __ASSEMBLY__ | 45 | #ifndef __ASSEMBLY__ |
46 | 46 | ||
47 | # define __REG(x) (*((volatile unsigned long *)io_p2v(x))) | 47 | # define __REG(x) (*((volatile u32 *)io_p2v(x))) |
48 | 48 | ||
49 | /* With indexed regs we don't want to feed the index through io_p2v() | 49 | /* With indexed regs we don't want to feed the index through io_p2v() |
50 | especially if it is a variable, otherwise horrible code will result. */ | 50 | especially if it is a variable, otherwise horrible code will result. */ |
51 | # define __REG2(x,y) \ | 51 | # define __REG2(x,y) \ |
52 | (*(volatile unsigned long *)((unsigned long)&__REG(x) + (y))) | 52 | (*(volatile u32 *)((u32)&__REG(x) + (y))) |
53 | 53 | ||
54 | # define __PREG(x) (io_v2p((u32)&(x))) | 54 | # define __PREG(x) (io_v2p((u32)&(x))) |
55 | 55 | ||
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h index c3bdbe44e21f..eb2dd58d397f 100644 --- a/include/asm-arm/arch-pxa/io.h +++ b/include/asm-arm/arch-pxa/io.h | |||
@@ -6,6 +6,8 @@ | |||
6 | #ifndef __ASM_ARM_ARCH_IO_H | 6 | #ifndef __ASM_ARM_ARCH_IO_H |
7 | #define __ASM_ARM_ARCH_IO_H | 7 | #define __ASM_ARM_ARCH_IO_H |
8 | 8 | ||
9 | #include <asm/hardware.h> | ||
10 | |||
9 | #define IO_SPACE_LIMIT 0xffffffff | 11 | #define IO_SPACE_LIMIT 0xffffffff |
10 | 12 | ||
11 | /* | 13 | /* |
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h new file mode 100644 index 000000000000..748406f384c2 --- /dev/null +++ b/include/asm-arm/arch-pxa/irda.h | |||
@@ -0,0 +1,17 @@ | |||
1 | #ifndef ASMARM_ARCH_IRDA_H | ||
2 | #define ASMARM_ARCH_IRDA_H | ||
3 | |||
4 | /* board specific transceiver capabilities */ | ||
5 | |||
6 | #define IR_OFF 1 | ||
7 | #define IR_SIRMODE 2 | ||
8 | #define IR_FIRMODE 4 | ||
9 | |||
10 | struct pxaficp_platform_data { | ||
11 | int transceiver_cap; | ||
12 | void (*transceiver_mode)(struct device *dev, int mode); | ||
13 | }; | ||
14 | |||
15 | extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); | ||
16 | |||
17 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h index 58bad9748b5c..eaf6d43939e9 100644 --- a/include/asm-arm/arch-pxa/memory.h +++ b/include/asm-arm/arch-pxa/memory.h | |||
@@ -15,7 +15,7 @@ | |||
15 | /* | 15 | /* |
16 | * Physical DRAM offset. | 16 | * Physical DRAM offset. |
17 | */ | 17 | */ |
18 | #define PHYS_OFFSET (0xa0000000UL) | 18 | #define PHYS_OFFSET UL(0xa0000000) |
19 | 19 | ||
20 | /* | 20 | /* |
21 | * Virtual view <-> DMA view memory address translations | 21 | * Virtual view <-> DMA view memory address translations |
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 3af7165ab0d7..a75a2470f4f5 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
@@ -326,6 +326,25 @@ | |||
326 | #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | 326 | #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ |
327 | #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | 327 | #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ |
328 | 328 | ||
329 | /* Hardware UART (HWUART) */ | ||
330 | #define HWUART HWRBR | ||
331 | #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ | ||
332 | #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ | ||
333 | #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ | ||
334 | #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ | ||
335 | #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ | ||
336 | #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ | ||
337 | #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ | ||
338 | #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ | ||
339 | #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ | ||
340 | #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ | ||
341 | #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ | ||
342 | #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ | ||
343 | #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ | ||
344 | #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ | ||
345 | #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
346 | #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
347 | |||
329 | #define IER_DMAE (1 << 7) /* DMA Requests Enable */ | 348 | #define IER_DMAE (1 << 7) /* DMA Requests Enable */ |
330 | #define IER_UUE (1 << 6) /* UART Unit Enable */ | 349 | #define IER_UUE (1 << 6) /* UART Unit Enable */ |
331 | #define IER_NRZE (1 << 5) /* NRZ coding Enable */ | 350 | #define IER_NRZE (1 << 5) /* NRZ coding Enable */ |
@@ -1013,14 +1032,12 @@ | |||
1013 | #define ICCR0_LBM (1 << 1) /* Loopback mode */ | 1032 | #define ICCR0_LBM (1 << 1) /* Loopback mode */ |
1014 | #define ICCR0_ITR (1 << 0) /* IrDA transmission */ | 1033 | #define ICCR0_ITR (1 << 0) /* IrDA transmission */ |
1015 | 1034 | ||
1016 | #ifdef CONFIG_PXA27x | ||
1017 | #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ | 1035 | #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ |
1018 | #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ | 1036 | #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ |
1019 | #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ | 1037 | #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ |
1020 | #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ | 1038 | #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ |
1021 | #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ | 1039 | #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ |
1022 | #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ | 1040 | #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ |
1023 | #endif | ||
1024 | 1041 | ||
1025 | #ifdef CONFIG_PXA27x | 1042 | #ifdef CONFIG_PXA27x |
1026 | #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ | 1043 | #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ |
@@ -1250,9 +1267,13 @@ | |||
1250 | #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ | 1267 | #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ |
1251 | #define GPIO41_FFRTS 41 /* FFUART request to send */ | 1268 | #define GPIO41_FFRTS 41 /* FFUART request to send */ |
1252 | #define GPIO42_BTRXD 42 /* BTUART receive data */ | 1269 | #define GPIO42_BTRXD 42 /* BTUART receive data */ |
1270 | #define GPIO42_HWRXD 42 /* HWUART receive data */ | ||
1253 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ | 1271 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ |
1272 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ | ||
1254 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ | 1273 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ |
1274 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ | ||
1255 | #define GPIO45_BTRTS 45 /* BTUART request to send */ | 1275 | #define GPIO45_BTRTS 45 /* BTUART request to send */ |
1276 | #define GPIO45_HWRTS 45 /* HWUART request to send */ | ||
1256 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ | 1277 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ |
1257 | #define GPIO46_ICPRXD 46 /* ICP receive data */ | 1278 | #define GPIO46_ICPRXD 46 /* ICP receive data */ |
1258 | #define GPIO46_STRXD 46 /* STD_UART receive data */ | 1279 | #define GPIO46_STRXD 46 /* STD_UART receive data */ |
@@ -1378,17 +1399,26 @@ | |||
1378 | #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) | 1399 | #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) |
1379 | #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) | 1400 | #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) |
1380 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) | 1401 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) |
1402 | #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) | ||
1381 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) | 1403 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) |
1404 | #define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) | ||
1382 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) | 1405 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) |
1406 | #define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) | ||
1383 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) | 1407 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) |
1408 | #define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) | ||
1384 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) | 1409 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) |
1385 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) | 1410 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) |
1386 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) | 1411 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) |
1387 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) | 1412 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) |
1388 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) | 1413 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) |
1389 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | 1414 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) |
1415 | #define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) | ||
1416 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
1417 | #define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) | ||
1390 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) | 1418 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) |
1391 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) | 1419 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) |
1420 | #define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) | ||
1421 | #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) | ||
1392 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) | 1422 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) |
1393 | #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) | 1423 | #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) |
1394 | #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) | 1424 | #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) |
@@ -1763,6 +1793,7 @@ | |||
1763 | #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ | 1793 | #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ |
1764 | #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ | 1794 | #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ |
1765 | #define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ | 1795 | #define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ |
1796 | #define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */ | ||
1766 | #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ | 1797 | #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ |
1767 | #define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ | 1798 | #define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ |
1768 | #define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */ | 1799 | #define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */ |
@@ -2282,4 +2313,11 @@ | |||
2282 | 2313 | ||
2283 | #endif | 2314 | #endif |
2284 | 2315 | ||
2316 | /* PWRMODE register M field values */ | ||
2317 | |||
2318 | #define PWRMODE_IDLE 0x1 | ||
2319 | #define PWRMODE_STANDBY 0x2 | ||
2320 | #define PWRMODE_SLEEP 0x3 | ||
2321 | #define PWRMODE_DEEPSLEEP 0x7 | ||
2322 | |||
2285 | #endif | 2323 | #endif |
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h index 4428d3eb7432..fe38090444e0 100644 --- a/include/asm-arm/arch-pxa/uncompress.h +++ b/include/asm-arm/arch-pxa/uncompress.h | |||
@@ -12,6 +12,7 @@ | |||
12 | #define FFUART ((volatile unsigned long *)0x40100000) | 12 | #define FFUART ((volatile unsigned long *)0x40100000) |
13 | #define BTUART ((volatile unsigned long *)0x40200000) | 13 | #define BTUART ((volatile unsigned long *)0x40200000) |
14 | #define STUART ((volatile unsigned long *)0x40700000) | 14 | #define STUART ((volatile unsigned long *)0x40700000) |
15 | #define HWUART ((volatile unsigned long *)0x41600000) | ||
15 | 16 | ||
16 | #define UART FFUART | 17 | #define UART FFUART |
17 | 18 | ||