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-rw-r--r--include/asm-arm/arch-pxa/akita.h32
-rw-r--r--include/asm-arm/arch-pxa/audio.h17
-rw-r--r--include/asm-arm/arch-pxa/bitfield.h113
-rw-r--r--include/asm-arm/arch-pxa/camera.h48
-rw-r--r--include/asm-arm/arch-pxa/colibri.h19
-rw-r--r--include/asm-arm/arch-pxa/corgi.h109
-rw-r--r--include/asm-arm/arch-pxa/debug-macro.S25
-rw-r--r--include/asm-arm/arch-pxa/dma.h50
-rw-r--r--include/asm-arm/arch-pxa/entry-macro.S57
-rw-r--r--include/asm-arm/arch-pxa/eseries-gpio.h50
-rw-r--r--include/asm-arm/arch-pxa/eseries-irq.h27
-rw-r--r--include/asm-arm/arch-pxa/gpio.h65
-rw-r--r--include/asm-arm/arch-pxa/gumstix.h96
-rw-r--r--include/asm-arm/arch-pxa/hardware.h240
-rw-r--r--include/asm-arm/arch-pxa/i2c.h77
-rw-r--r--include/asm-arm/arch-pxa/idp.h199
-rw-r--r--include/asm-arm/arch-pxa/io.h20
-rw-r--r--include/asm-arm/arch-pxa/irda.h23
-rw-r--r--include/asm-arm/arch-pxa/irqs.h264
-rw-r--r--include/asm-arm/arch-pxa/littleton.h6
-rw-r--r--include/asm-arm/arch-pxa/lpd270.h38
-rw-r--r--include/asm-arm/arch-pxa/lubbock.h40
-rw-r--r--include/asm-arm/arch-pxa/magician.h117
-rw-r--r--include/asm-arm/arch-pxa/mainstone.h120
-rw-r--r--include/asm-arm/arch-pxa/memory.h52
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa25x.h161
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa27x.h433
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa2xx.h133
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa300.h575
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa320.h447
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa3xx.h252
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa930.h491
-rw-r--r--include/asm-arm/arch-pxa/mfp.h319
-rw-r--r--include/asm-arm/arch-pxa/mmc.h23
-rw-r--r--include/asm-arm/arch-pxa/mtd-xip.h37
-rw-r--r--include/asm-arm/arch-pxa/ohci.h20
-rw-r--r--include/asm-arm/arch-pxa/palmtx.h106
-rw-r--r--include/asm-arm/arch-pxa/pcm027.h75
-rw-r--r--include/asm-arm/arch-pxa/pcm990_baseboard.h275
-rw-r--r--include/asm-arm/arch-pxa/pm.h27
-rw-r--r--include/asm-arm/arch-pxa/poodle.h75
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h1070
-rw-r--r--include/asm-arm/arch-pxa/pxa25x-udc.h163
-rw-r--r--include/asm-arm/arch-pxa/pxa27x-udc.h257
-rw-r--r--include/asm-arm/arch-pxa/pxa27x_keypad.h58
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-gpio.h368
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-regs.h246
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx_spi.h46
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h183
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx_nand.h20
-rw-r--r--include/asm-arm/arch-pxa/pxafb.h151
-rw-r--r--include/asm-arm/arch-pxa/regs-lcd.h180
-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h127
-rw-r--r--include/asm-arm/arch-pxa/sharpsl.h34
-rw-r--r--include/asm-arm/arch-pxa/spitz.h158
-rw-r--r--include/asm-arm/arch-pxa/ssp.h83
-rw-r--r--include/asm-arm/arch-pxa/system.h24
-rw-r--r--include/asm-arm/arch-pxa/timex.h26
-rw-r--r--include/asm-arm/arch-pxa/tosa.h198
-rw-r--r--include/asm-arm/arch-pxa/tosa_bt.h22
-rw-r--r--include/asm-arm/arch-pxa/trizeps4.h106
-rw-r--r--include/asm-arm/arch-pxa/udc.h8
-rw-r--r--include/asm-arm/arch-pxa/uncompress.h45
-rw-r--r--include/asm-arm/arch-pxa/vmalloc.h11
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h47
65 files changed, 0 insertions, 8984 deletions
diff --git a/include/asm-arm/arch-pxa/akita.h b/include/asm-arm/arch-pxa/akita.h
deleted file mode 100644
index 5d8cc1d9cb10..000000000000
--- a/include/asm-arm/arch-pxa/akita.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Hardware specific definitions for SL-C1000 (Akita)
3 *
4 * Copyright (c) 2005 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/* Akita IO Expander GPIOs */
13
14#define AKITA_IOEXP_RESERVED_7 (1 << 7)
15#define AKITA_IOEXP_IR_ON (1 << 6)
16#define AKITA_IOEXP_AKIN_PULLUP (1 << 5)
17#define AKITA_IOEXP_BACKLIGHT_CONT (1 << 4)
18#define AKITA_IOEXP_BACKLIGHT_ON (1 << 3)
19#define AKITA_IOEXP_MIC_BIAS (1 << 2)
20#define AKITA_IOEXP_RESERVED_1 (1 << 1)
21#define AKITA_IOEXP_RESERVED_0 (1 << 0)
22
23/* Direction Bitfield 0=output 1=input */
24#define AKITA_IOEXP_IO_DIR 0
25/* Default Values */
26#define AKITA_IOEXP_IO_OUT (AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP)
27
28extern struct platform_device akitaioexp_device;
29
30void akita_set_ioexp(struct device *dev, unsigned char bitmask);
31void akita_reset_ioexp(struct device *dev, unsigned char bitmask);
32
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h
deleted file mode 100644
index f82f96dd1053..000000000000
--- a/include/asm-arm/arch-pxa/audio.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef __ASM_ARCH_AUDIO_H__
2#define __ASM_ARCH_AUDIO_H__
3
4#include <sound/core.h>
5#include <sound/pcm.h>
6
7typedef struct {
8 int (*startup)(struct snd_pcm_substream *, void *);
9 void (*shutdown)(struct snd_pcm_substream *, void *);
10 void (*suspend)(void *);
11 void (*resume)(void *);
12 void *priv;
13} pxa2xx_audio_ops_t;
14
15extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
16
17#endif
diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h
deleted file mode 100644
index f1f0e3387d9c..000000000000
--- a/include/asm-arm/arch-pxa/bitfield.h
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * FILE bitfield.h
3 *
4 * Version 1.1
5 * Author Copyright (c) Marc A. Viredaz, 1998
6 * DEC Western Research Laboratory, Palo Alto, CA
7 * Date April 1998 (April 1997)
8 * System Advanced RISC Machine (ARM)
9 * Language C or ARM Assembly
10 * Purpose Definition of macros to operate on bit fields.
11 */
12
13
14
15#ifndef __BITFIELD_H
16#define __BITFIELD_H
17
18#ifndef __ASSEMBLY__
19#define UData(Data) ((unsigned long) (Data))
20#else
21#define UData(Data) (Data)
22#endif
23
24
25/*
26 * MACRO: Fld
27 *
28 * Purpose
29 * The macro "Fld" encodes a bit field, given its size and its shift value
30 * with respect to bit 0.
31 *
32 * Note
33 * A more intuitive way to encode bit fields would have been to use their
34 * mask. However, extracting size and shift value information from a bit
35 * field's mask is cumbersome and might break the assembler (255-character
36 * line-size limit).
37 *
38 * Input
39 * Size Size of the bit field, in number of bits.
40 * Shft Shift value of the bit field with respect to bit 0.
41 *
42 * Output
43 * Fld Encoded bit field.
44 */
45
46#define Fld(Size, Shft) (((Size) << 16) + (Shft))
47
48
49/*
50 * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
51 *
52 * Purpose
53 * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
54 * the size, shift value, mask, aligned mask, and first bit of a
55 * bit field.
56 *
57 * Input
58 * Field Encoded bit field (using the macro "Fld").
59 *
60 * Output
61 * FSize Size of the bit field, in number of bits.
62 * FShft Shift value of the bit field with respect to bit 0.
63 * FMsk Mask for the bit field.
64 * FAlnMsk Mask for the bit field, aligned on bit 0.
65 * F1stBit First bit of the bit field.
66 */
67
68#define FSize(Field) ((Field) >> 16)
69#define FShft(Field) ((Field) & 0x0000FFFF)
70#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
71#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
72#define F1stBit(Field) (UData (1) << FShft (Field))
73
74
75/*
76 * MACRO: FInsrt
77 *
78 * Purpose
79 * The macro "FInsrt" inserts a value into a bit field by shifting the
80 * former appropriately.
81 *
82 * Input
83 * Value Bit-field value.
84 * Field Encoded bit field (using the macro "Fld").
85 *
86 * Output
87 * FInsrt Bit-field value positioned appropriately.
88 */
89
90#define FInsrt(Value, Field) \
91 (UData (Value) << FShft (Field))
92
93
94/*
95 * MACRO: FExtr
96 *
97 * Purpose
98 * The macro "FExtr" extracts the value of a bit field by masking and
99 * shifting it appropriately.
100 *
101 * Input
102 * Data Data containing the bit-field to be extracted.
103 * Field Encoded bit field (using the macro "Fld").
104 *
105 * Output
106 * FExtr Bit-field value.
107 */
108
109#define FExtr(Data, Field) \
110 ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
111
112
113#endif /* __BITFIELD_H */
diff --git a/include/asm-arm/arch-pxa/camera.h b/include/asm-arm/arch-pxa/camera.h
deleted file mode 100644
index 39516ced8b1f..000000000000
--- a/include/asm-arm/arch-pxa/camera.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 camera.h - PXA camera driver header file
3
4 Copyright (C) 2003, Intel Corporation
5 Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __ASM_ARCH_CAMERA_H_
23#define __ASM_ARCH_CAMERA_H_
24
25#define PXA_CAMERA_MASTER 1
26#define PXA_CAMERA_DATAWIDTH_4 2
27#define PXA_CAMERA_DATAWIDTH_5 4
28#define PXA_CAMERA_DATAWIDTH_8 8
29#define PXA_CAMERA_DATAWIDTH_9 0x10
30#define PXA_CAMERA_DATAWIDTH_10 0x20
31#define PXA_CAMERA_PCLK_EN 0x40
32#define PXA_CAMERA_MCLK_EN 0x80
33#define PXA_CAMERA_PCP 0x100
34#define PXA_CAMERA_HSP 0x200
35#define PXA_CAMERA_VSP 0x400
36
37struct pxacamera_platform_data {
38 int (*init)(struct device *);
39 int (*power)(struct device *, int);
40 int (*reset)(struct device *, int);
41
42 unsigned long flags;
43 unsigned long mclk_10khz;
44};
45
46extern void pxa_set_camera_info(struct pxacamera_platform_data *);
47
48#endif /* __ASM_ARCH_CAMERA_H_ */
diff --git a/include/asm-arm/arch-pxa/colibri.h b/include/asm-arm/arch-pxa/colibri.h
deleted file mode 100644
index 2ae373fb5675..000000000000
--- a/include/asm-arm/arch-pxa/colibri.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef _COLIBRI_H_
2#define _COLIBRI_H_
3
4/* physical memory regions */
5#define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
6#define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
7#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */
8
9/* virtual memory regions */
10#define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */
11
12/* size of flash */
13#define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
14
15/* Ethernet Controller Davicom DM9000 */
16#define GPIO_DM9000 114
17#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
18
19#endif /* _COLIBRI_H_ */
diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h
deleted file mode 100644
index bf856503baf6..000000000000
--- a/include/asm-arm/arch-pxa/corgi.h
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Hardware specific definitions for SL-C7xx series of PDAs
3 *
4 * Copyright (c) 2004-2005 Richard Purdie
5 *
6 * Based on Sharp's 2.4 kernel patches
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#ifndef __ASM_ARCH_CORGI_H
14#define __ASM_ARCH_CORGI_H 1
15
16
17/*
18 * Corgi (Non Standard) GPIO Definitions
19 */
20#define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */
21#define CORGI_GPIO_AC_IN (1) /* Charger Detection */
22#define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */
23#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */
24#define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */
25#define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */
26#define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */
27#define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */
28#define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */
29#define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */
30#define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */
31#define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */
32#define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */
33#define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */
34#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */
35#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */
36#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */
37#define CORGI_GPIO_IR_ON (22) /* Enable IR Transciever */
38#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */
39#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */
40#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */
41#define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */
42#define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */
43#define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */
44#define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */
45
46
47/*
48 * Corgi Keyboard Definitions
49 */
50#define CORGI_KEY_STROBE_NUM (12)
51#define CORGI_KEY_SENSE_NUM (8)
52#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc)
53#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000)
54#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26)
55#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003)
56#define CORGI_GPIO_LOW_SENSE_LSHIFT (6)
57#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a))
58#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a))
59#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0)
60#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000)
61#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f)
62#define CORGI_GPIO_KEY_SENSE(a) (58+(a))
63#define CORGI_GPIO_KEY_STROBE(a) (66+(a))
64
65
66/*
67 * Corgi Interrupts
68 */
69#define CORGI_IRQ_GPIO_KEY_INT IRQ_GPIO(0)
70#define CORGI_IRQ_GPIO_AC_IN IRQ_GPIO(1)
71#define CORGI_IRQ_GPIO_WAKEUP IRQ_GPIO(3)
72#define CORGI_IRQ_GPIO_AK_INT IRQ_GPIO(4)
73#define CORGI_IRQ_GPIO_TP_INT IRQ_GPIO(5)
74#define CORGI_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9)
75#define CORGI_IRQ_GPIO_nSD_INT IRQ_GPIO(10)
76#define CORGI_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(11)
77#define CORGI_IRQ_GPIO_CF_CD IRQ_GPIO(14)
78#define CORGI_IRQ_GPIO_CHRG_FULL IRQ_GPIO(16) /* Battery fully charged */
79#define CORGI_IRQ_GPIO_CF_IRQ IRQ_GPIO(17)
80#define CORGI_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(58+(a)) /* Keyboard Sense lines */
81
82
83/*
84 * Corgi SCOOP GPIOs and Config
85 */
86#define CORGI_SCP_LED_GREEN SCOOP_GPCR_PA11
87#define CORGI_SCP_SWA SCOOP_GPCR_PA12 /* Hinge Switch A */
88#define CORGI_SCP_SWB SCOOP_GPCR_PA13 /* Hinge Switch B */
89#define CORGI_SCP_MUTE_L SCOOP_GPCR_PA14
90#define CORGI_SCP_MUTE_R SCOOP_GPCR_PA15
91#define CORGI_SCP_AKIN_PULLUP SCOOP_GPCR_PA16
92#define CORGI_SCP_APM_ON SCOOP_GPCR_PA17
93#define CORGI_SCP_BACKLIGHT_CONT SCOOP_GPCR_PA18
94#define CORGI_SCP_MIC_BIAS SCOOP_GPCR_PA19
95
96#define CORGI_SCOOP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \
97 CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \
98 CORGI_SCP_MIC_BIAS )
99#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
100
101
102/*
103 * Shared data structures
104 */
105extern struct platform_device corgiscoop_device;
106extern struct platform_device corgissp_device;
107
108#endif /* __ASM_ARCH_CORGI_H */
109
diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S
deleted file mode 100644
index 9012cbc0ad8b..000000000000
--- a/include/asm-arm/arch-pxa/debug-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
1/* linux/include/asm-arm/arch-pxa/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include "hardware.h"
15
16 .macro addruart,rx
17 mrc p15, 0, \rx, c1, c0
18 tst \rx, #1 @ MMU enabled?
19 moveq \rx, #0x40000000 @ physical
20 movne \rx, #io_p2v(0x40000000) @ virtual
21 orr \rx, \rx, #0x00100000
22 .endm
23
24#define UART_SHIFT 2
25#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
deleted file mode 100644
index dbe110ee2666..000000000000
--- a/include/asm-arm/arch-pxa/dma.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/dma.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#ifndef __ASM_ARCH_DMA_H
13#define __ASM_ARCH_DMA_H
14
15/*
16 * Descriptor structure for PXA's DMA engine
17 * Note: this structure must always be aligned to a 16-byte boundary.
18 */
19
20typedef struct pxa_dma_desc {
21 volatile u32 ddadr; /* Points to the next descriptor + flags */
22 volatile u32 dsadr; /* DSADR value for the current transfer */
23 volatile u32 dtadr; /* DTADR value for the current transfer */
24 volatile u32 dcmd; /* DCMD value for the current transfer */
25} pxa_dma_desc;
26
27typedef enum {
28 DMA_PRIO_HIGH = 0,
29 DMA_PRIO_MEDIUM = 1,
30 DMA_PRIO_LOW = 2
31} pxa_dma_prio;
32
33#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
34#define HAVE_ARCH_PCI_SET_DMA_MASK 1
35#endif
36
37/*
38 * DMA registration
39 */
40
41int __init pxa_init_dma(int num_ch);
42
43int pxa_request_dma (char *name,
44 pxa_dma_prio prio,
45 void (*irq_handler)(int, void *),
46 void *data);
47
48void pxa_free_dma (int dma_ch);
49
50#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S
deleted file mode 100644
index 897d164da223..000000000000
--- a/include/asm-arm/arch-pxa/entry-macro.S
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * include/asm-arm/arch-pxa/entry-macro.S
3 *
4 * Low-level IRQ helper macros for PXA-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <asm/arch/hardware.h>
11#include <asm/arch/irqs.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro get_irqnr_preamble, base, tmp
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23 mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
24 mov \tmp, \tmp, lsr #13
25 and \tmp, \tmp, #0x7 @ Core G
26 cmp \tmp, #1
27 bhi 1004f
28
29 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
30 add \base, \base, #0x00d00000
31 ldr \irqstat, [\base, #0] @ ICIP
32 ldr \irqnr, [\base, #4] @ ICMR
33 b 1002f
34
351004:
36 mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2
37 mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2
38 ands \irqnr, \irqstat, \irqnr
39 beq 1003f
40 rsb \irqstat, \irqnr, #0
41 and \irqstat, \irqstat, \irqnr
42 clz \irqnr, \irqstat
43 rsb \irqnr, \irqnr, #31
44 add \irqnr, \irqnr, #32
45 b 1001f
461003:
47 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
48 mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
491002:
50 ands \irqnr, \irqstat, \irqnr
51 beq 1001f
52 rsb \irqstat, \irqnr, #0
53 and \irqstat, \irqstat, \irqnr
54 clz \irqnr, \irqstat
55 rsb \irqnr, \irqnr, #31
561001:
57 .endm
diff --git a/include/asm-arm/arch-pxa/eseries-gpio.h b/include/asm-arm/arch-pxa/eseries-gpio.h
deleted file mode 100644
index 4c90b1310270..000000000000
--- a/include/asm-arm/arch-pxa/eseries-gpio.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * eseries-gpio.h
3 *
4 * Copyright (C) Ian Molton <spyro@f2s.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/* e-series power button */
13#define GPIO_ESERIES_POWERBTN 0
14
15/* UDC GPIO definitions */
16#define GPIO_E7XX_USB_DISC 13
17#define GPIO_E7XX_USB_PULLUP 3
18
19#define GPIO_E800_USB_DISC 4
20#define GPIO_E800_USB_PULLUP 84
21
22/* e740 PCMCIA GPIO definitions */
23/* Note: PWR1 seems to be inverted */
24#define GPIO_E740_PCMCIA_CD0 8
25#define GPIO_E740_PCMCIA_CD1 44
26#define GPIO_E740_PCMCIA_RDY0 11
27#define GPIO_E740_PCMCIA_RDY1 6
28#define GPIO_E740_PCMCIA_RST0 27
29#define GPIO_E740_PCMCIA_RST1 24
30#define GPIO_E740_PCMCIA_PWR0 20
31#define GPIO_E740_PCMCIA_PWR1 23
32
33/* e750 PCMCIA GPIO definitions */
34#define GPIO_E750_PCMCIA_CD0 8
35#define GPIO_E750_PCMCIA_RDY0 12
36#define GPIO_E750_PCMCIA_RST0 27
37#define GPIO_E750_PCMCIA_PWR0 20
38
39/* e800 PCMCIA GPIO definitions */
40#define GPIO_E800_PCMCIA_RST0 69
41#define GPIO_E800_PCMCIA_RST1 72
42#define GPIO_E800_PCMCIA_PWR0 20
43#define GPIO_E800_PCMCIA_PWR1 73
44
45/* e7xx IrDA power control */
46#define GPIO_E7XX_IR_ON 38
47
48/* ASIC related GPIOs */
49#define GPIO_ESERIES_TMIO_IRQ 5
50#define GPIO_E800_ANGELX_IRQ 8
diff --git a/include/asm-arm/arch-pxa/eseries-irq.h b/include/asm-arm/arch-pxa/eseries-irq.h
deleted file mode 100644
index f2a93d5e31d3..000000000000
--- a/include/asm-arm/arch-pxa/eseries-irq.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * eseries-irq.h
3 *
4 * Copyright (C) Ian Molton <spyro@f2s.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8)
13#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n))
14
15#define ANGELX_RDY0_IRQ IRQ_ANGELX(0)
16#define ANGELX_ST0_IRQ IRQ_ANGELX(1)
17#define ANGELX_CD0_IRQ IRQ_ANGELX(2)
18#define ANGELX_RDY1_IRQ IRQ_ANGELX(3)
19#define ANGELX_ST1_IRQ IRQ_ANGELX(4)
20#define ANGELX_CD1_IRQ IRQ_ANGELX(5)
21
22#define TMIO_IRQ_BASE (IRQ_BOARD_START+0)
23#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n))
24
25#define TMIO_SD_IRQ IRQ_TMIO(1)
26#define TMIO_USB_IRQ IRQ_TMIO(2)
27
diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h
deleted file mode 100644
index 2c1e3d8ad7a2..000000000000
--- a/include/asm-arm/arch-pxa/gpio.h
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/gpio.h
3 *
4 * PXA GPIO wrappers for arch-neutral GPIO calls
5 *
6 * Written by Philipp Zabel <philipp.zabel@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __ASM_ARCH_PXA_GPIO_H
25#define __ASM_ARCH_PXA_GPIO_H
26
27#include <asm/arch/pxa-regs.h>
28#include <asm/irq.h>
29#include <asm/arch/hardware.h>
30
31#include <asm-generic/gpio.h>
32
33
34/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
35 * Those cases currently cause holes in the GPIO number space.
36 */
37#define NR_BUILTIN_GPIO 128
38
39static inline int gpio_get_value(unsigned gpio)
40{
41 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
42 return GPLR(gpio) & GPIO_bit(gpio);
43 else
44 return __gpio_get_value(gpio);
45}
46
47static inline void gpio_set_value(unsigned gpio, int value)
48{
49 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
50 if (value)
51 GPSR(gpio) = GPIO_bit(gpio);
52 else
53 GPCR(gpio) = GPIO_bit(gpio);
54 } else {
55 __gpio_set_value(gpio, value);
56 }
57}
58
59#define gpio_cansleep __gpio_cansleep
60
61#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
62#define irq_to_gpio(irq) IRQ_TO_GPIO(irq)
63
64
65#endif
diff --git a/include/asm-arm/arch-pxa/gumstix.h b/include/asm-arm/arch-pxa/gumstix.h
deleted file mode 100644
index 6fa85c4f94f8..000000000000
--- a/include/asm-arm/arch-pxa/gumstix.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/gumstix.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9
10/* BTRESET - Reset line to Bluetooth module, active low signal. */
11#define GPIO_GUMSTIX_BTRESET 7
12#define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT)
13
14
15/*
16GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
17interrupt signal for determining cable presence. On the original gumstix,
18this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F,
19this moves to GPIO17 and GPIO37. */
20
21/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
22has detected a cable insertion; driven low otherwise. */
23
24#ifdef CONFIG_ARCH_GUMSTIX_ORIG
25
26#define GPIO_GUMSTIX_USB_GPIOn 81
27#define GPIO_GUMSTIX_USB_GPIOx 83
28
29#else
30
31#define GPIO_GUMSTIX_USB_GPIOn 35
32#define GPIO_GUMSTIX_USB_GPIOx 41
33
34#endif
35
36/* usb state change */
37#define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn)
38
39#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
40#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
41#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN)
42
43/*
44 * SD/MMC definitions
45 */
46#define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */
47#define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */
48#define GUMSTIX_IRQ_GPIO_nSD_DETECT IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT)
49
50/*
51 * SMC Ethernet definitions
52 * ETH_RST provides a hardware reset line to the ethernet chip
53 * ETH is the IRQ line in from the ethernet chip to the PXA
54 */
55#define GPIO_GUMSTIX_ETH0_RST 80
56#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
57#define GPIO_GUMSTIX_ETH1_RST 52
58#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
59
60#define GPIO_GUMSTIX_ETH0 36
61#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN)
62#define GUMSTIX_ETH0_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH0)
63#define GPIO_GUMSTIX_ETH1 27
64#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN)
65#define GUMSTIX_ETH1_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH1)
66
67
68/* CF reset line */
69#define GPIO8_RESET 8
70
71/* CF slot 0 */
72#define GPIO4_nBVD1 4
73#define GPIO4_nSTSCHG GPIO4_nBVD1
74#define GPIO11_nCD 11
75#define GPIO26_PRDY_nBSY 26
76#define GUMSTIX_S0_nSTSCHG_IRQ IRQ_GPIO(GPIO4_nSTSCHG)
77#define GUMSTIX_S0_nCD_IRQ IRQ_GPIO(GPIO11_nCD)
78#define GUMSTIX_S0_PRDY_nBSY_IRQ IRQ_GPIO(GPIO26_PRDY_nBSY)
79
80/* CF slot 1 */
81#define GPIO18_nBVD1 18
82#define GPIO18_nSTSCHG GPIO18_nBVD1
83#define GPIO36_nCD 36
84#define GPIO27_PRDY_nBSY 27
85#define GUMSTIX_S1_nSTSCHG_IRQ IRQ_GPIO(GPIO18_nSTSCHG)
86#define GUMSTIX_S1_nCD_IRQ IRQ_GPIO(GPIO36_nCD)
87#define GUMSTIX_S1_PRDY_nBSY_IRQ IRQ_GPIO(GPIO27_PRDY_nBSY)
88
89/* CF GPIO line modes */
90#define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN)
91#define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT)
92#define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN)
93#define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN)
94#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN)
95#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN)
96#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN)
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
deleted file mode 100644
index 979a45695d7d..000000000000
--- a/include/asm-arm/arch-pxa/hardware.h
+++ /dev/null
@@ -1,240 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/hardware.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H
15
16/*
17 * We requires absolute addresses.
18 */
19#define PCIO_BASE 0
20
21/*
22 * Workarounds for at least 2 errata so far require this.
23 * The mapping is set in mach-pxa/generic.c.
24 */
25#define UNCACHED_PHYS_0 0xff000000
26#define UNCACHED_ADDR UNCACHED_PHYS_0
27
28/*
29 * Intel PXA2xx internal register mapping:
30 *
31 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
32 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
33 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
34 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
35 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
36 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
37 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
38 *
39 * Note that not all PXA2xx chips implement all those addresses, and the
40 * kernel only maps the minimum needed range of this mapping.
41 */
42#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
43#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
44
45#ifndef __ASSEMBLY__
46
47# define __REG(x) (*((volatile u32 *)io_p2v(x)))
48
49/* With indexed regs we don't want to feed the index through io_p2v()
50 especially if it is a variable, otherwise horrible code will result. */
51# define __REG2(x,y) \
52 (*(volatile u32 *)((u32)&__REG(x) + (y)))
53
54# define __PREG(x) (io_v2p((u32)&(x)))
55
56#else
57
58# define __REG(x) io_p2v(x)
59# define __PREG(x) io_v2p(x)
60
61#endif
62
63#ifndef __ASSEMBLY__
64
65#ifdef CONFIG_PXA25x
66#define __cpu_is_pxa21x(id) \
67 ({ \
68 unsigned int _id = (id) >> 4 & 0xf3f; \
69 _id == 0x212; \
70 })
71
72#define __cpu_is_pxa255(id) \
73 ({ \
74 unsigned int _id = (id) >> 4 & 0xfff; \
75 _id == 0x2d0; \
76 })
77
78#define __cpu_is_pxa25x(id) \
79 ({ \
80 unsigned int _id = (id) >> 4 & 0xfff; \
81 _id == 0x2d0 || _id == 0x290; \
82 })
83#else
84#define __cpu_is_pxa21x(id) (0)
85#define __cpu_is_pxa255(id) (0)
86#define __cpu_is_pxa25x(id) (0)
87#endif
88
89#ifdef CONFIG_PXA27x
90#define __cpu_is_pxa27x(id) \
91 ({ \
92 unsigned int _id = (id) >> 4 & 0xfff; \
93 _id == 0x411; \
94 })
95#else
96#define __cpu_is_pxa27x(id) (0)
97#endif
98
99#ifdef CONFIG_CPU_PXA300
100#define __cpu_is_pxa300(id) \
101 ({ \
102 unsigned int _id = (id) >> 4 & 0xfff; \
103 _id == 0x688; \
104 })
105#else
106#define __cpu_is_pxa300(id) (0)
107#endif
108
109#ifdef CONFIG_CPU_PXA310
110#define __cpu_is_pxa310(id) \
111 ({ \
112 unsigned int _id = (id) >> 4 & 0xfff; \
113 _id == 0x689; \
114 })
115#else
116#define __cpu_is_pxa310(id) (0)
117#endif
118
119#ifdef CONFIG_CPU_PXA320
120#define __cpu_is_pxa320(id) \
121 ({ \
122 unsigned int _id = (id) >> 4 & 0xfff; \
123 _id == 0x603 || _id == 0x682; \
124 })
125#else
126#define __cpu_is_pxa320(id) (0)
127#endif
128
129#ifdef CONFIG_CPU_PXA930
130#define __cpu_is_pxa930(id) \
131 ({ \
132 unsigned int _id = (id) >> 4 & 0xfff; \
133 _id == 0x683; \
134 })
135#else
136#define __cpu_is_pxa930(id) (0)
137#endif
138
139#define cpu_is_pxa21x() \
140 ({ \
141 __cpu_is_pxa21x(read_cpuid_id()); \
142 })
143
144#define cpu_is_pxa255() \
145 ({ \
146 __cpu_is_pxa255(read_cpuid_id()); \
147 })
148
149#define cpu_is_pxa25x() \
150 ({ \
151 __cpu_is_pxa25x(read_cpuid_id()); \
152 })
153
154#define cpu_is_pxa27x() \
155 ({ \
156 __cpu_is_pxa27x(read_cpuid_id()); \
157 })
158
159#define cpu_is_pxa300() \
160 ({ \
161 __cpu_is_pxa300(read_cpuid_id()); \
162 })
163
164#define cpu_is_pxa310() \
165 ({ \
166 __cpu_is_pxa310(read_cpuid_id()); \
167 })
168
169#define cpu_is_pxa320() \
170 ({ \
171 __cpu_is_pxa320(read_cpuid_id()); \
172 })
173
174#define cpu_is_pxa930() \
175 ({ \
176 unsigned int id = read_cpuid(CPUID_ID); \
177 __cpu_is_pxa930(id); \
178 })
179
180/*
181 * CPUID Core Generation Bit
182 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
183 * == 0x3 for pxa300/pxa310/pxa320
184 */
185#define __cpu_is_pxa2xx(id) \
186 ({ \
187 unsigned int _id = (id) >> 13 & 0x7; \
188 _id <= 0x2; \
189 })
190
191#define __cpu_is_pxa3xx(id) \
192 ({ \
193 unsigned int _id = (id) >> 13 & 0x7; \
194 _id == 0x3; \
195 })
196
197#define cpu_is_pxa2xx() \
198 ({ \
199 __cpu_is_pxa2xx(read_cpuid_id()); \
200 })
201
202#define cpu_is_pxa3xx() \
203 ({ \
204 __cpu_is_pxa3xx(read_cpuid_id()); \
205 })
206
207/*
208 * Handy routine to set GPIO alternate functions
209 */
210extern int pxa_gpio_mode( int gpio_mode );
211
212/*
213 * Return GPIO level, nonzero means high, zero is low
214 */
215extern int pxa_gpio_get_value(unsigned gpio);
216
217/*
218 * Set output GPIO level
219 */
220extern void pxa_gpio_set_value(unsigned gpio, int value);
221
222/*
223 * return current memory and LCD clock frequency in units of 10kHz
224 */
225extern unsigned int get_memclk_frequency_10khz(void);
226
227/*
228 * register GPIO as reset generator
229 */
230extern int init_gpio_reset(int gpio);
231
232#endif
233
234#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
235#define PCIBIOS_MIN_IO 0
236#define PCIBIOS_MIN_MEM 0
237#define pcibios_assign_all_busses() 1
238#endif
239
240#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-pxa/i2c.h b/include/asm-arm/arch-pxa/i2c.h
deleted file mode 100644
index 80596b013443..000000000000
--- a/include/asm-arm/arch-pxa/i2c.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * i2c_pxa.h
3 *
4 * Copyright (C) 2002 Intrinsyc Software Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#ifndef _I2C_PXA_H_
12#define _I2C_PXA_H_
13
14#if 0
15#define DEF_TIMEOUT 3
16#else
17/* need a longer timeout if we're dealing with the fact we may well be
18 * looking at a multi-master environment
19*/
20#define DEF_TIMEOUT 32
21#endif
22
23#define BUS_ERROR (-EREMOTEIO)
24#define XFER_NAKED (-ECONNREFUSED)
25#define I2C_RETRY (-2000) /* an error has occurred retry transmit */
26
27/* ICR initialize bit values
28*
29* 15. FM 0 (100 Khz operation)
30* 14. UR 0 (No unit reset)
31* 13. SADIE 0 (Disables the unit from interrupting on slave addresses
32* matching its slave address)
33* 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration
34* in master mode)
35* 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
36* 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
37* 9. IRFIE 1 (Enable interrupts from full buffer received)
38* 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
39* 7. GCD 1 (Disables i2c unit response to general call messages as a slave)
40* 6. IUE 0 (Disable unit until we change settings)
41* 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
42* 4. MA 0 (Only send stop with the ICR stop bit)
43* 3. TB 0 (We are not transmitting a byte initially)
44* 2. ACKNAK 0 (Send an ACK after the unit receives a byte)
45* 1. STOP 0 (Do not send a STOP)
46* 0. START 0 (Do not send a START)
47*
48*/
49#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
50
51/* I2C status register init values
52 *
53 * 10. BED 1 (Clear bus error detected)
54 * 9. SAD 1 (Clear slave address detected)
55 * 7. IRF 1 (Clear IDBR Receive Full)
56 * 6. ITE 1 (Clear IDBR Transmit Empty)
57 * 5. ALD 1 (Clear Arbitration Loss Detected)
58 * 4. SSD 1 (Clear Slave Stop Detected)
59 */
60#define I2C_ISR_INIT 0x7FF /* status register init */
61
62struct i2c_slave_client;
63
64struct i2c_pxa_platform_data {
65 unsigned int slave_addr;
66 struct i2c_slave_client *slave;
67 unsigned int class;
68 int use_pio;
69};
70
71extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
72
73#ifdef CONFIG_PXA27x
74extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info);
75#endif
76
77#endif
diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h
deleted file mode 100644
index 21aa8ac35c1c..000000000000
--- a/include/asm-arm/arch-pxa/idp.h
+++ /dev/null
@@ -1,199 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/idp.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
9 *
10 * 2001-09-13: Cliff Brake <cbrake@accelent.com>
11 * Initial code
12 *
13 * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
14 * <http://www.vibren.com> <http://bec-systems.com>
15 * Changes for 2.6 kernel.
16 */
17
18
19/*
20 * Note: this file must be safe to include in assembly files
21 *
22 * Support for the Vibren PXA255 IDP requires rev04 or later
23 * IDP hardware.
24 */
25
26
27#define IDP_FLASH_PHYS (PXA_CS0_PHYS)
28#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
29#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
30#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
31#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
32#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
33#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
34
35
36/*
37 * virtual memory map
38 */
39
40#define IDP_COREVOLT_VIRT (0xf0000000)
41#define IDP_COREVOLT_SIZE (1*1024*1024)
42
43#define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
44#define IDP_CPLD_SIZE (1*1024*1024)
45
46#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
47#error Your custom IO space is getting a bit large !!
48#endif
49
50#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
51#define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
52
53#ifndef __ASSEMBLY__
54# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
55#else
56# define __CPLD_REG(x) CPLD_P2V(x)
57#endif
58
59/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
60
61#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
62#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
63#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
64#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
65#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
66#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
67#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
68#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
69#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
70#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
71#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28)
72#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C)
73#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30)
74#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34)
75
76#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50)
77#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54)
78#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58)
79#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C)
80
81/* FPGA register virtual addresses */
82
83#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV)
84#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
85#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL)
86#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
87#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
88#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN)
89#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
90#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
91#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
92#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
93#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
94#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL)
95#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD)
96#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE)
97
98#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW)
99#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
100#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
101#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS)
102
103
104/*
105 * Bit masks for various registers
106 */
107
108// IDP_CPLD_PCCARD_PWR
109#define PCC0_PWR0 (1 << 0)
110#define PCC0_PWR1 (1 << 1)
111#define PCC0_PWR2 (1 << 2)
112#define PCC0_PWR3 (1 << 3)
113#define PCC1_PWR0 (1 << 4)
114#define PCC1_PWR1 (1 << 5)
115#define PCC1_PWR2 (1 << 6)
116#define PCC1_PWR3 (1 << 7)
117
118// IDP_CPLD_PCCARD_EN
119#define PCC0_RESET (1 << 6)
120#define PCC1_RESET (1 << 7)
121#define PCC0_ENABLE (1 << 0)
122#define PCC1_ENABLE (1 << 1)
123
124// IDP_CPLD_PCCARDx_STATUS
125#define _PCC_WRPROT (1 << 7) // 7-4 read as low true
126#define _PCC_RESET (1 << 6)
127#define _PCC_IRQ (1 << 5)
128#define _PCC_INPACK (1 << 4)
129#define PCC_BVD2 (1 << 3)
130#define PCC_BVD1 (1 << 2)
131#define PCC_VS2 (1 << 1)
132#define PCC_VS1 (1 << 0)
133
134#define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
135
136/* A listing of interrupts used by external hardware devices */
137
138#define TOUCH_PANEL_IRQ IRQ_GPIO(5)
139#define IDE_IRQ IRQ_GPIO(21)
140
141#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
142
143#define ETHERNET_IRQ IRQ_GPIO(4)
144#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING
145
146#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
147
148#define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
149#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
150
151#define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
152#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
153
154#define PCMCIA_S0_RDYINT IRQ_GPIO(19)
155#define PCMCIA_S1_RDYINT IRQ_GPIO(22)
156
157
158/*
159 * Macros for LED Driver
160 */
161
162/* leds 0 = ON */
163#define IDP_HB_LED (1<<5)
164#define IDP_BUSY_LED (1<<6)
165
166#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
167
168/*
169 * macros for MTD driver
170 */
171
172#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1))
173#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1))
174
175/*
176 * macros for matrix keyboard driver
177 */
178
179#define KEYBD_MATRIX_NUMBER_INPUTS 7
180#define KEYBD_MATRIX_NUMBER_OUTPUTS 14
181
182#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE
183#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE
184
185#define KEYBD_MATRIX_SETTLING_TIME_US 100
186#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2
187
188#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
189{\
190 IDP_CPLD_KB_COL_LOW = outputs;\
191 IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
192}
193
194#define KEYBD_MATRIX_GET_INPUTS(inputs) \
195{\
196 inputs = (IDP_CPLD_KB_ROW & 0x7f);\
197}
198
199
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h
deleted file mode 100644
index af34e0f2f7dc..000000000000
--- a/include/asm-arm/arch-pxa/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/io.h
3 *
4 * Copied from asm/arch/sa1100/io.h
5 */
6#ifndef __ASM_ARM_ARCH_IO_H
7#define __ASM_ARM_ARCH_IO_H
8
9#include <asm/arch/hardware.h>
10
11#define IO_SPACE_LIMIT 0xffffffff
12
13/*
14 * We don't actually have real ISA nor PCI buses, but there is so many
15 * drivers out there that might just work if we fake them...
16 */
17#define __io(a) ((void __iomem *)(a))
18#define __mem_pci(a) (a)
19
20#endif
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
deleted file mode 100644
index 0a50c3c763df..000000000000
--- a/include/asm-arm/arch-pxa/irda.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#ifndef ASMARM_ARCH_IRDA_H
2#define ASMARM_ARCH_IRDA_H
3
4/* board specific transceiver capabilities */
5
6#define IR_OFF 1
7#define IR_SIRMODE 2
8#define IR_FIRMODE 4
9
10struct pxaficp_platform_data {
11 int transceiver_cap;
12 void (*transceiver_mode)(struct device *dev, int mode);
13 int (*startup)(struct device *dev);
14 void (*shutdown)(struct device *dev);
15};
16
17extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
18
19#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
20void pxa2xx_transceiver_mode(struct device *dev, int mode);
21#endif
22
23#endif
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
deleted file mode 100644
index 9413121b0ed9..000000000000
--- a/include/asm-arm/arch-pxa/irqs.h
+++ /dev/null
@@ -1,264 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/irqs.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13
14#define PXA_IRQ(x) (x)
15
16#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
17#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
18#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
19#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
20#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */
21#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
22#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
23#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
24#endif
25
26#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
27#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
28#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
29#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */
30#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
31#define IRQ_USB PXA_IRQ(11) /* USB Service */
32#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
33#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */
34#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
35#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
36#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
37#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */
38#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */
39#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
40#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
41#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
42#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
43#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
44#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
45#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */
46#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */
47#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */
48#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */
49#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */
50#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */
51#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */
52#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
53#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
54
55#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
56#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
57#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
58#endif
59
60#ifdef CONFIG_PXA3xx
61#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */
62#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
63#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
64#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
65#define IRQ_GRPHICS PXA_IRQ(39) /* Graphics Controller */
66#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */
67#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */
68#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */
69#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */
70#define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */
71#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */
72#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */
73#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
74#endif
75
76#define PXA_GPIO_IRQ_BASE (64)
77#define PXA_GPIO_IRQ_NUM (128)
78
79#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
80#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
81
82#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
83#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
84
85/*
86 * The next 16 interrupts are for board specific purposes. Since
87 * the kernel can only run on one machine at a time, we can re-use
88 * these. If you need more, increase IRQ_BOARD_END, but keep it
89 * within sensible limits.
90 */
91#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
92#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
93
94#define IRQ_SA1111_START (IRQ_BOARD_END)
95#define IRQ_GPAIN0 (IRQ_BOARD_END + 0)
96#define IRQ_GPAIN1 (IRQ_BOARD_END + 1)
97#define IRQ_GPAIN2 (IRQ_BOARD_END + 2)
98#define IRQ_GPAIN3 (IRQ_BOARD_END + 3)
99#define IRQ_GPBIN0 (IRQ_BOARD_END + 4)
100#define IRQ_GPBIN1 (IRQ_BOARD_END + 5)
101#define IRQ_GPBIN2 (IRQ_BOARD_END + 6)
102#define IRQ_GPBIN3 (IRQ_BOARD_END + 7)
103#define IRQ_GPBIN4 (IRQ_BOARD_END + 8)
104#define IRQ_GPBIN5 (IRQ_BOARD_END + 9)
105#define IRQ_GPCIN0 (IRQ_BOARD_END + 10)
106#define IRQ_GPCIN1 (IRQ_BOARD_END + 11)
107#define IRQ_GPCIN2 (IRQ_BOARD_END + 12)
108#define IRQ_GPCIN3 (IRQ_BOARD_END + 13)
109#define IRQ_GPCIN4 (IRQ_BOARD_END + 14)
110#define IRQ_GPCIN5 (IRQ_BOARD_END + 15)
111#define IRQ_GPCIN6 (IRQ_BOARD_END + 16)
112#define IRQ_GPCIN7 (IRQ_BOARD_END + 17)
113#define IRQ_MSTXINT (IRQ_BOARD_END + 18)
114#define IRQ_MSRXINT (IRQ_BOARD_END + 19)
115#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20)
116#define IRQ_TPTXINT (IRQ_BOARD_END + 21)
117#define IRQ_TPRXINT (IRQ_BOARD_END + 22)
118#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23)
119#define SSPXMTINT (IRQ_BOARD_END + 24)
120#define SSPRCVINT (IRQ_BOARD_END + 25)
121#define SSPROR (IRQ_BOARD_END + 26)
122#define AUDXMTDMADONEA (IRQ_BOARD_END + 32)
123#define AUDRCVDMADONEA (IRQ_BOARD_END + 33)
124#define AUDXMTDMADONEB (IRQ_BOARD_END + 34)
125#define AUDRCVDMADONEB (IRQ_BOARD_END + 35)
126#define AUDTFSR (IRQ_BOARD_END + 36)
127#define AUDRFSR (IRQ_BOARD_END + 37)
128#define AUDTUR (IRQ_BOARD_END + 38)
129#define AUDROR (IRQ_BOARD_END + 39)
130#define AUDDTS (IRQ_BOARD_END + 40)
131#define AUDRDD (IRQ_BOARD_END + 41)
132#define AUDSTO (IRQ_BOARD_END + 42)
133#define IRQ_USBPWR (IRQ_BOARD_END + 43)
134#define IRQ_HCIM (IRQ_BOARD_END + 44)
135#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45)
136#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46)
137#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47)
138#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48)
139#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49)
140#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50)
141#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51)
142#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52)
143#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53)
144#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54)
145
146#define IRQ_LOCOMO_START (IRQ_BOARD_END)
147#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0)
148#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1)
149#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2)
150#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3)
151#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4)
152#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5)
153#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6)
154#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7)
155#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8)
156#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9)
157#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10)
158#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11)
159#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12)
160#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13)
161#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14)
162#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15)
163#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16)
164#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17)
165#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18)
166#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19)
167#define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20)
168#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21)
169
170/*
171 * Figure out the MAX IRQ number.
172 *
173 * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
174 * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
175 * Otherwise, we have the standard IRQs only.
176 */
177#ifdef CONFIG_SA1111
178#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1)
179#elif defined(CONFIG_SHARP_LOCOMO)
180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
181#elif defined(CONFIG_ARCH_LUBBOCK) || \
182 defined(CONFIG_MACH_LOGICPD_PXA270) || \
183 defined(CONFIG_MACH_TOSA) || \
184 defined(CONFIG_MACH_MAINSTONE) || \
185 defined(CONFIG_MACH_PCM027) || \
186 defined(CONFIG_MACH_MAGICIAN)
187#define NR_IRQS (IRQ_BOARD_END)
188#elif defined(CONFIG_MACH_ZYLONITE)
189#define NR_IRQS (IRQ_BOARD_START + 32)
190#else
191#define NR_IRQS (IRQ_BOARD_START)
192#endif
193
194/*
195 * Board specific IRQs. Define them here.
196 * Do not surround them with ifdefs.
197 */
198#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x))
199#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
200#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
201#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
202#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3)
203#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4)
204#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5)
205#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
206#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
207
208#define LPD270_IRQ(x) (IRQ_BOARD_START + (x))
209#define LPD270_USBC_IRQ LPD270_IRQ(2)
210#define LPD270_ETHERNET_IRQ LPD270_IRQ(3)
211#define LPD270_AC97_IRQ LPD270_IRQ(4)
212
213#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x))
214#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
215#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
216#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
217#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3)
218#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4)
219#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5)
220#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6)
221#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7)
222#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9)
223#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
224#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11)
225#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13)
226#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
227#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
228
229/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
230#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0)
231#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
232#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
233#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
234
235/* phyCORE-PXA270 (PCM027) Interrupts */
236#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
237#define PCM027_BTDET_IRQ PCM027_IRQ(0)
238#define PCM027_FF_RI_IRQ PCM027_IRQ(1)
239#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
240#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
241
242/* ITE8152 irqs */
243/* add IT8152 IRQs beyond BOARD_END */
244#ifdef CONFIG_PCI_HOST_ITE8152
245#define IT8152_IRQ(x) (IRQ_BOARD_END + (x))
246
247/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
248#define IT8152_LD_IRQ_COUNT 9
249#define IT8152_LP_IRQ_COUNT 16
250#define IT8152_PD_IRQ_COUNT 15
251
252/* Priorities: */
253#define IT8152_PD_IRQ(i) IT8152_IRQ(i)
254#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
255#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
256
257#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1)
258
259#if NR_IRQS < (IT8152_LAST_IRQ+1)
260#undef NR_IRQS
261#define NR_IRQS (IT8152_LAST_IRQ+1)
262#endif
263
264#endif /* CONFIG_PCI_HOST_ITE8152 */
diff --git a/include/asm-arm/arch-pxa/littleton.h b/include/asm-arm/arch-pxa/littleton.h
deleted file mode 100644
index 79d209b826f4..000000000000
--- a/include/asm-arm/arch-pxa/littleton.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_ARCH_ZYLONITE_H
2#define __ASM_ARCH_ZYLONITE_H
3
4#define LITTLETON_ETH_PHYS 0x30000000
5
6#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/include/asm-arm/arch-pxa/lpd270.h b/include/asm-arm/arch-pxa/lpd270.h
deleted file mode 100644
index 501d240ac120..000000000000
--- a/include/asm-arm/arch-pxa/lpd270.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * include/asm-arm/arch-pxa/lpd270.h
3 *
4 * Author: Lennert Buytenhek
5 * Created: Feb 10, 2006
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_LPD270_H
13#define __ASM_ARCH_LPD270_H
14
15#define LPD270_CPLD_PHYS PXA_CS2_PHYS
16#define LPD270_CPLD_VIRT 0xf0000000
17#define LPD270_CPLD_SIZE 0x00100000
18
19#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000)
20
21/* CPLD registers */
22#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x)))
23#define LPD270_CONTROL LPD270_CPLD_REG(0x00)
24#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04)
25#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08)
26#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14)
27#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20)
28#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24)
29#define LPD270_EGPIO LPD270_CPLD_REG(0x30)
30#define LPD270_INT_MASK LPD270_CPLD_REG(0x40)
31#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50)
32
33#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */
34#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */
35#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */
36
37
38#endif
diff --git a/include/asm-arm/arch-pxa/lubbock.h b/include/asm-arm/arch-pxa/lubbock.h
deleted file mode 100644
index 11ee73593fc3..000000000000
--- a/include/asm-arm/arch-pxa/lubbock.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/lubbock.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS
14
15#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS
16#define LUBBOCK_FPGA_VIRT (0xf0000000)
17#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
18#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)
19
20#ifndef __ASSEMBLY__
21# define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x)))
22#else
23# define __LUB_REG(x) LUB_P2V(x)
24#endif
25
26/* FPGA register virtual addresses */
27#define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
28#define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
29#define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
30#define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
31#define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
32#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
33#define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090)
34#define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0)
35#define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
36#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
37
38#ifndef __ASSEMBLY__
39extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
40#endif
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h
deleted file mode 100644
index 169b374f9921..000000000000
--- a/include/asm-arm/arch-pxa/magician.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * GPIO and IRQ definitions for HTC Magician PDA phones
3 *
4 * Copyright (c) 2007 Philipp Zabel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef _MAGICIAN_H_
13#define _MAGICIAN_H_
14
15#include <asm/arch/irqs.h>
16
17/*
18 * PXA GPIOs
19 */
20
21#define GPIO0_MAGICIAN_KEY_POWER 0
22#define GPIO9_MAGICIAN_UNKNOWN 9
23#define GPIO10_MAGICIAN_GSM_IRQ 10
24#define GPIO11_MAGICIAN_GSM_OUT1 11
25#define GPIO13_MAGICIAN_CPLD_IRQ 13
26#define GPIO18_MAGICIAN_UNKNOWN 18
27#define GPIO22_MAGICIAN_VIBRA_EN 22
28#define GPIO26_MAGICIAN_GSM_POWER 26
29#define GPIO27_MAGICIAN_USBC_PUEN 27
30#define GPIO30_MAGICIAN_nCHARGE_EN 30
31#define GPIO37_MAGICIAN_KEY_HANGUP 37
32#define GPIO38_MAGICIAN_KEY_CONTACTS 38
33#define GPIO40_MAGICIAN_GSM_OUT2 40
34#define GPIO48_MAGICIAN_UNKNOWN 48
35#define GPIO56_MAGICIAN_UNKNOWN 56
36#define GPIO57_MAGICIAN_CAM_RESET 57
37#define GPIO75_MAGICIAN_SAMSUNG_POWER 75
38#define GPIO83_MAGICIAN_nIR_EN 83
39#define GPIO86_MAGICIAN_GSM_RESET 86
40#define GPIO87_MAGICIAN_GSM_SELECT 87
41#define GPIO90_MAGICIAN_KEY_CALENDAR 90
42#define GPIO91_MAGICIAN_KEY_CAMERA 91
43#define GPIO93_MAGICIAN_KEY_UP 93
44#define GPIO94_MAGICIAN_KEY_DOWN 94
45#define GPIO95_MAGICIAN_KEY_LEFT 95
46#define GPIO96_MAGICIAN_KEY_RIGHT 96
47#define GPIO97_MAGICIAN_KEY_ENTER 97
48#define GPIO98_MAGICIAN_KEY_RECORD 98
49#define GPIO99_MAGICIAN_HEADPHONE_IN 99
50#define GPIO100_MAGICIAN_KEY_VOL_UP 100
51#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101
52#define GPIO102_MAGICIAN_KEY_PHONE 102
53#define GPIO103_MAGICIAN_LED_KP 103
54#define GPIO104_MAGICIAN_LCD_POWER_1 104
55#define GPIO105_MAGICIAN_LCD_POWER_2 105
56#define GPIO106_MAGICIAN_LCD_POWER_3 106
57#define GPIO107_MAGICIAN_DS1WM_IRQ 107
58#define GPIO108_MAGICIAN_GSM_READY 108
59#define GPIO114_MAGICIAN_UNKNOWN 114
60#define GPIO115_MAGICIAN_nPEN_IRQ 115
61#define GPIO116_MAGICIAN_nCAM_EN 116
62#define GPIO119_MAGICIAN_UNKNOWN 119
63#define GPIO120_MAGICIAN_UNKNOWN 120
64
65/*
66 * CPLD IRQs
67 */
68
69#define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0)
70#define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1)
71#define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2)
72#define IRQ_MAGICIAN_AC (IRQ_BOARD_START + 3)
73
74/*
75 * CPLD EGPIOs
76 */
77
78#define MAGICIAN_EGPIO_BASE 0x80 /* GPIO_BOARD_START */
79#define MAGICIAN_EGPIO(reg,bit) \
80 (MAGICIAN_EGPIO_BASE + 8*reg + bit)
81
82/* output */
83
84#define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2)
85#define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5)
86#define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6)
87#define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7)
88#define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0)
89#define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1)
90#define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2)
91#define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3)
92#define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4)
93#define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5)
94#define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6)
95#define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7)
96#define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0)
97#define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1)
98#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL MAGICIAN_EGPIO(2, 2)
99#define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3)
100#define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4)
101#define EGPIO_MAGICIAN_CHARGE_EN MAGICIAN_EGPIO(2, 5)
102#define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7)
103
104/* input */
105
106#define EGPIO_MAGICIAN_CABLE_STATE_AC MAGICIAN_EGPIO(4, 0)
107#define EGPIO_MAGICIAN_CABLE_STATE_USB MAGICIAN_EGPIO(4, 1)
108
109#define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0)
110#define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1)
111#define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2)
112#define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3)
113#define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4)
114
115#define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1)
116
117#endif /* _MAGICIAN_H_ */
diff --git a/include/asm-arm/arch-pxa/mainstone.h b/include/asm-arm/arch-pxa/mainstone.h
deleted file mode 100644
index 14c862adcaa1..000000000000
--- a/include/asm-arm/arch-pxa/mainstone.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mainstone.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Nov 14, 2002
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef ASM_ARCH_MAINSTONE_H
14#define ASM_ARCH_MAINSTONE_H
15
16#define MST_ETH_PHYS PXA_CS4_PHYS
17
18#define MST_FPGA_PHYS PXA_CS2_PHYS
19#define MST_FPGA_VIRT (0xf0000000)
20#define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT)
21#define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS)
22
23#ifndef __ASSEMBLY__
24# define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x)))
25#else
26# define __MST_REG(x) MST_P2V(x)
27#endif
28
29/* board level registers in the FPGA */
30
31#define MST_LEDDAT1 __MST_REG(0x08000010)
32#define MST_LEDDAT2 __MST_REG(0x08000014)
33#define MST_LEDCTRL __MST_REG(0x08000040)
34#define MST_GPSWR __MST_REG(0x08000060)
35#define MST_MSCWR1 __MST_REG(0x08000080)
36#define MST_MSCWR2 __MST_REG(0x08000084)
37#define MST_MSCWR3 __MST_REG(0x08000088)
38#define MST_MSCRD __MST_REG(0x08000090)
39#define MST_INTMSKENA __MST_REG(0x080000c0)
40#define MST_INTSETCLR __MST_REG(0x080000d0)
41#define MST_PCMCIA0 __MST_REG(0x080000e0)
42#define MST_PCMCIA1 __MST_REG(0x080000e4)
43
44#define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */
45#define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */
46#define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */
47#define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */
48#define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */
49#define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */
50#define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */
51#define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */
52#define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */
53
54#define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */
55#define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */
56#define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */
57#define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */
58#define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */
59
60#define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */
61#define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */
62#define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */
63#define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */
64#define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */
65
66#define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */
67#define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */
68#define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */
69#define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */
70#define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */
71#define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */
72#define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */
73
74#define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */
75#define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */
76#define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */
77
78#define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */
79#define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */
80#define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */
81#define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */
82#define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */
83#define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */
84#define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */
85#define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */
86#define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */
87#define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */
88
89#define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */
90#define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */
91#define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */
92#define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */
93#define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */
94#define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */
95#define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */
96#define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */
97#define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */
98#define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */
99#define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */
100#define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */
101#define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */
102#define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */
103
104#define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */
105#define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */
106#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */
107#define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */
108#define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */
109#define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */
110#define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */
111#define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */
112
113#define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */
114#define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/
115#define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */
116#define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */
117#define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */
118#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */
119
120#endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
deleted file mode 100644
index bee81d66c184..000000000000
--- a/include/asm-arm/arch-pxa/memory.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/memory.h
3 *
4 * Author: Nicolas Pitre
5 * Copyright: (C) 2001 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H
14
15/*
16 * Physical DRAM offset.
17 */
18#define PHYS_OFFSET UL(0xa0000000)
19
20/*
21 * Virtual view <-> DMA view memory address translations
22 * virt_to_bus: Used to translate the virtual address to an
23 * address suitable to be passed to set_dma_addr
24 * bus_to_virt: Used to convert an address for DMA operations
25 * to an address that the kernel can use.
26 */
27#define __virt_to_bus(x) __virt_to_phys(x)
28#define __bus_to_virt(x) __phys_to_virt(x)
29
30/*
31 * The nodes are matched with the physical SDRAM banks as follows:
32 *
33 * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff
34 * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff
35 * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff
36 * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff
37 *
38 * This needs a node mem size of 26 bits.
39 */
40#define NODE_MEM_SIZE_BITS 26
41
42#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
43void cmx270_pci_adjust_zones(int node, unsigned long *size,
44 unsigned long *holes);
45
46#define arch_adjust_zones(node, size, holes) \
47 cmx270_pci_adjust_zones(node, size, holes)
48
49#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
50#endif
51
52#endif
diff --git a/include/asm-arm/arch-pxa/mfp-pxa25x.h b/include/asm-arm/arch-pxa/mfp-pxa25x.h
deleted file mode 100644
index 0499323010ba..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa25x.h
+++ /dev/null
@@ -1,161 +0,0 @@
1#ifndef __ASM_ARCH_MFP_PXA25X_H
2#define __ASM_ARCH_MFP_PXA25X_H
3
4#include <asm/arch/mfp.h>
5#include <asm/arch/mfp-pxa2xx.h>
6
7/* GPIO */
8#define GPIO2_GPIO MFP_CFG_IN(GPIO2, AF0)
9#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0)
10#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0)
11#define GPIO5_GPIO MFP_CFG_IN(GPIO5, AF0)
12#define GPIO6_GPIO MFP_CFG_IN(GPIO6, AF0)
13#define GPIO7_GPIO MFP_CFG_IN(GPIO7, AF0)
14#define GPIO8_GPIO MFP_CFG_IN(GPIO8, AF0)
15
16#define GPIO1_RST MFP_CFG_IN(GPIO1, AF1)
17
18/* Crystal and Clock Signals */
19#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
20#define GPIO70_RTC_CLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
21#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW)
22#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
23#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
24#define GPIO12_32KHz MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
25#define GPIO72_32kHz MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW)
26
27/* SDRAM and Static Memory I/O Signals */
28#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
29#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
30#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
31#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
32#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
33
34/* Miscellaneous I/O and DMA Signals */
35#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1)
36#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1)
37#define GPIO19_DREQ_1 MFP_CFG_IN(GPIO19, AF1)
38
39/* Alternate Bus Master Mode I/O Signals */
40#define GPIO13_MBGNT MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW)
41#define GPIO73_MBGNT MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW)
42#define GPIO14_MBREQ MFP_CFG_IN(GPIO14, AF1)
43#define GPIO66_MBREQ MFP_CFG_IN(GPIO66, AF1)
44
45/* PC CARD */
46#define GPIO52_nPCE_1 MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH)
47#define GPIO53_nPCE_2 MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH)
48#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
49#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
50#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
51#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
52#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
53#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1)
54#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1)
55#define GPIO54_nPSKTSEL MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
56
57/* FFUART */
58#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1)
59#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1)
60#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1)
61#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1)
62#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1)
63#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
64#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
65#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
66
67/* BTUART */
68#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1)
69#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
70#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1)
71#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
72
73/* STUART */
74#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2)
75#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
76
77/* HWUART */
78#define GPIO42_HWUART_RXD MFP_CFG_IN(GPIO42, AF3)
79#define GPIO43_HWUART_TXD MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH)
80#define GPIO44_HWUART_CTS MFP_CFG_IN(GPIO44, AF3)
81#define GPIO45_HWUART_RTS MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH)
82#define GPIO48_HWUART_TXD MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH)
83#define GPIO49_HWUART_RXD MFP_CFG_IN(GPIO49, AF1)
84#define GPIO50_HWUART_CTS MFP_CFG_IN(GPIO50, AF1)
85#define GPIO51_HWUART_RTS MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH)
86
87/* FICP */
88#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1)
89#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
90
91/* PWM 0/1 */
92#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
93#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
94
95/* AC97 */
96#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1)
97#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1)
98#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
99#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
100#define GPIO32_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO32, AF1)
101
102/* I2S */
103#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2)
104#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
105#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2)
106#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
107#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
108#define GPIO32_I2S_SYSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
109
110/* SSP 1 */
111#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
112#define GPIO24_SSP1_SFRM MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW)
113#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
114#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1)
115#define GPIO27_SSP1_EXTCLK MFP_CFG_IN(GPIO27, AF1)
116
117/* SSP 2 - NSSP */
118#define GPIO81_SSP2_CLK_OUT MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
119#define GPIO81_SSP2_CLK_IN MFP_CFG_IN(GPIO81, AF1)
120#define GPIO82_SSP2_FRM_OUT MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW)
121#define GPIO82_SSP2_FRM_IN MFP_CFG_IN(GPIO82, AF1)
122#define GPIO83_SSP2_TXD MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW)
123#define GPIO83_SSP2_RXD MFP_CFG_IN(GPIO83, AF2)
124#define GPIO84_SSP2_TXD MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW)
125#define GPIO84_SSP2_RXD MFP_CFG_IN(GPIO84, AF2)
126
127/* MMC */
128#define GPIO6_MMC_CLK MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW)
129#define GPIO8_MMC_CS0 MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW)
130#define GPIO9_MMC_CS1 MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW)
131#define GPIO34_MMC_CS0 MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW)
132#define GPIO39_MMC_CS1 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
133#define GPIO53_MMC_CLK MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
134#define GPIO54_MMC_CLK MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW)
135#define GPIO69_MMC_CLK MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW)
136#define GPIO67_MMC_CS0 MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW)
137#define GPIO68_MMC_CS1 MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW)
138
139/* LCD */
140#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
141#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
142#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
143#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
144#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
145#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
146#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
147#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
148#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
149#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
150#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
151#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
152#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
153#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
154#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
155#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
156#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
157#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
158#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
159#define GPIO77_LCD_ACBIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
160
161#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa27x.h b/include/asm-arm/arch-pxa/mfp-pxa27x.h
deleted file mode 100644
index bc73ab84167c..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa27x.h
+++ /dev/null
@@ -1,433 +0,0 @@
1#ifndef __ASM_ARCH_MFP_PXA27X_H
2#define __ASM_ARCH_MFP_PXA27X_H
3
4/*
5 * NOTE: for those special-function bidirectional GPIOs, as described
6 * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input
7 * alternative is preserved, the direction is actually selected by the
8 * specific controller, and this should work in most cases.
9 */
10
11#include <asm/arch/mfp.h>
12#include <asm/arch/mfp-pxa2xx.h>
13
14/* GPIO */
15#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0)
16#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0)
17#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0)
18#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0)
19#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0)
20#define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0)
21#define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0)
22#define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0)
23#define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0)
24#define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0)
25#define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0)
26#define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0)
27#define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0)
28#define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0)
29#define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0)
30#define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0)
31#define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0)
32#define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0)
33#define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0)
34#define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0)
35#define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0)
36#define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0)
37#define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0)
38#define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0)
39#define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0)
40#define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0)
41#define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0)
42#define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0)
43#define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0)
44#define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0)
45#define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0)
46#define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0)
47#define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0)
48#define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0)
49#define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0)
50#define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0)
51
52/* Crystal and Clock Signals */
53#define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW)
54#define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
55#define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW)
56#define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW)
57#define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1)
58
59/* OS Timer Signals */
60#define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1)
61#define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1)
62#define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW)
63#define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW)
64#define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
65#define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
66
67/* SDRAM and Static Memory I/O Signals */
68#define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH)
69#define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH)
70#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
71#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
72#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
73#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
74#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
75
76/* Miscellaneous I/O and DMA Signals */
77#define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH)
78#define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH)
79#define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH)
80#define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH)
81#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1)
82#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1)
83#define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1)
84#define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1)
85#define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2)
86#define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2)
87#define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2)
88
89/* Alternate Bus Master Mode I/O Signals */
90#define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2)
91#define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2)
92#define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2)
93#define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3)
94#define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW)
95#define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW)
96#define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW)
97#define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW)
98
99/* PC CARD */
100#define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH)
101#define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH)
102#define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH)
103#define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH)
104#define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
105#define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
106#define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1)
107#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
108#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
109#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
110#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
111#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
112#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1)
113#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1)
114#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
115#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH)
116
117/* I2C */
118#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1)
119#define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1)
120
121/* FFUART */
122#define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3)
123#define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3)
124#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1)
125#define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3)
126#define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1)
127#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1)
128#define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2)
129#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1)
130#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1)
131#define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3)
132#define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3)
133#define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1)
134#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1)
135#define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1)
136#define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1)
137#define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1)
138#define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3)
139#define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3)
140#define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH)
141#define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH)
142#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
143#define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH)
144#define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH)
145#define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH)
146#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
147#define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH)
148#define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH)
149#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
150#define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH)
151
152/* BTUART */
153#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1)
154#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1)
155#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
156#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
157
158/* STUART */
159#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2)
160#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
161
162/* FICP */
163#define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2)
164#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1)
165#define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH)
166#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
167
168/* PWM 0/1/2/3 */
169#define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW)
170#define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW)
171#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
172#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
173#define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW)
174#define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW)
175#define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW)
176#define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW)
177#define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW)
178#define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW)
179
180/* AC97 */
181#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
182#define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW)
183#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
184#define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW)
185#define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW)
186#define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW)
187#define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW)
188#define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW)
189#define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW)
190#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1)
191#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1)
192#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2)
193#define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2)
194
195/* I2S */
196#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2)
197#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
198#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2)
199#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
200#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
201#define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW)
202
203/* SSP 1 */
204#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
205#define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3)
206#define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW)
207#define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW)
208#define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2)
209#define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3)
210#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
211#define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW)
212#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1)
213#define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2)
214
215/* SSP 2 */
216#define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1)
217#define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3)
218#define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW)
219#define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2)
220#define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3)
221#define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW)
222#define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2)
223#define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2)
224#define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW)
225#define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3)
226#define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW)
227#define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW)
228#define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW)
229#define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW)
230#define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2)
231#define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW)
232#define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1)
233#define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1)
234#define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2)
235#define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1)
236#define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1)
237#define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2)
238#define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2)
239
240/* SSP 3 */
241#define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3)
242#define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW)
243#define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2)
244#define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1)
245#define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW)
246#define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3)
247#define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3)
248#define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1)
249#define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW)
250#define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW)
251#define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
252#define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3)
253#define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1)
254#define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1)
255
256/* MMC */
257#define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW)
258#define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1)
259#define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1)
260#define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1)
261#define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1)
262#define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1)
263
264/* LCD */
265#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
266#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
267#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
268#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
269#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
270#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
271#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
272#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
273#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
274#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
275#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
276#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
277#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
278#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
279#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
280#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
281#define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW)
282#define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW)
283#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
284#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
285#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
286#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
287#define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1)
288#define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW)
289
290/* Keypad */
291#define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1)
292#define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1)
293#define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1)
294#define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1)
295#define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1)
296#define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1)
297#define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1)
298#define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2)
299#define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1)
300#define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1)
301#define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1)
302#define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2)
303#define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3)
304#define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3)
305#define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3)
306#define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2)
307#define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1)
308#define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1)
309#define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1)
310#define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3)
311#define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1)
312#define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1)
313#define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3)
314#define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3)
315#define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3)
316#define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH)
317#define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH)
318#define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH)
319#define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH)
320#define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH)
321#define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH)
322#define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH)
323#define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH)
324#define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH)
325#define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH)
326#define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH)
327
328/* USB P3 */
329#define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3)
330#define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3)
331#define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
332#define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
333#define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
334#define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3)
335#define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3)
336#define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2)
337#define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2)
338#define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3)
339
340/* USB P2 */
341#define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW)
342#define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2)
343#define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW)
344#define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW)
345#define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3)
346#define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
347#define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3)
348#define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2)
349#define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2)
350
351/* USB Host Port 1/2 */
352#define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1)
353#define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW)
354#define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1)
355#define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW)
356
357/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */
358#define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2)
359#define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1)
360#define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2)
361#define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2)
362#define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW)
363#define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1)
364#define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1)
365#define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2)
366#define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3)
367#define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW)
368#define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3)
369#define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3)
370#define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3)
371#define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1)
372#define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1)
373#define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1)
374#define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1)
375#define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1)
376#define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW)
377#define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3)
378#define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1)
379#define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2)
380#define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3)
381#define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3)
382#define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3)
383#define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3)
384#define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3)
385#define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3)
386#define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2)
387#define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2)
388#define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2)
389#define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2)
390#define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1)
391#define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1)
392#define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1)
393#define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1)
394#define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1)
395#define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1)
396#define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1)
397
398/* Universal Subscriber ID Interface */
399#define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW)
400#define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW)
401#define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW)
402#define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW)
403#define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW)
404#define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW)
405#define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW)
406#define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3)
407#define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW)
408#define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW)
409
410/* Mobile Scalable Link (MSL) Interface */
411#define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW)
412#define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW)
413#define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW)
414#define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW)
415#define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW)
416#define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
417#define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2)
418#define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2)
419#define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2)
420#define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2)
421#define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2)
422#define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2)
423#define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2)
424#define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW)
425
426/* Memory Stick Host Controller */
427#define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW)
428#define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2)
429#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2)
430#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
431
432extern int keypad_set_wake(unsigned int on);
433#endif /* __ASM_ARCH_MFP_PXA27X_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
deleted file mode 100644
index 8de1c0dae624..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa2xx.h
+++ /dev/null
@@ -1,133 +0,0 @@
1#ifndef __ASM_ARCH_MFP_PXA2XX_H
2#define __ASM_ARCH_MFP_PXA2XX_H
3
4#include <asm/arch/mfp.h>
5
6/*
7 * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
8 *
9 * MFP_PIN(x)
10 * MFP_AFx
11 * MFP_LPM_DRIVE_{LOW, HIGH}
12 * MFP_LPM_EDGE_x
13 *
14 * other MFP_x bit definitions will be ignored
15 *
16 * and adds the below two bits specifically for pxa2xx:
17 *
18 * bit 23 - Input/Output (PXA2xx specific)
19 * bit 24 - Wakeup Enable(PXA2xx specific)
20 */
21
22#define MFP_DIR_IN (0x0 << 23)
23#define MFP_DIR_OUT (0x1 << 23)
24#define MFP_DIR_MASK (0x1 << 23)
25#define MFP_DIR(x) (((x) >> 23) & 0x1)
26
27#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
28#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
29#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
30#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
31
32/* specifically for enabling wakeup on keypad GPIOs */
33#define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP)
34
35#define MFP_CFG_IN(pin, af) \
36 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
37 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN))
38
39/* NOTE: pins configured as output _must_ provide a low power state,
40 * and this state should help to minimize the power dissipation.
41 */
42#define MFP_CFG_OUT(pin, af, state) \
43 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
44 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
45
46/* Common configurations for pxa25x and pxa27x
47 *
48 * Note: pins configured as GPIO are always initialized to input
49 * so not to cause any side effect
50 */
51#define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0)
52#define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0)
53#define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0)
54#define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0)
55#define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0)
56#define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0)
57#define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0)
58#define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0)
59#define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0)
60#define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0)
61#define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0)
62#define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0)
63#define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0)
64#define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0)
65#define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0)
66#define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0)
67#define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0)
68#define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0)
69#define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0)
70#define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0)
71#define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0)
72#define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0)
73#define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0)
74#define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0)
75#define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0)
76#define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0)
77#define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0)
78#define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0)
79#define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0)
80#define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0)
81#define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0)
82#define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0)
83#define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0)
84#define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0)
85#define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0)
86#define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0)
87#define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0)
88#define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0)
89#define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0)
90#define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0)
91#define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0)
92#define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0)
93#define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0)
94#define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0)
95#define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0)
96#define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0)
97#define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0)
98#define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0)
99#define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0)
100#define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0)
101#define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0)
102#define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0)
103#define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0)
104#define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0)
105#define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0)
106#define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0)
107#define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0)
108#define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0)
109#define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0)
110#define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0)
111#define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0)
112#define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0)
113#define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0)
114#define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0)
115#define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0)
116#define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0)
117#define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0)
118#define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0)
119#define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0)
120#define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0)
121#define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0)
122#define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0)
123#define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0)
124#define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0)
125#define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0)
126#define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0)
127#define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0)
128#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0)
129
130extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
131extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm);
132extern int gpio_set_wake(unsigned int gpio, unsigned int on);
133#endif /* __ASM_ARCH_MFP_PXA2XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h
deleted file mode 100644
index bb410313556f..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa300.h
+++ /dev/null
@@ -1,575 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp-pxa300.h
3 *
4 * PXA300/PXA310 specific MFP configuration definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 * 2007-08-21: eric miao <eric.miao@marvell.com>
8 * initial version
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_MFP_PXA300_H
16#define __ASM_ARCH_MFP_PXA300_H
17
18#include <asm/arch/mfp.h>
19#include <asm/arch/mfp-pxa3xx.h>
20
21/* GPIO */
22#define GPIO46_GPIO MFP_CFG(GPIO46, AF1)
23#define GPIO49_GPIO MFP_CFG(GPIO49, AF3)
24#define GPIO50_GPIO MFP_CFG(GPIO50, AF2)
25#define GPIO51_GPIO MFP_CFG(GPIO51, AF3)
26#define GPIO52_GPIO MFP_CFG(GPIO52, AF3)
27#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
28#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
29#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
30#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
31#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
32#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
33
34#ifdef CONFIG_CPU_PXA310
35#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
36#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
37#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
38#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
39#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
40#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
41#endif
42
43/* Chip Select */
44#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1)
45
46/* AC97 */
47#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1)
48#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1)
49#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1)
50#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1)
51#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1)
52#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3)
53#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2)
54#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3)
55#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2)
56#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1)
57#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1)
58
59/* I2C */
60#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH)
61#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH)
62
63/* QCI */
64#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X)
65#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X)
66#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X)
67#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X)
68#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X)
69#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X)
70#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X)
71#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X)
72#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X)
73#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X)
74#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X)
75#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X)
76#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X)
77#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X)
78
79/* KEYPAD */
80#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT)
81#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT)
82#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT)
83#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT)
84#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT)
85#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
86#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
87#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT)
88#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT)
89#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT)
90#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
91#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
92#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
93#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
94#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
95#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
96#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
97#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
98#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
99#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
100#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
101#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
102#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
103#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
104#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
105#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
106#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
107#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
108#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT)
109#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
110#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT)
111#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
112#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
113#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
114#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT)
115
116#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT)
117#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT)
118#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
119#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
120#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT)
121#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT)
122#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT)
123#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT)
124#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT)
125#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT)
126#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
127#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
128#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
129#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
130#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
131#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
132#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
133#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT)
134#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT)
135
136#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
137#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH)
138#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH)
139#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
140#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH)
141#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH)
142#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH)
143#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH)
144#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH)
145#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
146#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
147#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH)
148#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH)
149#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH)
150#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH)
151#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
152#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
153#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
154#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
155#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
156#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH)
157#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
158#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH)
159#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH)
160
161/* LCD */
162#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X)
163#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X)
164#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X)
165#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X)
166#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X)
167#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X)
168#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X)
169#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X)
170#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X)
171#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X)
172#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X)
173#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X)
174#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X)
175#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X)
176#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X)
177#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X)
178#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X)
179#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X)
180#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X)
181#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X)
182#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X)
183#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS02X)
184#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X)
185#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X)
186
187#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X)
188#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X)
189#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X)
190
191/* Mini-LCD */
192#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X)
193#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X)
194#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X)
195#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X)
196#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X)
197#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X)
198#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X)
199#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X)
200#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X)
201#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X)
202#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X)
203#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X)
204#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X)
205#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X)
206#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X)
207#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X)
208#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X)
209#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X)
210#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X)
211#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X)
212
213/* MMC1 */
214#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
215#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
216#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH)
217#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH)
218#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH)
219#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH)
220#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
221#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
222
223/* MMC2 */
224#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH)
225#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH)
226#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH)
227#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH)
228#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH)
229#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH)
230#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
231#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
232#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
233#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
234#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH)
235#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH)
236
237/* SSP1 */
238#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1)
239#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1)
240#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6)
241#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2)
242#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5)
243#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5)
244#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1)
245#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1)
246#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7)
247#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2)
248#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2)
249#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7)
250#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5)
251#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4)
252#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5)
253#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6)
254#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1)
255#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6)
256#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6)
257#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1)
258
259/* SSP2 */
260#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2)
261#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2)
262#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2)
263#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2)
264#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2)
265#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6)
266#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6)
267#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2)
268#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2)
269#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2)
270#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7)
271#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5)
272#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4)
273#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2)
274#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5)
275#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5)
276#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2)
277#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7)
278#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6)
279#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4)
280#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2)
281#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2)
282#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4)
283#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7)
284
285/* SSP3 */
286#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW)
287#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT)
288#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW)
289#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT)
290#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
291#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT)
292#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW)
293#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT)
294#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW)
295#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT)
296#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW)
297#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
298
299/* SSP4 */
300#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
301#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
302#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH)
303#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH)
304#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH)
305#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH)
306
307/* UART1 */
308#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT)
309#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT)
310#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT)
311#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT)
312#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT)
313#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT)
314
315#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT)
316#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT)
317#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT)
318#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT)
319#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT)
320#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
321
322#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT)
323#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT)
324#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT)
325#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT)
326#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
327#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT)
328
329#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT)
330#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT)
331#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT)
332#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT)
333#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
334#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT)
335
336#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT)
337#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT)
338#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT)
339
340#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT)
341#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT)
342#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT)
343
344#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
345#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT)
346#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT)
347#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT)
348#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT)
349#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT)
350#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT)
351#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT)
352
353#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT)
354#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
355#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT)
356#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT)
357#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT)
358#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
359#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT)
360
361/* UART2 */
362#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT)
363#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT)
364#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT)
365#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT)
366
367#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT)
368#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT)
369#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT)
370#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT)
371
372#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT)
373#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT)
374#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT)
375#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT)
376
377#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT)
378#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT)
379#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT)
380#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT)
381
382/* UART3 */
383#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT)
384#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT)
385#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT)
386#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT)
387
388#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT)
389#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT)
390#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT)
391#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT)
392
393#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT)
394#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT)
395#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT)
396#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT)
397#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT)
398#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
399
400#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT)
401#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT)
402#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT)
403#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT)
404#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT)
405#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
406
407/* USB Host */
408#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1)
409#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1)
410
411/* USB P3 */
412#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2)
413#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2)
414#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2)
415#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2)
416#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2)
417#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2)
418
419/* PWM */
420#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1)
421#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1)
422#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1)
423#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1)
424
425/* CIR */
426#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5)
427#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3)
428
429#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5)
430#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2)
431
432#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1)
433#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7)
434#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6)
435#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6)
436#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6)
437#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6)
438#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2)
439#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3)
440#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7)
441#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6)
442
443#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1)
444
445#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1)
446#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1)
447#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1)
448#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1)
449
450#define GPIO9_SCIO MFP_CFG(GPIO9, AF1)
451#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4)
452#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1)
453
454/*
455 * PXA300 specific MFP configurations
456 */
457#ifdef CONFIG_CPU_PXA300
458#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2)
459#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3)
460#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4)
461#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4)
462#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5)
463#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2)
464#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2)
465#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2)
466#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2)
467#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2)
468#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2)
469#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2)
470
471/* U2D UTMI */
472#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1)
473#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3)
474#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1)
475#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5)
476#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3)
477#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2)
478#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5)
479#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3)
480#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2)
481#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1)
482#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5)
483#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1)
484#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3)
485#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3)
486#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3)
487#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4)
488#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3)
489#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3)
490#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3)
491#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4)
492#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2)
493#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7)
494#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4)
495#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2)
496#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3)
497#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5)
498#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1)
499#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2)
500#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3)
501#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3)
502#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2)
503#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3)
504#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5)
505#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3)
506#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5)
507#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3)
508#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4)
509#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3)
510#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7)
511#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5)
512#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3)
513#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5)
514#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3)
515#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3)
516#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3)
517#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3)
518#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3)
519#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3)
520#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3)
521#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3)
522#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3)
523#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3)
524#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3)
525#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3)
526#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3)
527#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3)
528#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3)
529#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3)
530#endif /* CONFIG_CPU_PXA300 */
531
532/*
533 * PXA310 specific MFP configurations
534 */
535#ifdef CONFIG_CPU_PXA310
536/* USB P2 */
537#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1)
538#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1)
539#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1)
540#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1)
541#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1)
542#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1)
543
544/* MMC1 */
545#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3)
546#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3)
547
548/* MMC3 */
549#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2)
550#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2)
551#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1)
552#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1)
553#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1)
554#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1)
555#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1)
556#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1)
557
558/* ULPI */
559#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1)
560#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3)
561#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3)
562#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3)
563#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3)
564#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3)
565#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3)
566#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3)
567#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3)
568#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1)
569
570#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
571#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
572#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
573#endif /* CONFIG_CPU_PXA310 */
574
575#endif /* __ASM_ARCH_MFP_PXA300_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h
deleted file mode 100644
index 576aa46d90fc..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa320.h
+++ /dev/null
@@ -1,447 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp-pxa320.h
3 *
4 * PXA320 specific MFP configuration definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 * 2007-08-21: eric miao <eric.miao@marvell.com>
8 * initial version
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_MFP_PXA320_H
16#define __ASM_ARCH_MFP_PXA320_H
17
18#include <asm/arch/mfp.h>
19#include <asm/arch/mfp-pxa3xx.h>
20
21/* GPIO */
22#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
23#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
24#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
25#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
26#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
27
28#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
29#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
30#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
31#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
32#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
33#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
34#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0)
35#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0)
36#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0)
37#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0)
38#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0)
39
40/* Chip Select */
41#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1)
42
43/* AC97 */
44#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1)
45#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1)
46#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1)
47#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1)
48#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1)
49#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2)
50#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2)
51#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3)
52#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3)
53#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1)
54#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1)
55
56/* I2C */
57#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH)
58#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH)
59
60/* QCI */
61#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X)
62#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X)
63#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X)
64#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X)
65#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X)
66#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X)
67#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X)
68#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X)
69#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X)
70#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X)
71#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X)
72#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X)
73#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X)
74#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X)
75
76#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5)
77
78#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3)
79#define GPIO0_DRQ MFP_CFG(GPIO0, AF2)
80#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5)
81#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6)
82#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1)
83#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4)
84#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1)
85#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1)
86
87#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT)
88#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT)
89#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
90#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
91
92#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT)
93#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT)
94#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
95#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
96#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
97#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
98#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
99#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
100
101#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
102#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
103#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
104#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
105#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
106#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
107#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
108#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
109
110#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT)
111#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT)
112
113#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
114#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
115#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
116#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
117#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
118#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
119#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
120#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
121
122#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT)
123#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT)
124#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
125#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
126#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
127#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
128#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
129#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
130
131#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH)
132#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH)
133#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
134#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
135#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
136#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH)
137
138#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
139#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
140#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
141#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
142#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
143#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH)
144#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH)
145#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
146
147/* LCD */
148#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X)
149#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X)
150#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X)
151#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X)
152#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X)
153#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X)
154#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X)
155#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X)
156#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X)
157#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X)
158#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X)
159#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X)
160#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X)
161#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X)
162#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X)
163#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X)
164#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X)
165#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X)
166#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X)
167#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X)
168#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X)
169#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X)
170#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X)
171#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X)
172#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X)
173#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X)
174
175#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X)
176#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X)
177#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X)
178#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X)
179#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X)
180#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X)
181#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X)
182#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X)
183#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X)
184#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X)
185#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X)
186#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X)
187#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X)
188#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X)
189#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X)
190#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X)
191#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X)
192#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X)
193#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X)
194#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X)
195#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X)
196#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X)
197#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X)
198#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X)
199
200/* MMC1 */
201#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH)
202#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH)
203#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH)
204#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH)
205#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH)
206#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
207#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
208#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
209#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
210#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH)
211#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH)
212#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH)
213#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH)
214
215#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH)
216#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH)
217#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH)
218#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH)
219#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
220#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
221
222#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH)
223#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH)
224#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH)
225#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH)
226#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH)
227#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH)
228#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH)
229#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH)
230#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH)
231#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
232#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH)
233#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
234
235/* 1-Wire */
236#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT)
237#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
238
239/* SSP1 */
240#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1)
241#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1)
242#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1)
243#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1)
244#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6)
245#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1)
246#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1)
247#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6)
248
249/* SSP2 */
250#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2)
251#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2)
252#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2)
253#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2)
254#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2)
255#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5)
256#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2)
257#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2)
258#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5)
259
260#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
261#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
262#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
263#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
264#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
265#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
266#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
267#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW)
268#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT)
269#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW)
270#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT)
271#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW)
272
273#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH)
274#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH)
275#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH)
276#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH)
277#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
278#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
279#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH)
280
281/* UART1 */
282#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT)
283#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT)
284#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT)
285#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT)
286#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT)
287#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT)
288#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT)
289#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT)
290#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT)
291#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT)
292#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT)
293#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT)
294#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT)
295#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT)
296#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT)
297#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT)
298#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT)
299#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT)
300#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT)
301#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT)
302#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT)
303#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT)
304#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
305#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
306#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT)
307#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
308#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT)
309#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT)
310
311/* UART2 */
312#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT)
313#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT)
314#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT)
315#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT)
316#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
317#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
318#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT)
319#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT)
320
321/* UART3 */
322#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT)
323#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT)
324#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT)
325#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT)
326#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT)
327#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT)
328#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT)
329#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
330#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
331#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT)
332#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT)
333#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
334#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT)
335#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT)
336#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT)
337#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT)
338#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT)
339#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT)
340#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT)
341#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT)
342
343
344/* USB 2.0 UTMI */
345#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1)
346#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3)
347#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1)
348#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5)
349#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3)
350#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2)
351#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5)
352#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3)
353#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1)
354#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5)
355#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1)
356#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3)
357#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3)
358#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3)
359#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4)
360#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3)
361#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3)
362#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3)
363
364#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3)
365#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3)
366#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3)
367#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3)
368#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3)
369#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3)
370#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3)
371#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3)
372
373#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3)
374#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3)
375#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3)
376#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3)
377#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3)
378#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3)
379#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3)
380#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3)
381
382#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4)
383#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2)
384#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7)
385
386#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4)
387#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2)
388#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4)
389#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5)
390
391#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1)
392#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2)
393#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3)
394
395#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3)
396#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2)
397#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3)
398
399#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5)
400#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3)
401#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7)
402#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5)
403
404#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4)
405#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5)
406#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7)
407
408#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5)
409#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3)
410#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5)
411
412/* USB Host 1.1 */
413#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1)
414#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1)
415
416/* USB P2 */
417#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2)
418#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4)
419#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4)
420#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2)
421#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2)
422#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2)
423#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2)
424#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2)
425#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2)
426#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2)
427
428/* USB P3 */
429#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2)
430#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2)
431#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2)
432#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2)
433#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2)
434#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2)
435
436#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6)
437#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6)
438
439#define GPIO2_RDY MFP_CFG(GPIO2, AF1)
440#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3)
441
442#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1)
443#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1)
444#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1)
445#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1)
446
447#endif /* __ASM_ARCH_MFP_PXA320_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa3xx.h b/include/asm-arm/arch-pxa/mfp-pxa3xx.h
deleted file mode 100644
index 1f6b35c015d0..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa3xx.h
+++ /dev/null
@@ -1,252 +0,0 @@
1#ifndef __ASM_ARCH_MFP_PXA3XX_H
2#define __ASM_ARCH_MFP_PXA3XX_H
3
4#define MFPR_BASE (0x40e10000)
5#define MFPR_SIZE (PAGE_SIZE)
6
7/* MFPR register bit definitions */
8#define MFPR_PULL_SEL (0x1 << 15)
9#define MFPR_PULLUP_EN (0x1 << 14)
10#define MFPR_PULLDOWN_EN (0x1 << 13)
11#define MFPR_SLEEP_SEL (0x1 << 9)
12#define MFPR_SLEEP_OE_N (0x1 << 7)
13#define MFPR_EDGE_CLEAR (0x1 << 6)
14#define MFPR_EDGE_FALL_EN (0x1 << 5)
15#define MFPR_EDGE_RISE_EN (0x1 << 4)
16
17#define MFPR_SLEEP_DATA(x) ((x) << 8)
18#define MFPR_DRIVE(x) (((x) & 0x7) << 10)
19#define MFPR_AF_SEL(x) (((x) & 0x7) << 0)
20
21#define MFPR_EDGE_NONE (0)
22#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN)
23#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN)
24#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
25
26/*
27 * Table that determines the low power modes outputs, with actual settings
28 * used in parentheses for don't-care values. Except for the float output,
29 * the configured driven and pulled levels match, so if there is a need for
30 * non-LPM pulled output, the same configuration could probably be used.
31 *
32 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
33 * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
34 *
35 * Input 0 X(0) X(0) X(0) 0
36 * Drive 0 0 0 0 X(1) 0
37 * Drive 1 0 1 X(1) 0 0
38 * Pull hi (1) 1 X(1) 1 0 0
39 * Pull lo (0) 1 X(0) 0 1 0
40 * Z (float) 1 X(0) 0 0 0
41 */
42#define MFPR_LPM_INPUT (0)
43#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
44#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
45#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N)
46#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
47#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N)
48#define MFPR_LPM_MASK (0xe080)
49
50/*
51 * The pullup and pulldown state of the MFP pin at run mode is by default
52 * determined by the selected alternate function. In case that some buggy
53 * devices need to override this default behavior, the definitions below
54 * indicates the setting of corresponding MFPR bits
55 *
56 * Definition pull_sel pullup_en pulldown_en
57 * MFPR_PULL_NONE 0 0 0
58 * MFPR_PULL_LOW 1 0 1
59 * MFPR_PULL_HIGH 1 1 0
60 * MFPR_PULL_BOTH 1 1 1
61 */
62#define MFPR_PULL_NONE (0)
63#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
64#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN)
65#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN)
66
67/* PXA3xx common MFP configurations - processor specific ones defined
68 * in mfp-pxa300.h and mfp-pxa320.h
69 */
70#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
71#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
72#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
73#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
74#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
75#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
76#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
77#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
78#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
79#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
80#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
81#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
82#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
83#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
84#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
85#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
86#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
87#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
88#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
89#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
90#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
91#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
92#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
93#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
94#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
95#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
96#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
97#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
98#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
99#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
100#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
101#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
102#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
103#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
104#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
105#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
106#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
107#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
108#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
109#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
110#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
111#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
112#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
113#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
114#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
115#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
116
117#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
118#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
119
120#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
121#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
122#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
123
124#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
125
126#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
127#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
128#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
129#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
130#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
131#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
132#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
133#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
134#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
135#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
136#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
137#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
138#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
139#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
140#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
141#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
142#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
143#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
144#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
145#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
146#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
147#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
148#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
149#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
150#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
151#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
152#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
153#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
154#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
155#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
156#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
157#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
158#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
159#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
160#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
161#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
162#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
163#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
164#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
165#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
166#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
167#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
168#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
169#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
170#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
171#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
172#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
173#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
174#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
175#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
176#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
177#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
178#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
179#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
180#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
181#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
182#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
183#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
184#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
185#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
186#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
187#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
188#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
189#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
190#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
191
192#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
193#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
194#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
195#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
196#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
197#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
198#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
199
200/*
201 * each MFP pin will have a MFPR register, since the offset of the
202 * register varies between processors, the processor specific code
203 * should initialize the pin offsets by pxa3xx_mfp_init_addr()
204 *
205 * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
206 * structure, which represents a range of MFP pins from "start" to
207 * "end", with the offset begining at "offset", to define a single
208 * pin, let "end" = -1
209 *
210 * use
211 *
212 * MFP_ADDR_X() to define a range of pins
213 * MFP_ADDR() to define a single pin
214 * MFP_ADDR_END to signal the end of pin offset definitions
215 */
216struct pxa3xx_mfp_addr_map {
217 unsigned int start;
218 unsigned int end;
219 unsigned long offset;
220};
221
222#define MFP_ADDR_X(start, end, offset) \
223 { MFP_PIN_##start, MFP_PIN_##end, offset }
224
225#define MFP_ADDR(pin, offset) \
226 { MFP_PIN_##pin, -1, offset }
227
228#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
229
230/*
231 * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
232 * to the MFPR register
233 */
234unsigned long pxa3xx_mfp_read(int mfp);
235void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
236
237/*
238 * pxa3xx_mfp_config - configure the MFPR registers
239 *
240 * used by board specific initialization code
241 */
242void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
243
244/*
245 * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
246 * index and MFPR register offset
247 *
248 * used by processor specific code
249 */
250void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
251void __init pxa3xx_init_mfp(void);
252#endif /* __ASM_ARCH_MFP_PXA3XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa930.h b/include/asm-arm/arch-pxa/mfp-pxa930.h
deleted file mode 100644
index c4e945ab1923..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa930.h
+++ /dev/null
@@ -1,491 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp-pxa930.h
3 *
4 * PXA930 specific MFP configuration definitions
5 *
6 * Copyright (C) 2007-2008 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_MFP_PXA9xx_H
14#define __ASM_ARCH_MFP_PXA9xx_H
15
16#include <asm/arch/mfp.h>
17#include <asm/arch/mfp-pxa3xx.h>
18
19/* GPIO */
20#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
21#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
22#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
23#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
24#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
25#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
26#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
27#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
28#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
29#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
30#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
31
32#define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0)
33#define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0)
34#define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0)
35#define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0)
36
37#define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0)
38#define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0)
39#define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0)
40#define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0)
41#define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0)
42#define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0)
43#define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0)
44#define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0)
45#define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0)
46#define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0)
47#define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0)
48#define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0)
49#define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0)
50#define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0)
51#define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0)
52#define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0)
53#define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0)
54#define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0)
55#define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0)
56#define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0)
57#define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0)
58#define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0)
59#define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0)
60#define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0)
61#define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0)
62
63#define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0)
64#define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0)
65#define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0)
66#define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0)
67#define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0)
68#define nLUA_GPIO_58 MFP_CFG(nLUA, AF0)
69#define nLLA_GPIO_59 MFP_CFG(nLLA, AF0)
70#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0)
71#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0)
72#define RDY_GPIO_62 MFP_CFG(RDY, AF0)
73
74/* Chip Select */
75#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
76#define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH)
77
78/* AC97 */
79#define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3)
80#define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3)
81#define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3)
82#define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3)
83#define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3)
84#define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3)
85
86/* I2C */
87#define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH)
88#define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH)
89
90#define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH)
91#define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH)
92
93#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
94#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
95
96#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
97#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
98
99#define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH)
100#define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH)
101
102#define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
103#define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
104
105#define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH)
106#define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH)
107
108/* QCI */
109#define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW)
110#define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW)
111#define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW)
112#define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW)
113#define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW)
114#define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW)
115#define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW)
116#define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW)
117#define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW)
118#define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW)
119#define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW)
120#define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW)
121#define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW)
122#define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW)
123
124/* KEYPAD */
125#define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT)
126#define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT)
127#define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT)
128#define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT)
129#define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT)
130#define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
131#define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
132#define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT)
133
134#define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT)
135#define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT)
136#define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT)
137#define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT)
138
139#define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT)
140#define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT)
141#define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT)
142#define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT)
143#define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT)
144#define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT)
145
146#define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT)
147#define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT)
148#define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT)
149#define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT)
150#define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT)
151#define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT)
152#define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT)
153#define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1)
154#define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4)
155
156#define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH)
157#define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH)
158#define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH)
159#define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
160#define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH)
161#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH)
162#define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH)
163#define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH)
164#define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH)
165
166/* LCD */
167#define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1)
168#define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1)
169#define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1)
170#define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1)
171#define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1)
172#define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2)
173#define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1)
174#define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1)
175#define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1)
176#define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1)
177#define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1)
178#define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1)
179#define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1)
180#define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1)
181#define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1)
182#define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1)
183#define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1)
184#define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1)
185#define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1)
186#define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1)
187#define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1)
188#define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1)
189#define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1)
190#define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1)
191#define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1)
192#define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3)
193#define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3)
194#define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1)
195
196/* Mini-LCD */
197#define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3)
198#define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3)
199#define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3)
200#define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3)
201#define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3)
202#define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3)
203#define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3)
204#define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3)
205#define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3)
206#define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3)
207#define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3)
208#define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3)
209#define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3)
210#define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3)
211#define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3)
212#define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3)
213#define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3)
214#define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3)
215#define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3)
216#define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3)
217#define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5)
218
219/* MMC1 */
220#define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4)
221#define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4)
222#define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4)
223#define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4)
224#define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4)
225#define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4)
226#define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3)
227#define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3)
228#define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3)
229#define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3)
230#define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3)
231#define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3)
232
233#define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2)
234#define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2)
235#define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2)
236#define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3)
237#define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2)
238
239/* MMC2 */
240#define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7)
241#define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7)
242#define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7)
243#define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7)
244#define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7)
245#define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7)
246
247#define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1)
248#define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1)
249#define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1)
250#define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1)
251#define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1)
252#define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1)
253
254#define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3)
255#define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3)
256#define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3)
257#define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3)
258#define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3)
259#define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3)
260
261/* BSSP1 */
262#define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3)
263#define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3)
264#define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3)
265#define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3)
266#define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5)
267#define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5)
268
269/* BSSP2 */
270#define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1)
271#define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1)
272#define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1)
273#define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1)
274#define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1)
275#define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4)
276
277/* BSSP3 */
278#define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1)
279#define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1)
280#define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1)
281#define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1)
282#define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1)
283
284/* BSSP4 */
285#define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4)
286#define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4)
287#define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4)
288#define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4)
289
290#define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4)
291#define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4)
292#define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4)
293#define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4)
294
295/* GSSP1 */
296#define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2)
297#define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2)
298#define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2)
299#define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2)
300#define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2)
301
302#define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4)
303#define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4)
304#define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4)
305#define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4)
306
307/* GSSP2 */
308#define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4)
309#define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4)
310#define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4)
311#define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4)
312
313#define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4)
314#define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4)
315#define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4)
316#define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4)
317
318#define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2)
319#define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2)
320#define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2)
321#define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2)
322#define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2)
323#define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5)
324
325#define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2)
326#define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2)
327#define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2)
328#define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2)
329
330/* UART1 - FFUART */
331#define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1)
332#define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1)
333#define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1)
334#define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1)
335#define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1)
336#define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1)
337#define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1)
338#define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1)
339
340#define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2)
341#define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2)
342#define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2)
343#define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2)
344#define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2)
345#define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2)
346#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2)
347#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2)
348
349/* UART2 - BTUART */
350#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1)
351#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1)
352#define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1)
353#define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1)
354
355/* UART3 - STUART */
356#define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3)
357#define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3)
358#define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3)
359#define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3)
360
361#define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5)
362#define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5)
363#define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5)
364#define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5)
365
366/* DFI */
367#define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2)
368#define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2)
369#define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2)
370#define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2)
371#define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2)
372#define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2)
373#define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2)
374#define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2)
375#define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2)
376#define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2)
377#define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2)
378#define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2)
379#define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2)
380#define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2)
381#define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2)
382#define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2)
383#define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2)
384#define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2)
385#define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2)
386#define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2)
387#define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2)
388#define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2)
389
390/* DFI - NAND */
391#define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH)
392#define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW)
393#define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW)
394#define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW)
395#define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW)
396#define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW)
397#define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW)
398#define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW)
399#define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW)
400#define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW)
401#define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW)
402#define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW)
403#define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW)
404#define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW)
405#define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW)
406#define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW)
407#define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW)
408#define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW)
409#define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH)
410#define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH)
411#define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH)
412#define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH)
413#define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH)
414#define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH)
415#define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH)
416
417/* PWM */
418#define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW)
419#define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW)
420#define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW)
421#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
422#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
423#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
424
425/* CIR */
426#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1)
427#define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3)
428
429/* USB P2 */
430#define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3)
431#define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5)
432#define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2)
433#define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7)
434#define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6)
435#define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3)
436
437#define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2)
438#define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT)
439#define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2)
440#define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2)
441#define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2)
442#define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2)
443#define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2)
444#define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2)
445
446#define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3)
447#define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3)
448#define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3)
449#define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3)
450#define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3)
451#define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3)
452#define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3)
453#define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3)
454
455/* ULPI */
456#define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4)
457#define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7)
458#define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5)
459#define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5)
460#define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5)
461#define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5)
462#define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5)
463#define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5)
464#define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4)
465#define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4)
466#define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4)
467#define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4)
468
469#define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3)
470#define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7)
471#define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5)
472#define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4)
473#define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3)
474#define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3)
475
476#define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5)
477#define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7)
478#define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5)
479#define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4)
480
481#define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3)
482#define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7)
483#define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3)
484#define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5)
485#define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4)
486#define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3)
487
488/* 1 wire */
489#define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5)
490
491#endif /* __ASM_ARCH_MFP_PXA9xx_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
deleted file mode 100644
index e7d58798da67..000000000000
--- a/include/asm-arm/arch-pxa/mfp.h
+++ /dev/null
@@ -1,319 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp.h
3 *
4 * Multi-Function Pin Definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * 2007-8-21: eric miao <eric.miao@marvell.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_MFP_H
17#define __ASM_ARCH_MFP_H
18
19#define mfp_to_gpio(m) ((m) % 128)
20
21/* list of all the configurable MFP pins */
22enum {
23 MFP_PIN_INVALID = -1,
24
25 MFP_PIN_GPIO0 = 0,
26 MFP_PIN_GPIO1,
27 MFP_PIN_GPIO2,
28 MFP_PIN_GPIO3,
29 MFP_PIN_GPIO4,
30 MFP_PIN_GPIO5,
31 MFP_PIN_GPIO6,
32 MFP_PIN_GPIO7,
33 MFP_PIN_GPIO8,
34 MFP_PIN_GPIO9,
35 MFP_PIN_GPIO10,
36 MFP_PIN_GPIO11,
37 MFP_PIN_GPIO12,
38 MFP_PIN_GPIO13,
39 MFP_PIN_GPIO14,
40 MFP_PIN_GPIO15,
41 MFP_PIN_GPIO16,
42 MFP_PIN_GPIO17,
43 MFP_PIN_GPIO18,
44 MFP_PIN_GPIO19,
45 MFP_PIN_GPIO20,
46 MFP_PIN_GPIO21,
47 MFP_PIN_GPIO22,
48 MFP_PIN_GPIO23,
49 MFP_PIN_GPIO24,
50 MFP_PIN_GPIO25,
51 MFP_PIN_GPIO26,
52 MFP_PIN_GPIO27,
53 MFP_PIN_GPIO28,
54 MFP_PIN_GPIO29,
55 MFP_PIN_GPIO30,
56 MFP_PIN_GPIO31,
57 MFP_PIN_GPIO32,
58 MFP_PIN_GPIO33,
59 MFP_PIN_GPIO34,
60 MFP_PIN_GPIO35,
61 MFP_PIN_GPIO36,
62 MFP_PIN_GPIO37,
63 MFP_PIN_GPIO38,
64 MFP_PIN_GPIO39,
65 MFP_PIN_GPIO40,
66 MFP_PIN_GPIO41,
67 MFP_PIN_GPIO42,
68 MFP_PIN_GPIO43,
69 MFP_PIN_GPIO44,
70 MFP_PIN_GPIO45,
71 MFP_PIN_GPIO46,
72 MFP_PIN_GPIO47,
73 MFP_PIN_GPIO48,
74 MFP_PIN_GPIO49,
75 MFP_PIN_GPIO50,
76 MFP_PIN_GPIO51,
77 MFP_PIN_GPIO52,
78 MFP_PIN_GPIO53,
79 MFP_PIN_GPIO54,
80 MFP_PIN_GPIO55,
81 MFP_PIN_GPIO56,
82 MFP_PIN_GPIO57,
83 MFP_PIN_GPIO58,
84 MFP_PIN_GPIO59,
85 MFP_PIN_GPIO60,
86 MFP_PIN_GPIO61,
87 MFP_PIN_GPIO62,
88 MFP_PIN_GPIO63,
89 MFP_PIN_GPIO64,
90 MFP_PIN_GPIO65,
91 MFP_PIN_GPIO66,
92 MFP_PIN_GPIO67,
93 MFP_PIN_GPIO68,
94 MFP_PIN_GPIO69,
95 MFP_PIN_GPIO70,
96 MFP_PIN_GPIO71,
97 MFP_PIN_GPIO72,
98 MFP_PIN_GPIO73,
99 MFP_PIN_GPIO74,
100 MFP_PIN_GPIO75,
101 MFP_PIN_GPIO76,
102 MFP_PIN_GPIO77,
103 MFP_PIN_GPIO78,
104 MFP_PIN_GPIO79,
105 MFP_PIN_GPIO80,
106 MFP_PIN_GPIO81,
107 MFP_PIN_GPIO82,
108 MFP_PIN_GPIO83,
109 MFP_PIN_GPIO84,
110 MFP_PIN_GPIO85,
111 MFP_PIN_GPIO86,
112 MFP_PIN_GPIO87,
113 MFP_PIN_GPIO88,
114 MFP_PIN_GPIO89,
115 MFP_PIN_GPIO90,
116 MFP_PIN_GPIO91,
117 MFP_PIN_GPIO92,
118 MFP_PIN_GPIO93,
119 MFP_PIN_GPIO94,
120 MFP_PIN_GPIO95,
121 MFP_PIN_GPIO96,
122 MFP_PIN_GPIO97,
123 MFP_PIN_GPIO98,
124 MFP_PIN_GPIO99,
125 MFP_PIN_GPIO100,
126 MFP_PIN_GPIO101,
127 MFP_PIN_GPIO102,
128 MFP_PIN_GPIO103,
129 MFP_PIN_GPIO104,
130 MFP_PIN_GPIO105,
131 MFP_PIN_GPIO106,
132 MFP_PIN_GPIO107,
133 MFP_PIN_GPIO108,
134 MFP_PIN_GPIO109,
135 MFP_PIN_GPIO110,
136 MFP_PIN_GPIO111,
137 MFP_PIN_GPIO112,
138 MFP_PIN_GPIO113,
139 MFP_PIN_GPIO114,
140 MFP_PIN_GPIO115,
141 MFP_PIN_GPIO116,
142 MFP_PIN_GPIO117,
143 MFP_PIN_GPIO118,
144 MFP_PIN_GPIO119,
145 MFP_PIN_GPIO120,
146 MFP_PIN_GPIO121,
147 MFP_PIN_GPIO122,
148 MFP_PIN_GPIO123,
149 MFP_PIN_GPIO124,
150 MFP_PIN_GPIO125,
151 MFP_PIN_GPIO126,
152 MFP_PIN_GPIO127,
153 MFP_PIN_GPIO0_2,
154 MFP_PIN_GPIO1_2,
155 MFP_PIN_GPIO2_2,
156 MFP_PIN_GPIO3_2,
157 MFP_PIN_GPIO4_2,
158 MFP_PIN_GPIO5_2,
159 MFP_PIN_GPIO6_2,
160 MFP_PIN_GPIO7_2,
161 MFP_PIN_GPIO8_2,
162 MFP_PIN_GPIO9_2,
163 MFP_PIN_GPIO10_2,
164 MFP_PIN_GPIO11_2,
165 MFP_PIN_GPIO12_2,
166 MFP_PIN_GPIO13_2,
167 MFP_PIN_GPIO14_2,
168 MFP_PIN_GPIO15_2,
169 MFP_PIN_GPIO16_2,
170 MFP_PIN_GPIO17_2,
171
172 MFP_PIN_ULPI_STP,
173 MFP_PIN_ULPI_NXT,
174 MFP_PIN_ULPI_DIR,
175
176 MFP_PIN_nXCVREN,
177 MFP_PIN_DF_CLE_nOE,
178 MFP_PIN_DF_nADV1_ALE,
179 MFP_PIN_DF_SCLK_E,
180 MFP_PIN_DF_SCLK_S,
181 MFP_PIN_nBE0,
182 MFP_PIN_nBE1,
183 MFP_PIN_DF_nADV2_ALE,
184 MFP_PIN_DF_INT_RnB,
185 MFP_PIN_DF_nCS0,
186 MFP_PIN_DF_nCS1,
187 MFP_PIN_nLUA,
188 MFP_PIN_nLLA,
189 MFP_PIN_DF_nWE,
190 MFP_PIN_DF_ALE_nWE,
191 MFP_PIN_DF_nRE_nOE,
192 MFP_PIN_DF_ADDR0,
193 MFP_PIN_DF_ADDR1,
194 MFP_PIN_DF_ADDR2,
195 MFP_PIN_DF_ADDR3,
196 MFP_PIN_DF_IO0,
197 MFP_PIN_DF_IO1,
198 MFP_PIN_DF_IO2,
199 MFP_PIN_DF_IO3,
200 MFP_PIN_DF_IO4,
201 MFP_PIN_DF_IO5,
202 MFP_PIN_DF_IO6,
203 MFP_PIN_DF_IO7,
204 MFP_PIN_DF_IO8,
205 MFP_PIN_DF_IO9,
206 MFP_PIN_DF_IO10,
207 MFP_PIN_DF_IO11,
208 MFP_PIN_DF_IO12,
209 MFP_PIN_DF_IO13,
210 MFP_PIN_DF_IO14,
211 MFP_PIN_DF_IO15,
212
213 /* additional pins on PXA930 */
214 MFP_PIN_GSIM_UIO,
215 MFP_PIN_GSIM_UCLK,
216 MFP_PIN_GSIM_UDET,
217 MFP_PIN_GSIM_nURST,
218 MFP_PIN_PMIC_INT,
219 MFP_PIN_RDY,
220
221 MFP_PIN_MAX,
222};
223
224/*
225 * a possible MFP configuration is represented by a 32-bit integer
226 *
227 * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
228 * bit 10..12 - Alternate Function Selection
229 * bit 13..15 - Drive Strength
230 * bit 16..18 - Low Power Mode State
231 * bit 19..20 - Low Power Mode Edge Detection
232 * bit 21..22 - Run Mode Pull State
233 *
234 * to facilitate the definition, the following macros are provided
235 *
236 * MFP_CFG_DEFAULT - default MFP configuration value, with
237 * alternate function = 0,
238 * drive strength = fast 3mA (MFP_DS03X)
239 * low power mode = default
240 * edge detection = none
241 *
242 * MFP_CFG - default MFPR value with alternate function
243 * MFP_CFG_DRV - default MFPR value with alternate function and
244 * pin drive strength
245 * MFP_CFG_LPM - default MFPR value with alternate function and
246 * low power mode
247 * MFP_CFG_X - default MFPR value with alternate function,
248 * pin drive strength and low power mode
249 */
250
251typedef unsigned long mfp_cfg_t;
252
253#define MFP_PIN(x) ((x) & 0x3ff)
254
255#define MFP_AF0 (0x0 << 10)
256#define MFP_AF1 (0x1 << 10)
257#define MFP_AF2 (0x2 << 10)
258#define MFP_AF3 (0x3 << 10)
259#define MFP_AF4 (0x4 << 10)
260#define MFP_AF5 (0x5 << 10)
261#define MFP_AF6 (0x6 << 10)
262#define MFP_AF7 (0x7 << 10)
263#define MFP_AF_MASK (0x7 << 10)
264#define MFP_AF(x) (((x) >> 10) & 0x7)
265
266#define MFP_DS01X (0x0 << 13)
267#define MFP_DS02X (0x1 << 13)
268#define MFP_DS03X (0x2 << 13)
269#define MFP_DS04X (0x3 << 13)
270#define MFP_DS06X (0x4 << 13)
271#define MFP_DS08X (0x5 << 13)
272#define MFP_DS10X (0x6 << 13)
273#define MFP_DS13X (0x7 << 13)
274#define MFP_DS_MASK (0x7 << 13)
275#define MFP_DS(x) (((x) >> 13) & 0x7)
276
277#define MFP_LPM_INPUT (0x0 << 16)
278#define MFP_LPM_DRIVE_LOW (0x1 << 16)
279#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
280#define MFP_LPM_PULL_LOW (0x3 << 16)
281#define MFP_LPM_PULL_HIGH (0x4 << 16)
282#define MFP_LPM_FLOAT (0x5 << 16)
283#define MFP_LPM_STATE_MASK (0x7 << 16)
284#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
285
286#define MFP_LPM_EDGE_NONE (0x0 << 19)
287#define MFP_LPM_EDGE_RISE (0x1 << 19)
288#define MFP_LPM_EDGE_FALL (0x2 << 19)
289#define MFP_LPM_EDGE_BOTH (0x3 << 19)
290#define MFP_LPM_EDGE_MASK (0x3 << 19)
291#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
292
293#define MFP_PULL_NONE (0x0 << 21)
294#define MFP_PULL_LOW (0x1 << 21)
295#define MFP_PULL_HIGH (0x2 << 21)
296#define MFP_PULL_BOTH (0x3 << 21)
297#define MFP_PULL_MASK (0x3 << 21)
298#define MFP_PULL(x) (((x) >> 21) & 0x3)
299
300#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
301 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
302
303#define MFP_CFG(pin, af) \
304 ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
305 (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
306
307#define MFP_CFG_DRV(pin, af, drv) \
308 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
309 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
310
311#define MFP_CFG_LPM(pin, af, lpm) \
312 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
313 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
314
315#define MFP_CFG_X(pin, af, drv, lpm) \
316 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
317 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
318
319#endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
deleted file mode 100644
index 6d1304c9270f..000000000000
--- a/include/asm-arm/arch-pxa/mmc.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#ifndef ASMARM_ARCH_MMC_H
2#define ASMARM_ARCH_MMC_H
3
4#include <linux/mmc/host.h>
5#include <linux/interrupt.h>
6
7struct device;
8struct mmc_host;
9
10struct pxamci_platform_data {
11 unsigned int ocr_mask; /* available voltages */
12 unsigned long detect_delay; /* delay in jiffies before detecting cards after interrupt */
13 int (*init)(struct device *, irq_handler_t , void *);
14 int (*get_ro)(struct device *);
15 void (*setpower)(struct device *, unsigned int);
16 void (*exit)(struct device *, void *);
17};
18
19extern void pxa_set_mci_info(struct pxamci_platform_data *info);
20extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
21extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
22
23#endif
diff --git a/include/asm-arm/arch-pxa/mtd-xip.h b/include/asm-arm/arch-pxa/mtd-xip.h
deleted file mode 100644
index 8704dbceb432..000000000000
--- a/include/asm-arm/arch-pxa/mtd-xip.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Author: Nicolas Pitre
7 * Created: Nov 2, 2004
8 * Copyright: (C) 2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
15 */
16
17#ifndef __ARCH_PXA_MTD_XIP_H__
18#define __ARCH_PXA_MTD_XIP_H__
19
20#include <asm/arch/pxa-regs.h>
21
22#define xip_irqpending() (ICIP & ICMR)
23
24/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
25#define xip_currtime() (OSCR)
26#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
27
28/*
29 * xip_cpu_idle() is used when waiting for a delay equal or larger than
30 * the system timer tick period. This should put the CPU into idle mode
31 * to save power and to be woken up only when some interrupts are pending.
32 * As above, this should not rely upon standard kernel code.
33 */
34
35#define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
36
37#endif /* __ARCH_PXA_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-pxa/ohci.h b/include/asm-arm/arch-pxa/ohci.h
deleted file mode 100644
index e848a47128cd..000000000000
--- a/include/asm-arm/arch-pxa/ohci.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef ASMARM_ARCH_OHCI_H
2#define ASMARM_ARCH_OHCI_H
3
4struct device;
5
6struct pxaohci_platform_data {
7 int (*init)(struct device *);
8 void (*exit)(struct device *);
9
10 int port_mode;
11#define PMM_NPS_MODE 1
12#define PMM_GLOBAL_MODE 2
13#define PMM_PERPORT_MODE 3
14
15 int power_budget;
16};
17
18extern void pxa_set_ohci_info(struct pxaohci_platform_data *info);
19
20#endif
diff --git a/include/asm-arm/arch-pxa/palmtx.h b/include/asm-arm/arch-pxa/palmtx.h
deleted file mode 100644
index 1e8bccbda510..000000000000
--- a/include/asm-arm/arch-pxa/palmtx.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * GPIOs and interrupts for Palm T|X Handheld Computer
3 *
4 * Based on palmld-gpio.h by Alex Osborne
5 *
6 * Authors: Marek Vasut <marek.vasut@gmail.com>
7 * Cristiano P. <cristianop@users.sourceforge.net>
8 * Jan Herman <2hp@seznam.cz>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#ifndef _INCLUDE_PALMTX_H_
17#define _INCLUDE_PALMTX_H_
18
19/** HERE ARE GPIOs **/
20
21/* GPIOs */
22#define GPIO_NR_PALMTX_GPIO_RESET 1
23
24#define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */
25#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10
26#define GPIO_NR_PALMTX_EARPHONE_DETECT 107
27
28/* SD/MMC */
29#define GPIO_NR_PALMTX_SD_DETECT_N 14
30#define GPIO_NR_PALMTX_SD_POWER 114 /* probably */
31#define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */
32
33/* TOUCHSCREEN */
34#define GPIO_NR_PALMTX_WM9712_IRQ 27
35
36/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
37#define GPIO_NR_PALMTX_IR_DISABLE 40
38
39/* USB */
40#define GPIO_NR_PALMTX_USB_DETECT_N 13
41#define GPIO_NR_PALMTX_USB_POWER 95
42#define GPIO_NR_PALMTX_USB_PULLUP 93
43
44/* LCD/BACKLIGHT */
45#define GPIO_NR_PALMTX_BL_POWER 84
46#define GPIO_NR_PALMTX_LCD_POWER 96
47
48/* LCD BORDER */
49#define GPIO_NR_PALMTX_BORDER_SWITCH 98
50#define GPIO_NR_PALMTX_BORDER_SELECT 22
51
52/* BLUETOOTH */
53#define GPIO_NR_PALMTX_BT_POWER 17
54#define GPIO_NR_PALMTX_BT_RESET 83
55
56/* PCMCIA (WiFi) */
57#define GPIO_NR_PALMTX_PCMCIA_POWER1 94
58#define GPIO_NR_PALMTX_PCMCIA_POWER2 108
59#define GPIO_NR_PALMTX_PCMCIA_RESET 79
60#define GPIO_NR_PALMTX_PCMCIA_READY 116
61
62/* NAND Flash ... this GPIO may be incorrect! */
63#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79
64
65/* INTERRUPTS */
66#define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N)
67#define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ)
68#define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT)
69#define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET)
70
71/** HERE ARE INIT VALUES **/
72
73/* Various addresses */
74#define PALMTX_PCMCIA_PHYS 0x28000000
75#define PALMTX_PCMCIA_VIRT 0xf0000000
76#define PALMTX_PCMCIA_SIZE 0x100000
77
78#define PALMTX_PHYS_RAM_START 0xa0000000
79#define PALMTX_PHYS_IO_START 0x40000000
80
81#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
82#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */
83
84/* TOUCHSCREEN */
85#define AC97_LINK_FRAME 21
86
87
88/* BATTERY */
89#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
90#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
91#define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */
92#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */
93#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */
94#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */
95#define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */
96
97#define PALMTX_BAT_MEASURE_DELAY (HZ * 1)
98
99/* BACKLIGHT */
100#define PALMTX_MAX_INTENSITY 0xFE
101#define PALMTX_DEFAULT_INTENSITY 0x7E
102#define PALMTX_LIMIT_MASK 0x7F
103#define PALMTX_PRESCALER 0x3F
104#define PALMTX_PERIOD_NS 3500
105
106#endif
diff --git a/include/asm-arm/arch-pxa/pcm027.h b/include/asm-arm/arch-pxa/pcm027.h
deleted file mode 100644
index 7beae1472c3e..000000000000
--- a/include/asm-arm/arch-pxa/pcm027.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pcm027.h
3 *
4 * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
5 * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
23 * Definitions of CPU card resources only
24 */
25
26/* I2C RTC */
27#define PCM027_RTC_IRQ_GPIO 0
28#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
29#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
30#define ADR_PCM027_RTC 0x51 /* I2C address */
31
32/* I2C EEPROM */
33#define ADR_PCM027_EEPROM 0x54 /* I2C address */
34
35/* Ethernet chip (SMSC91C111) */
36#define PCM027_ETH_IRQ_GPIO 52
37#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
38#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING
39#define PCM027_ETH_PHYS PXA_CS5_PHYS
40#define PCM027_ETH_SIZE (1*1024*1024)
41
42/* CAN controller SJA1000 (unsupported yet) */
43#define PCM027_CAN_IRQ_GPIO 114
44#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
45#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
46#define PCM027_CAN_PHYS 0x22000000
47#define PCM027_CAN_SIZE 0x100
48
49/* SPI GPIO expander (unsupported yet) */
50#define PCM027_EGPIO_IRQ_GPIO 27
51#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
52#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
53#define PCM027_EGPIO_CS 24
54/*
55 * TODO: Switch this pin from dedicated usage to GPIO if
56 * more than the MAX7301 device is connected to this SPI bus
57 */
58#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD
59
60/* Flash memory */
61#define PCM027_FLASH_PHYS 0x00000000
62#define PCM027_FLASH_SIZE 0x02000000
63
64/* onboard LEDs connected to GPIO */
65#define PCM027_LED_CPU 90
66#define PCM027_LED_HEARD_BEAT 91
67
68/*
69 * This CPU module needs a baseboard to work. After basic initializing
70 * its own devices, it calls baseboard's init function.
71 * TODO: Add your own basebaord init function and call it from
72 * inside pcm027_init(). This example here is for the developmen board.
73 * Refer pcm990-baseboard.c
74 */
75extern void pcm990_baseboard_init(void);
diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h
deleted file mode 100644
index 2e2013179063..000000000000
--- a/include/asm-arm/arch-pxa/pcm990_baseboard.h
+++ /dev/null
@@ -1,275 +0,0 @@
1/*
2 * include/asm-arm/arch-pxa/pcm990_baseboard.h
3 *
4 * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
5 * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <asm/arch/pcm027.h>
23
24/*
25 * definitions relevant only when the PCM-990
26 * development base board is in use
27 */
28
29/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
30#define PCM990_CTRL_INT_IRQ_GPIO 9
31#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
32#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING
33#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
34#define PCM990_CTRL_BASE 0xea000000
35#define PCM990_CTRL_SIZE (1*1024*1024)
36
37#define PCM990_CTRL_PWR_IRQ_GPIO 14
38#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
39#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING
40
41/* visible CPLD (U7) registers */
42#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
43#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
44#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
45#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
46
47#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
48#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
49#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
50#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
51
52#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
53#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
54#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */
55#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */
56
57#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */
58#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */
59#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
60#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */
61#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */
62
63#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */
64#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */
65
66#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */
67#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */
68#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */
69#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */
70#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */
71
72#define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */
73#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */
74#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */
75#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */
76#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */
77
78#define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */
79#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */
80#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */
81#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */
82#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */
83
84#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */
85#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */
86#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */
87#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */
88#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */
89
90#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */
91#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */
92#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */
93#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */
94
95#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */
96#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */
97#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */
98
99#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */
100#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */
101#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */
102#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */
103#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */
104
105#define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
106#define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
107
108#ifndef __ASSEMBLY__
109# define __PCM990_CTRL_REG(x) \
110 (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
111#else
112# define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x)
113#endif
114
115#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
116#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
117#define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
118#define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
119#define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
120#define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
121#define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
122#define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
123#define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
124#define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
125#define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
126#define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
127#define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
128#define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
129
130
131/*
132 * IDE
133 */
134#define PCM990_IDE_IRQ_GPIO 13
135#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
136#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
137#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
138#define PCM990_IDE_PLD_BASE 0xee000000
139#define PCM990_IDE_PLD_SIZE (1*1024*1024)
140
141/* visible CPLD (U6) registers */
142#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */
143#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */
144#define PCM990_IDE_STBY 0x0008 /* R System StandBy */
145
146#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */
147#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */
148#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */
149#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */
150
151#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */
152#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */
153#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */
154#define PCM990_IDE_RDY 0x0008 /* RDY */
155
156#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */
157#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
158#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
159#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
160
161#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */
162#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */
163#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */
164#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */
165
166#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
167#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
168
169#ifndef __ASSEMBLY__
170# define __PCM990_IDE_PLD_REG(x) \
171 (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
172#else
173# define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x)
174#endif
175
176#define PCM990_IDE0 \
177 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
178#define PCM990_IDE1 \
179 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
180#define PCM990_IDE2 \
181 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
182#define PCM990_IDE3 \
183 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
184#define PCM990_IDE4 \
185 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
186
187/*
188 * Compact Flash
189 */
190#define PCM990_CF_IRQ_GPIO 11
191#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
192#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING
193
194#define PCM990_CF_CD_GPIO 12
195#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
196#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING
197
198#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
199#define PCM990_CF_PLD_BASE 0xef000000
200#define PCM990_CF_PLD_SIZE (1*1024*1024)
201#define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
202#define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
203
204/* visible CPLD (U6) registers */
205#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */
206#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */
207#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */
208#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */
209#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */
210
211#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */
212#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */
213#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */
214
215#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */
216#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */
217#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */
218#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */
219
220#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */
221#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
222#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
223#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
224#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
225
226#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */
227#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */
228#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
229#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */
230#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */
231
232#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */
233#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */
234#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */
235#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */
236#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */
237
238#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */
239#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */
240#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */
241
242#ifndef __ASSEMBLY__
243# define __PCM990_CF_PLD_REG(x) \
244 (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
245#else
246# define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x)
247#endif
248
249#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
250#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
251#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
252#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
253#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
254#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
255#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
256
257/*
258 * Wolfson AC97 Touch
259 */
260#define PCM990_AC97_IRQ_GPIO 10
261#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
262#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING
263
264/*
265 * MMC phyCORE
266 */
267#define PCM990_MMC0_IRQ_GPIO 9
268#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
269#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
270
271/*
272 * USB phyCore
273 */
274#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
275#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h
deleted file mode 100644
index 261e5bc958db..000000000000
--- a/include/asm-arm/arch-pxa/pm.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Copyright (c) 2005 Richard Purdie
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/suspend.h>
11
12struct pxa_cpu_pm_fns {
13 int save_count;
14 void (*save)(unsigned long *);
15 void (*restore)(unsigned long *);
16 int (*valid)(suspend_state_t state);
17 void (*enter)(suspend_state_t state);
18};
19
20extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
21
22/* sleep.S */
23extern void pxa25x_cpu_suspend(unsigned int);
24extern void pxa27x_cpu_suspend(unsigned int);
25extern void pxa_cpu_resume(void);
26
27extern int pxa_pm_enter(suspend_state_t state);
diff --git a/include/asm-arm/arch-pxa/poodle.h b/include/asm-arm/arch-pxa/poodle.h
deleted file mode 100644
index 4d6a40315764..000000000000
--- a/include/asm-arm/arch-pxa/poodle.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/poodle.h
3 *
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 * Based on:
8 * linux/include/asm-arm/arch-sa1100/collie.h
9 *
10 * ChangeLog:
11 * 04-06-2001 Lineo Japan, Inc.
12 * 04-16-2001 SHARP Corporation
13 * Update to 2.6 John Lenz
14 */
15#ifndef __ASM_ARCH_POODLE_H
16#define __ASM_ARCH_POODLE_H 1
17
18/*
19 * GPIOs
20 */
21/* PXA GPIOs */
22#define POODLE_GPIO_ON_KEY (0)
23#define POODLE_GPIO_AC_IN (1)
24#define POODLE_GPIO_CO 16
25#define POODLE_GPIO_TP_INT (5)
26#define POODLE_GPIO_WAKEUP (11) /* change battery */
27#define POODLE_GPIO_GA_INT (10)
28#define POODLE_GPIO_IR_ON (22)
29#define POODLE_GPIO_HP_IN (4)
30#define POODLE_GPIO_CF_IRQ (17)
31#define POODLE_GPIO_CF_CD (14)
32#define POODLE_GPIO_CF_STSCHG (14)
33#define POODLE_GPIO_SD_PWR (33)
34#define POODLE_GPIO_SD_PWR1 (3)
35#define POODLE_GPIO_nSD_CLK (6)
36#define POODLE_GPIO_nSD_WP (7)
37#define POODLE_GPIO_nSD_INT (8)
38#define POODLE_GPIO_nSD_DETECT (9)
39#define POODLE_GPIO_MAIN_BAT_LOW (13)
40#define POODLE_GPIO_BAT_COVER (13)
41#define POODLE_GPIO_USB_PULLUP (20)
42#define POODLE_GPIO_ADC_TEMP_ON (21)
43#define POODLE_GPIO_BYPASS_ON (36)
44#define POODLE_GPIO_CHRG_ON (38)
45#define POODLE_GPIO_CHRG_FULL (16)
46#define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */
47
48/* PXA GPIOs */
49#define POODLE_IRQ_GPIO_ON_KEY IRQ_GPIO(0)
50#define POODLE_IRQ_GPIO_AC_IN IRQ_GPIO(1)
51#define POODLE_IRQ_GPIO_HP_IN IRQ_GPIO(4)
52#define POODLE_IRQ_GPIO_CO IRQ_GPIO(16)
53#define POODLE_IRQ_GPIO_TP_INT IRQ_GPIO(5)
54#define POODLE_IRQ_GPIO_WAKEUP IRQ_GPIO(11)
55#define POODLE_IRQ_GPIO_GA_INT IRQ_GPIO(10)
56#define POODLE_IRQ_GPIO_CF_IRQ IRQ_GPIO(17)
57#define POODLE_IRQ_GPIO_CF_CD IRQ_GPIO(14)
58#define POODLE_IRQ_GPIO_nSD_INT IRQ_GPIO(8)
59#define POODLE_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9)
60#define POODLE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(13)
61
62/* SCOOP GPIOs */
63#define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11
64#define POODLE_SCOOP_CP401 SCOOP_GPCR_PA13
65#define POODLE_SCOOP_VPEN SCOOP_GPCR_PA18
66#define POODLE_SCOOP_L_PCLK SCOOP_GPCR_PA20
67#define POODLE_SCOOP_L_LCLK SCOOP_GPCR_PA21
68#define POODLE_SCOOP_HS_OUT SCOOP_GPCR_PA22
69
70#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
71#define POODLE_SCOOP_IO_OUT ( 0 )
72
73extern struct platform_device poodle_locomo_device;
74
75#endif /* __ASM_ARCH_POODLE_H */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
deleted file mode 100644
index dce9308626b7..000000000000
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ /dev/null
@@ -1,1070 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __PXA_REGS_H
14#define __PXA_REGS_H
15
16
17/*
18 * PXA Chip selects
19 */
20
21#define PXA_CS0_PHYS 0x00000000
22#define PXA_CS1_PHYS 0x04000000
23#define PXA_CS2_PHYS 0x08000000
24#define PXA_CS3_PHYS 0x0C000000
25#define PXA_CS4_PHYS 0x10000000
26#define PXA_CS5_PHYS 0x14000000
27
28
29/*
30 * Personal Computer Memory Card International Association (PCMCIA) sockets
31 */
32
33#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
34#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
35#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
36#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
37#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
38
39#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
40#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
41#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
42#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
43
44#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
45#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
46#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
47#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
48
49#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
50 (0x20000000 + (Nb)*PCMCIASp)
51#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
52#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
53 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
54#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
55 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
56
57#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
58#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
59#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
60#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
61
62#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
63#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
64#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
65#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
66
67
68
69/*
70 * DMA Controller
71 */
72
73#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
74#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
75#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
76#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
77#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
78#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
79#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
80#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
81#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
82#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
83#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
84#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
85#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
86#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
87#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
88#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
89
90#define DCSR(x) __REG2(0x40000000, (x) << 2)
91
92#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
93#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
94#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
95#ifdef CONFIG_PXA27x
96#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
97#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
98#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
99#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
100#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
101#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
102#define DCSR_EORINTR (1 << 9) /* The end of Receive */
103#endif
104#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
105#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
106#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
107#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
108#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
109
110#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
111#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
112
113#define DRCMR(n) (*(((n) < 64) ? \
114 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
115 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
116
117#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
118#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
119#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
120#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
121#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
122#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
123#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
124#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
125#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
126#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
127#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
128#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
129#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
130#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
131#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
132#define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
133#define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
134#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
135#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
136#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
137#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
138#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
139#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
140#define DRCMR23 __REG(0x4000015c) /* Reserved */
141#define DRCMR24 __REG(0x40000160) /* Reserved */
142#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
143#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
144#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
145#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
146#define DRCMR29 __REG(0x40000174) /* Reserved */
147#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
148#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
149#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
150#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
151#define DRCMR34 __REG(0x40000188) /* Reserved */
152#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
153#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
154#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
155#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
156#define DRCMR39 __REG(0x4000019C) /* Reserved */
157#define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
158#define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
159#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
160#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
161#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
162
163#define DRCMRRXSADR DRCMR2
164#define DRCMRTXSADR DRCMR3
165#define DRCMRRXBTRBR DRCMR4
166#define DRCMRTXBTTHR DRCMR5
167#define DRCMRRXFFRBR DRCMR6
168#define DRCMRTXFFTHR DRCMR7
169#define DRCMRRXMCDR DRCMR8
170#define DRCMRRXMODR DRCMR9
171#define DRCMRTXMODR DRCMR10
172#define DRCMRRXPCDR DRCMR11
173#define DRCMRTXPCDR DRCMR12
174#define DRCMRRXSSDR DRCMR13
175#define DRCMRTXSSDR DRCMR14
176#define DRCMRRXSS2DR DRCMR15
177#define DRCMRTXSS2DR DRCMR16
178#define DRCMRRXICDR DRCMR17
179#define DRCMRTXICDR DRCMR18
180#define DRCMRRXSTRBR DRCMR19
181#define DRCMRTXSTTHR DRCMR20
182#define DRCMRRXMMC DRCMR21
183#define DRCMRTXMMC DRCMR22
184#define DRCMRRXSS3DR DRCMR66
185#define DRCMRTXSS3DR DRCMR67
186#define DRCMRUDC(x) DRCMR((x) + 24)
187
188#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
189#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
190
191#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
192#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
193#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
194#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
195#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
196#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
197#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
198#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
199#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
200#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
201#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
202#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
203#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
204#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
205#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
206#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
207#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
208#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
209#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
210#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
211#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
212#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
213#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
214#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
215#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
216#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
217#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
218#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
219#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
220#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
221#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
222#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
223#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
224#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
225#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
226#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
227#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
228#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
229#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
230#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
231#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
232#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
233#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
234#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
235#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
236#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
237#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
238#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
239#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
240#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
241#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
242#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
243#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
244#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
245#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
246#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
247#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
248#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
249#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
250#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
251#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
252#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
253#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
254#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
255
256#define DDADR(x) __REG2(0x40000200, (x) << 4)
257#define DSADR(x) __REG2(0x40000204, (x) << 4)
258#define DTADR(x) __REG2(0x40000208, (x) << 4)
259#define DCMD(x) __REG2(0x4000020c, (x) << 4)
260
261#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
262#define DDADR_STOP (1 << 0) /* Stop (read / write) */
263
264#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
265#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
266#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
267#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
268#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
269#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
270#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
271#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
272#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
273#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
274#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
275#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
276#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
277#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
278
279
280/*
281 * UARTs
282 */
283
284/* Full Function UART (FFUART) */
285#define FFUART FFRBR
286#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
287#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
288#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
289#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
290#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
291#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
292#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
293#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
294#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
295#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
296#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
297#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
298#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
299
300/* Bluetooth UART (BTUART) */
301#define BTUART BTRBR
302#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
303#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
304#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
305#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
306#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
307#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
308#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
309#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
310#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
311#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
312#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
313#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
314#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
315
316/* Standard UART (STUART) */
317#define STUART STRBR
318#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
319#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
320#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
321#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
322#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
323#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
324#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
325#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
326#define STMSR __REG(0x40700018) /* Reserved */
327#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
328#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
329#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
330#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
331
332/* Hardware UART (HWUART) */
333#define HWUART HWRBR
334#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
335#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
336#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
337#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
338#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
339#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
340#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
341#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
342#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
343#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
344#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
345#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
346#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
347#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
348#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
349#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
350
351#define IER_DMAE (1 << 7) /* DMA Requests Enable */
352#define IER_UUE (1 << 6) /* UART Unit Enable */
353#define IER_NRZE (1 << 5) /* NRZ coding Enable */
354#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
355#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
356#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
357#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
358#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
359
360#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
361#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
362#define IIR_TOD (1 << 3) /* Time Out Detected */
363#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
364#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
365#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
366
367#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
368#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
369#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
370#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
371#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
372#define FCR_ITL_1 (0)
373#define FCR_ITL_8 (FCR_ITL1)
374#define FCR_ITL_16 (FCR_ITL2)
375#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
376
377#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
378#define LCR_SB (1 << 6) /* Set Break */
379#define LCR_STKYP (1 << 5) /* Sticky Parity */
380#define LCR_EPS (1 << 4) /* Even Parity Select */
381#define LCR_PEN (1 << 3) /* Parity Enable */
382#define LCR_STB (1 << 2) /* Stop Bit */
383#define LCR_WLS1 (1 << 1) /* Word Length Select */
384#define LCR_WLS0 (1 << 0) /* Word Length Select */
385
386#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
387#define LSR_TEMT (1 << 6) /* Transmitter Empty */
388#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
389#define LSR_BI (1 << 4) /* Break Interrupt */
390#define LSR_FE (1 << 3) /* Framing Error */
391#define LSR_PE (1 << 2) /* Parity Error */
392#define LSR_OE (1 << 1) /* Overrun Error */
393#define LSR_DR (1 << 0) /* Data Ready */
394
395#define MCR_LOOP (1 << 4)
396#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
397#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
398#define MCR_RTS (1 << 1) /* Request to Send */
399#define MCR_DTR (1 << 0) /* Data Terminal Ready */
400
401#define MSR_DCD (1 << 7) /* Data Carrier Detect */
402#define MSR_RI (1 << 6) /* Ring Indicator */
403#define MSR_DSR (1 << 5) /* Data Set Ready */
404#define MSR_CTS (1 << 4) /* Clear To Send */
405#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
406#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
407#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
408#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
409
410/*
411 * IrSR (Infrared Selection Register)
412 */
413#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
414#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
415#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
416#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
417#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
418
419
420/*
421 * I2C registers
422 */
423
424#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
425#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
426#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
427#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
428#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
429
430#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
431#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
432#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
433#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
434#define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
435
436#define ICR_START (1 << 0) /* start bit */
437#define ICR_STOP (1 << 1) /* stop bit */
438#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
439#define ICR_TB (1 << 3) /* transfer byte bit */
440#define ICR_MA (1 << 4) /* master abort */
441#define ICR_SCLE (1 << 5) /* master clock enable */
442#define ICR_IUE (1 << 6) /* unit enable */
443#define ICR_GCD (1 << 7) /* general call disable */
444#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
445#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
446#define ICR_BEIE (1 << 10) /* enable bus error ints */
447#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
448#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
449#define ICR_SADIE (1 << 13) /* slave address detected int enable */
450#define ICR_UR (1 << 14) /* unit reset */
451
452#define ISR_RWM (1 << 0) /* read/write mode */
453#define ISR_ACKNAK (1 << 1) /* ack/nak status */
454#define ISR_UB (1 << 2) /* unit busy */
455#define ISR_IBB (1 << 3) /* bus busy */
456#define ISR_SSD (1 << 4) /* slave stop detected */
457#define ISR_ALD (1 << 5) /* arbitration loss detected */
458#define ISR_ITE (1 << 6) /* tx buffer empty */
459#define ISR_IRF (1 << 7) /* rx buffer full */
460#define ISR_GCAD (1 << 8) /* general call address detected */
461#define ISR_SAD (1 << 9) /* slave address detected */
462#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
463
464
465/*
466 * Serial Audio Controller
467 */
468
469#define SACR0 __REG(0x40400000) /* Global Control Register */
470#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
471#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
472#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
473#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
474#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
475#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
476
477#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
478#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
479#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
480#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
481#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
482#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
483#define SACR0_ENB (1 << 0) /* Enable I2S Link */
484#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
485#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
486#define SACR1_DREC (1 << 3) /* Disable Recording Function */
487#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
488
489#define SASR0_I2SOFF (1 << 7) /* Controller Status */
490#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
491#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
492#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
493#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
494#define SASR0_BSY (1 << 2) /* I2S Busy */
495#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
496#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
497
498#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
499#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
500
501#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
502#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
503#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
504#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
505
506/*
507 * AC97 Controller registers
508 */
509
510#define POCR __REG(0x40500000) /* PCM Out Control Register */
511#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
512#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
513
514#define PICR __REG(0x40500004) /* PCM In Control Register */
515#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
516#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
517
518#define MCCR __REG(0x40500008) /* Mic In Control Register */
519#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
520#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
521
522#define GCR __REG(0x4050000C) /* Global Control Register */
523#ifdef CONFIG_PXA3xx
524#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
525#endif
526#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
527#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
528#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
529#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
530#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
531#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
532#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
533#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
534#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
535#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
536#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
537
538#define POSR __REG(0x40500010) /* PCM Out Status Register */
539#define POSR_FIFOE (1 << 4) /* FIFO error */
540#define POSR_FSR (1 << 2) /* FIFO Service Request */
541
542#define PISR __REG(0x40500014) /* PCM In Status Register */
543#define PISR_FIFOE (1 << 4) /* FIFO error */
544#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
545#define PISR_FSR (1 << 2) /* FIFO Service Request */
546
547#define MCSR __REG(0x40500018) /* Mic In Status Register */
548#define MCSR_FIFOE (1 << 4) /* FIFO error */
549#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
550#define MCSR_FSR (1 << 2) /* FIFO Service Request */
551
552#define GSR __REG(0x4050001C) /* Global Status Register */
553#define GSR_CDONE (1 << 19) /* Command Done */
554#define GSR_SDONE (1 << 18) /* Status Done */
555#define GSR_RDCS (1 << 15) /* Read Completion Status */
556#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
557#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
558#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
559#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
560#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
561#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
562#define GSR_PCR (1 << 8) /* Primary Codec Ready */
563#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
564#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
565#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
566#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
567#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
568#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
569#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
570
571#define CAR __REG(0x40500020) /* CODEC Access Register */
572#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
573
574#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
575#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
576
577#define MOCR __REG(0x40500100) /* Modem Out Control Register */
578#define MOCR_FEIE (1 << 3) /* FIFO Error */
579#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
580
581#define MICR __REG(0x40500108) /* Modem In Control Register */
582#define MICR_FEIE (1 << 3) /* FIFO Error */
583#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
584
585#define MOSR __REG(0x40500110) /* Modem Out Status Register */
586#define MOSR_FIFOE (1 << 4) /* FIFO error */
587#define MOSR_FSR (1 << 2) /* FIFO Service Request */
588
589#define MISR __REG(0x40500118) /* Modem In Status Register */
590#define MISR_FIFOE (1 << 4) /* FIFO error */
591#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
592#define MISR_FSR (1 << 2) /* FIFO Service Request */
593
594#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
595
596#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
597#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
598#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
599#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
600
601
602/*
603 * Fast Infrared Communication Port
604 */
605
606#define FICP __REG(0x40800000) /* Start of FICP area */
607#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
608#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
609#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
610#define ICDR __REG(0x4080000c) /* ICP Data Register */
611#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
612#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
613
614#define ICCR0_AME (1 << 7) /* Address match enable */
615#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
616#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
617#define ICCR0_RXE (1 << 4) /* Receive enable */
618#define ICCR0_TXE (1 << 3) /* Transmit enable */
619#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
620#define ICCR0_LBM (1 << 1) /* Loopback mode */
621#define ICCR0_ITR (1 << 0) /* IrDA transmission */
622
623#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
624#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
625#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
626#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
627#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
628#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
629
630#ifdef CONFIG_PXA27x
631#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
632#endif
633#define ICSR0_FRE (1 << 5) /* Framing error */
634#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
635#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
636#define ICSR0_RAB (1 << 2) /* Receiver abort */
637#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
638#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
639
640#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
641#define ICSR1_CRE (1 << 5) /* CRC error */
642#define ICSR1_EOF (1 << 4) /* End of frame */
643#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
644#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
645#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
646#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
647
648
649/*
650 * Real Time Clock
651 */
652
653#define RCNR __REG(0x40900000) /* RTC Count Register */
654#define RTAR __REG(0x40900004) /* RTC Alarm Register */
655#define RTSR __REG(0x40900008) /* RTC Status Register */
656#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
657#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
658
659#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
660#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
661#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
662#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
663#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
664#define RTSR_AL (1 << 0) /* RTC alarm detected */
665
666
667/*
668 * OS Timer & Match Registers
669 */
670
671#define OSMR0 __REG(0x40A00000) /* */
672#define OSMR1 __REG(0x40A00004) /* */
673#define OSMR2 __REG(0x40A00008) /* */
674#define OSMR3 __REG(0x40A0000C) /* */
675#define OSMR4 __REG(0x40A00080) /* */
676#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
677#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
678#define OMCR4 __REG(0x40A000C0) /* */
679#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
680#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
681#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
682
683#define OSSR_M3 (1 << 3) /* Match status channel 3 */
684#define OSSR_M2 (1 << 2) /* Match status channel 2 */
685#define OSSR_M1 (1 << 1) /* Match status channel 1 */
686#define OSSR_M0 (1 << 0) /* Match status channel 0 */
687
688#define OWER_WME (1 << 0) /* Watchdog Match Enable */
689
690#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
691#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
692#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
693#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
694
695
696/*
697 * Pulse Width Modulator
698 */
699
700#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
701#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
702#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
703
704#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
705#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
706#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
707
708
709/*
710 * Interrupt Controller
711 */
712
713#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
714#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
715#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
716#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
717#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
718#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
719
720#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
721#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
722#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
723#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
724#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
725
726/*
727 * General Purpose I/O
728 */
729
730#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
731#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
732#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
733#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
734
735#define GPLR_OFFSET 0x00
736#define GPDR_OFFSET 0x0C
737#define GPSR_OFFSET 0x18
738#define GPCR_OFFSET 0x24
739#define GRER_OFFSET 0x30
740#define GFER_OFFSET 0x3C
741#define GEDR_OFFSET 0x48
742
743#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
744#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
745#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
746
747#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
748#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
749#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
750
751#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
752#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
753#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
754
755#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
756#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
757#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
758
759#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
760#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
761#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
762
763#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
764#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
765#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
766
767#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
768#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
769#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
770
771#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
772#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
773#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
774#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
775#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
776#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
777#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
778#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
779
780#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
781#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
782#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
783#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
784#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
785#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
786#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
787
788/* More handy macros. The argument is a literal GPIO number. */
789
790#define GPIO_bit(x) (1 << ((x) & 0x1f))
791
792#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
793
794/* Interrupt Controller */
795
796#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
797#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
798#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
799#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
800#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
801#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
802#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
803#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
804
805#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
806#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
807#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
808#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
809#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
810#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
811#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
812#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
813 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
814#else
815
816#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
817#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
818#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
819#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
820#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
821#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
822#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
823#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
824
825#endif
826
827/*
828 * Power Manager - see pxa2xx-regs.h
829 */
830
831/*
832 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
833 */
834
835/*
836 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
837 */
838
839/*
840 * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
841 */
842
843#ifdef CONFIG_PXA27x
844
845/* Camera Interface */
846#define CICR0 __REG(0x50000000)
847#define CICR1 __REG(0x50000004)
848#define CICR2 __REG(0x50000008)
849#define CICR3 __REG(0x5000000C)
850#define CICR4 __REG(0x50000010)
851#define CISR __REG(0x50000014)
852#define CIFR __REG(0x50000018)
853#define CITOR __REG(0x5000001C)
854#define CIBR0 __REG(0x50000028)
855#define CIBR1 __REG(0x50000030)
856#define CIBR2 __REG(0x50000038)
857
858#define CICR0_DMAEN (1 << 31) /* DMA request enable */
859#define CICR0_PAR_EN (1 << 30) /* Parity enable */
860#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
861#define CICR0_ENB (1 << 28) /* Camera interface enable */
862#define CICR0_DIS (1 << 27) /* Camera interface disable */
863#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
864#define CICR0_TOM (1 << 9) /* Time-out mask */
865#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
866#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
867#define CICR0_EOLM (1 << 6) /* End-of-line mask */
868#define CICR0_PERRM (1 << 5) /* Parity-error mask */
869#define CICR0_QDM (1 << 4) /* Quick-disable mask */
870#define CICR0_CDM (1 << 3) /* Disable-done mask */
871#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
872#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
873#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
874
875#define CICR1_TBIT (1 << 31) /* Transparency bit */
876#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
877#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
878#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
879#define CICR1_RGB_F (1 << 11) /* RGB format */
880#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
881#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
882#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
883#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
884#define CICR1_DW (0x7 << 0) /* Data width mask */
885
886#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
887 wait count mask */
888#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
889 wait count mask */
890#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
891#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
892 wait count mask */
893#define CICR2_FSW (0x7 << 0) /* Frame stabilization
894 wait count mask */
895
896#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
897 wait count mask */
898#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
899 wait count mask */
900#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
901#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
902 wait count mask */
903#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
904
905#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
906#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
907#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
908#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
909#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
910#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
911#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
912#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
913
914#define CISR_FTO (1 << 15) /* FIFO time-out */
915#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
916#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
917#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
918#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
919#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
920#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
921#define CISR_EOL (1 << 8) /* End of line */
922#define CISR_PAR_ERR (1 << 7) /* Parity error */
923#define CISR_CQD (1 << 6) /* Camera interface quick disable */
924#define CISR_CDD (1 << 5) /* Camera interface disable done */
925#define CISR_SOF (1 << 4) /* Start of frame */
926#define CISR_EOF (1 << 3) /* End of frame */
927#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
928#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
929#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
930
931#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
932#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
933#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
934#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
935#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
936#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
937#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
938#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
939
940#define SRAM_SIZE 0x40000 /* 4x64K */
941
942#define SRAM_MEM_PHYS 0x5C000000
943
944#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
945#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
946
947#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
948#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
949#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
950#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
951
952#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
953#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
954#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
955#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
956
957#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
958#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
959#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
960#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
961
962#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
963#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
964#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
965#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
966
967#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
968#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
969#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
970#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
971
972#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
973
974#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
975#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
976#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
977
978#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
979#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
980#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
981
982#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
983#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
984#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
985
986#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
987#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
988#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
989
990#endif
991
992#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
993/*
994 * UHC: USB Host Controller (OHCI-like) register definitions
995 */
996#define UHC_BASE_PHYS (0x4C000000)
997#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
998#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
999#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
1000#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
1001#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
1002#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
1003#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
1004#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
1005#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
1006#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
1007#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
1008#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
1009#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
1010#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
1011#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
1012#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
1013#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
1014#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
1015
1016#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
1017#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
1018
1019#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
1020#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
1021#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
1022#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
1023#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
1024
1025#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
1026#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
1027#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
1028#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
1029#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
1030#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
1031#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
1032#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
1033#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
1034#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
1035
1036#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
1037#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
1038#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
1039#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
1040#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
1041#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
1042#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
1043#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
1044#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
1045#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
1046#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
1047#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
1048
1049#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
1050#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
1051#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
1052#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
1053#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
1054#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
1055 Interrupt Enable*/
1056#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
1057#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
1058
1059#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
1060
1061#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
1062
1063/* PWRMODE register M field values */
1064
1065#define PWRMODE_IDLE 0x1
1066#define PWRMODE_STANDBY 0x2
1067#define PWRMODE_SLEEP 0x3
1068#define PWRMODE_DEEPSLEEP 0x7
1069
1070#endif
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h
deleted file mode 100644
index 1b80a4805a60..000000000000
--- a/include/asm-arm/arch-pxa/pxa25x-udc.h
+++ /dev/null
@@ -1,163 +0,0 @@
1#ifndef _ASM_ARCH_PXA25X_UDC_H
2#define _ASM_ARCH_PXA25X_UDC_H
3
4#ifdef _ASM_ARCH_PXA27X_UDC_H
5#error "You can't include both PXA25x and PXA27x UDC support"
6#endif
7
8#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
11
12#define UDCCR __REG(0x40600000) /* UDC Control Register */
13#define UDCCR_UDE (1 << 0) /* UDC enable */
14#define UDCCR_UDA (1 << 1) /* UDC active */
15#define UDCCR_RSM (1 << 2) /* Device resume */
16#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
17#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
18#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
19#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
20#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
21
22#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
23#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
24#define UDCCS0_IPR (1 << 1) /* IN packet ready */
25#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
26#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
27#define UDCCS0_SST (1 << 4) /* Sent stall */
28#define UDCCS0_FST (1 << 5) /* Force stall */
29#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
30#define UDCCS0_SA (1 << 7) /* Setup active */
31
32/* Bulk IN - Endpoint 1,6,11 */
33#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
36
37#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
38#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
39#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
40#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
41#define UDCCS_BI_SST (1 << 4) /* Sent stall */
42#define UDCCS_BI_FST (1 << 5) /* Force stall */
43#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
44
45/* Bulk OUT - Endpoint 2,7,12 */
46#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
48#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
49
50#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
51#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
52#define UDCCS_BO_DME (1 << 3) /* DMA enable */
53#define UDCCS_BO_SST (1 << 4) /* Sent stall */
54#define UDCCS_BO_FST (1 << 5) /* Force stall */
55#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
56#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
57
58/* Isochronous IN - Endpoint 3,8,13 */
59#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
60#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
61#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
62
63#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
64#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
65#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
66#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
67#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
68
69/* Isochronous OUT - Endpoint 4,9,14 */
70#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
71#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
72#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
73
74#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
75#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
76#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
77#define UDCCS_IO_DME (1 << 3) /* DMA enable */
78#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
79#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
80
81/* Interrupt IN - Endpoint 5,10,15 */
82#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
83#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
84#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
85
86#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
87#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
88#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
89#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
90#define UDCCS_INT_SST (1 << 4) /* Sent stall */
91#define UDCCS_INT_FST (1 << 5) /* Force stall */
92#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
93
94#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
95#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
96#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
97#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
98#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
99#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
100#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
101#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
102#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
103#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
104#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
105#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
106#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
107#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
108#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
109#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
110#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
111#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
112#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
113#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
114#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
115#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
116#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
117#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
118
119#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
120
121#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
122#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
123#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
124#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
125#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
126#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
127#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
128#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
129
130#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
131
132#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
133#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
134#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
135#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
136#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
137#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
138#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
139#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
140
141#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
142
143#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
144#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
145#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
146#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
147#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
148#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
149#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
150#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
151
152#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
153
154#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
155#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
156#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
157#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
158#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
159#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
160#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
161#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
162
163#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
deleted file mode 100644
index ab1443f8bd89..000000000000
--- a/include/asm-arm/arch-pxa/pxa27x-udc.h
+++ /dev/null
@@ -1,257 +0,0 @@
1#ifndef _ASM_ARCH_PXA27X_UDC_H
2#define _ASM_ARCH_PXA27X_UDC_H
3
4#ifdef _ASM_ARCH_PXA25X_UDC_H
5#error You cannot include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDCCR __REG(0x40600000) /* UDC Control Register */
9#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
10#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
11 Protocol Port Support */
12#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
13 Support */
14#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
15 Enable */
16#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
17#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
18#define UDCCR_ACN_S 11
19#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
20#define UDCCR_AIN_S 8
21#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
22 Setting Number */
23#define UDCCR_AAISN_S 5
24#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
25 Configuration */
26#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
27 Error */
28#define UDCCR_UDR (1 << 2) /* UDC Resume */
29#define UDCCR_UDA (1 << 1) /* UDC Active */
30#define UDCCR_UDE (1 << 0) /* UDC Enable */
31
32#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
33#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
34#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
35#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
36
37#define UDC_INT_FIFOERROR (0x2)
38#define UDC_INT_PACKETCMP (0x1)
39
40#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
41#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
42#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
43#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
44#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
45#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
46
47#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
48#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
49#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
50#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
51#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
52#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
53#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
54#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
55
56#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
57#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
58#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
59#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
60 Rising Edge Interrupt Enable */
61#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
62 Falling Edge Interrupt Enable */
63#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
64 Interrupt Enable */
65#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
66 Interrupt Enable */
67#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
68 Interrupt Enable */
69#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
70 Interrupt Enable */
71#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
72 Interrupt Enable */
73#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
74 Interrupt Enable */
75#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
76 Edge Interrupt Enable */
77#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
78 Edge Interrupt Enable */
79#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
80 Interrupt Enable */
81#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
82 Interrupt Enable */
83
84#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
85#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
86
87#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
88#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
89#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
90#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
91#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
92#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
93#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
94#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
95#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
96#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
97#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
98#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
99#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
100#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */
101
102#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
103#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
104#define UDCCSR0_SA (1 << 7) /* Setup Active */
105#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
106#define UDCCSR0_FST (1 << 5) /* Force Stall */
107#define UDCCSR0_SST (1 << 4) /* Sent Stall */
108#define UDCCSR0_DME (1 << 3) /* DMA Enable */
109#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
110#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
111#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
112
113#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
114#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
115#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
116#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
117#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
118#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
119#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
120#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
121#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
122#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
123#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
124#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
125#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
126#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
127#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
128#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
129#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
130#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
131#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
132#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
133#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
134#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
135#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
136
137#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
138#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
139#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
140#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
141#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
142#define UDCCSR_FST (1 << 5) /* Force STALL */
143#define UDCCSR_SST (1 << 4) /* Sent STALL */
144#define UDCCSR_DME (1 << 3) /* DMA Enable */
145#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
146#define UDCCSR_PC (1 << 1) /* Packet Complete */
147#define UDCCSR_FS (1 << 0) /* FIFO needs service */
148
149#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
150#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
151#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
152#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
153#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
154#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
155#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
156#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
157#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
158#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
159#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
160#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
161#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
162#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
163#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
164#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
165#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
166#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
167#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
168#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
169#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
170#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
171#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
172#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
173#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
174
175#define UDCDN(x) __REG2(0x40600300, (x)<<2)
176#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
177#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
178#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
179#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
180#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
181#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
182#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
183#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
184#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
185#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
186#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
187#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
188#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
189#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
190#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
191#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
192#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
193#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
194#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
195#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
196#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
197#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
198#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
199#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
200#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
201#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
202
203#define UDCCN(x) __REG2(0x40600400, (x)<<2)
204#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
205#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
206#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
207#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
208#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
209#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
210#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
211#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
212#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
213#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
214#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
215#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
216#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
217#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
218#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
219#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
220#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
221#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
222#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
223#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
224#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
225#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
226#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
227
228#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
229#define UDCCONR_CN_S (25)
230#define UDCCONR_IN (0x07 << 22) /* Interface Number */
231#define UDCCONR_IN_S (22)
232#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
233#define UDCCONR_AISN_S (19)
234#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
235#define UDCCONR_EN_S (15)
236#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
237#define UDCCONR_ET_S (13)
238#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
239#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
240#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
241#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
242#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
243#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
244#define UDCCONR_MPS_S (2)
245#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
246#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
247
248
249#define UDC_INT_FIFOERROR (0x2)
250#define UDC_INT_PACKETCMP (0x1)
251
252#define UDC_FNR_MASK (0x7ff)
253
254#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
255#define UDC_BCR_MASK (0x3ff)
256
257#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x_keypad.h b/include/asm-arm/arch-pxa/pxa27x_keypad.h
deleted file mode 100644
index d5a48a96dea7..000000000000
--- a/include/asm-arm/arch-pxa/pxa27x_keypad.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef __ASM_ARCH_PXA27x_KEYPAD_H
2#define __ASM_ARCH_PXA27x_KEYPAD_H
3
4#include <linux/input.h>
5
6#define MAX_MATRIX_KEY_ROWS (8)
7#define MAX_MATRIX_KEY_COLS (8)
8
9/* pxa3xx keypad platform specific parameters
10 *
11 * NOTE:
12 * 1. direct_key_num indicates the number of keys in the direct keypad
13 * _plus_ the number of rotary-encoder sensor inputs, this can be
14 * left as 0 if only rotary encoders are enabled, the driver will
15 * automatically calculate this
16 *
17 * 2. direct_key_map is the key code map for the direct keys, if rotary
18 * encoder(s) are enabled, direct key 0/1(2/3) will be ignored
19 *
20 * 3. rotary can be either interpreted as a relative input event (e.g.
21 * REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT)
22 *
23 * 4. matrix key and direct key will use the same debounce_interval by
24 * default, which should be sufficient in most cases
25 */
26struct pxa27x_keypad_platform_data {
27
28 /* code map for the matrix keys */
29 unsigned int matrix_key_rows;
30 unsigned int matrix_key_cols;
31 unsigned int *matrix_key_map;
32 int matrix_key_map_size;
33
34 /* direct keys */
35 int direct_key_num;
36 unsigned int direct_key_map[8];
37
38 /* rotary encoders 0 */
39 int enable_rotary0;
40 int rotary0_rel_code;
41 int rotary0_up_key;
42 int rotary0_down_key;
43
44 /* rotary encoders 1 */
45 int enable_rotary1;
46 int rotary1_rel_code;
47 int rotary1_up_key;
48 int rotary1_down_key;
49
50 /* key debounce interval */
51 unsigned int debounce_interval;
52};
53
54#define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val))
55
56extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
57
58#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
deleted file mode 100644
index 6ef1dd09970b..000000000000
--- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h
+++ /dev/null
@@ -1,368 +0,0 @@
1#ifndef __ASM_ARCH_PXA2XX_GPIO_H
2#define __ASM_ARCH_PXA2XX_GPIO_H
3
4#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
5
6/* GPIO alternate function assignments */
7
8#define GPIO1_RST 1 /* reset */
9#define GPIO6_MMCCLK 6 /* MMC Clock */
10#define GPIO7_48MHz 7 /* 48 MHz clock output */
11#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
12#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
13#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
14#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
15#define GPIO12_32KHz 12 /* 32 kHz out */
16#define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */
17#define GPIO13_MBGNT 13 /* memory controller grant */
18#define GPIO14_MBREQ 14 /* alternate bus master request */
19#define GPIO15_nCS_1 15 /* chip select 1 */
20#define GPIO16_PWM0 16 /* PWM0 output */
21#define GPIO17_PWM1 17 /* PWM1 output */
22#define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */
23#define GPIO18_RDY 18 /* Ext. Bus Ready */
24#define GPIO19_DREQ1 19 /* External DMA Request */
25#define GPIO20_DREQ0 20 /* External DMA Request */
26#define GPIO23_SCLK 23 /* SSP clock */
27#define GPIO23_CIF_MCLK 23 /* Camera Master Clock */
28#define GPIO24_SFRM 24 /* SSP Frame */
29#define GPIO24_CIF_FV 24 /* Camera frame start signal */
30#define GPIO25_STXD 25 /* SSP transmit */
31#define GPIO25_CIF_LV 25 /* Camera line start signal */
32#define GPIO26_SRXD 26 /* SSP receive */
33#define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */
34#define GPIO27_SEXTCLK 27 /* SSP ext_clk */
35#define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */
36#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
37#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
38#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
39#define GPIO31_SYNC 31 /* AC97/I2S sync */
40#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
41#define GPIO32_SYSCLK 32 /* I2S System Clock */
42#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */
43#define GPIO33_nCS_5 33 /* chip select 5 */
44#define GPIO34_FFRXD 34 /* FFUART receive */
45#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
46#define GPIO35_FFCTS 35 /* FFUART Clear to send */
47#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
48#define GPIO37_FFDSR 37 /* FFUART data set ready */
49#define GPIO38_FFRI 38 /* FFUART Ring Indicator */
50#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
51#define GPIO39_FFTXD 39 /* FFUART transmit data */
52#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
53#define GPIO41_FFRTS 41 /* FFUART request to send */
54#define GPIO42_BTRXD 42 /* BTUART receive data */
55#define GPIO42_HWRXD 42 /* HWUART receive data */
56#define GPIO42_CIF_MCLK 42 /* Camera Master Clock */
57#define GPIO43_BTTXD 43 /* BTUART transmit data */
58#define GPIO43_HWTXD 43 /* HWUART transmit data */
59#define GPIO43_CIF_FV 43 /* Camera frame start signal */
60#define GPIO44_BTCTS 44 /* BTUART clear to send */
61#define GPIO44_HWCTS 44 /* HWUART clear to send */
62#define GPIO44_CIF_LV 44 /* Camera line start signal */
63#define GPIO45_BTRTS 45 /* BTUART request to send */
64#define GPIO45_HWRTS 45 /* HWUART request to send */
65#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
66#define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */
67#define GPIO46_ICPRXD 46 /* ICP receive data */
68#define GPIO46_STRXD 46 /* STD_UART receive data */
69#define GPIO47_ICPTXD 47 /* ICP transmit data */
70#define GPIO47_STTXD 47 /* STD_UART transmit data */
71#define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */
72#define GPIO48_nPOE 48 /* Output Enable for Card Space */
73#define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */
74#define GPIO49_nPWE 49 /* Write Enable for Card Space */
75#define GPIO50_nPIOR 50 /* I/O Read for Card Space */
76#define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */
77#define GPIO51_nPIOW 51 /* I/O Write for Card Space */
78#define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */
79#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
80#define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */
81#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
82#define GPIO53_MMCCLK 53 /* MMC Clock */
83#define GPIO53_CIF_MCLK 53 /* Camera Master Clock */
84#define GPIO54_MMCCLK 54 /* MMC Clock */
85#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
86#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */
87#define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */
88#define GPIO55_nPREG 55 /* Card Address bit 26 */
89#define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */
90#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
91#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
92#define GPIO58_LDD_0 58 /* LCD data pin 0 */
93#define GPIO59_LDD_1 59 /* LCD data pin 1 */
94#define GPIO60_LDD_2 60 /* LCD data pin 2 */
95#define GPIO61_LDD_3 61 /* LCD data pin 3 */
96#define GPIO62_LDD_4 62 /* LCD data pin 4 */
97#define GPIO63_LDD_5 63 /* LCD data pin 5 */
98#define GPIO64_LDD_6 64 /* LCD data pin 6 */
99#define GPIO65_LDD_7 65 /* LCD data pin 7 */
100#define GPIO66_LDD_8 66 /* LCD data pin 8 */
101#define GPIO66_MBREQ 66 /* alternate bus master req */
102#define GPIO67_LDD_9 67 /* LCD data pin 9 */
103#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
104#define GPIO68_LDD_10 68 /* LCD data pin 10 */
105#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
106#define GPIO69_LDD_11 69 /* LCD data pin 11 */
107#define GPIO69_MMCCLK 69 /* MMC_CLK */
108#define GPIO70_LDD_12 70 /* LCD data pin 12 */
109#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
110#define GPIO71_LDD_13 71 /* LCD data pin 13 */
111#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
112#define GPIO72_LDD_14 72 /* LCD data pin 14 */
113#define GPIO72_32kHz 72 /* 32 kHz clock */
114#define GPIO73_LDD_15 73 /* LCD data pin 15 */
115#define GPIO73_MBGNT 73 /* Memory controller grant */
116#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
117#define GPIO75_LCD_LCLK 75 /* LCD line clock */
118#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
119#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
120#define GPIO78_nCS_2 78 /* chip select 2 */
121#define GPIO79_nCS_3 79 /* chip select 3 */
122#define GPIO80_nCS_4 80 /* chip select 4 */
123#define GPIO81_NSCLK 81 /* NSSP clock */
124#define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */
125#define GPIO82_NSFRM 82 /* NSSP Frame */
126#define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */
127#define GPIO83_NSTXD 83 /* NSSP transmit */
128#define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */
129#define GPIO84_NSRXD 84 /* NSSP receive */
130#define GPIO84_CIF_FV 84 /* Camera frame start signal */
131#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
132#define GPIO85_CIF_LV 85 /* Camera line start signal */
133#define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */
134#define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */
135#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
136#define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */
137#define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */
138#define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */
139#define GPIO96_FFRXD 96 /* FFUART recieve */
140#define GPIO98_FFRTS 98 /* FFUART request to send */
141#define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */
142#define GPIO99_FFTXD 99 /* FFUART transmit data */
143#define GPIO100_FFCTS 100 /* FFUART Clear to send */
144#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
145#define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */
146#define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */
147#define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */
148#define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */
149#define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */
150#define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */
151#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
152#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
153#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
154#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
155#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
156#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
157#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */
158#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
159#define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */
160#define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */
161#define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */
162
163/* GPIO alternate function mode & direction */
164
165#define GPIO_IN 0x000
166#define GPIO_OUT 0x080
167#define GPIO_ALT_FN_1_IN 0x100
168#define GPIO_ALT_FN_1_OUT 0x180
169#define GPIO_ALT_FN_2_IN 0x200
170#define GPIO_ALT_FN_2_OUT 0x280
171#define GPIO_ALT_FN_3_IN 0x300
172#define GPIO_ALT_FN_3_OUT 0x380
173#define GPIO_MD_MASK_NR 0x07f
174#define GPIO_MD_MASK_DIR 0x080
175#define GPIO_MD_MASK_FN 0x300
176#define GPIO_DFLT_LOW 0x400
177#define GPIO_DFLT_HIGH 0x800
178
179#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
180#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
181#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)
182#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
183#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
184#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
185#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
186#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
187#define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN)
188#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
189#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
190#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
191#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
192#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
193#define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN)
194#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
195#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
196#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
197#define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT)
198#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
199#define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT)
200#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
201#define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT)
202#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
203#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
204#define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN)
205#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
206#define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN)
207#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
208#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
209#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
210#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
211#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
212#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
213#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
214#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
215#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
216#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
217#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)
218#define GPIO32_MMCCLK_MD (32 | GPIO_ALT_FN_2_OUT)
219#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
220#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
221#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
222#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
223#define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT)
224#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
225#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
226#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
227#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
228#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
229#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
230#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
231#define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT)
232#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
233#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
234#define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT)
235#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
236#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
237#define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT)
238#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
239#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
240#define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT)
241#define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN)
242#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
243#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
244#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
245#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
246#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
247#define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN)
248#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
249#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
250#define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN)
251#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
252#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
253#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
254#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
255#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
256#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
257#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
258#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
259#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
260#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
261#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
262#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
263#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
264#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
265#define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN)
266#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
267#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
268#define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT)
269#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
270#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
271#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
272#define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN)
273#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
274#define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN)
275#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
276#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
277#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
278#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
279#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
280#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
281#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
282#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
283#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
284#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
285#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
286#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
287#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
288#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
289#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
290#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
291#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
292#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
293#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
294#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
295#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
296#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
297#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
298#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
299#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
300#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
301#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
302#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
303#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
304#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
305#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
306#define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT)
307#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
308#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)
309#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
310#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)
311#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)
312#define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN)
313#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)
314#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)
315#define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN)
316#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
317#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
318#define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN)
319#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
320#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
321#define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN)
322#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
323#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN)
324#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT)
325#define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN)
326#define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT)
327#define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN)
328#define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN)
329#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
330#define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN)
331#define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN)
332#define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN)
333#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN)
334#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN)
335#define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN)
336#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN)
337#define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN)
338#define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT)
339#define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT)
340#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN)
341#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN)
342#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
343#define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN)
344#define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN)
345#define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT)
346#define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN)
347#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
348#define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT)
349#define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN)
350#define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT)
351#define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN)
352#define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT)
353#define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN)
354#define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT)
355#define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN)
356#define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT)
357#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
358#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
359#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
360#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
361#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
362#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
363#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
364#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
365#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN)
366#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
367
368#endif /* __ASM_ARCH_PXA2XX_GPIO_H */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
deleted file mode 100644
index 73e0a329cf7f..000000000000
--- a/include/asm-arm/arch-pxa/pxa2xx-regs.h
+++ /dev/null
@@ -1,246 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
3 *
4 * Taken from pxa-regs.h by Russell King
5 *
6 * Author: Nicolas Pitre
7 * Copyright: MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __PXA2XX_REGS_H
15#define __PXA2XX_REGS_H
16
17/*
18 * Memory controller
19 */
20
21#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
22#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
23#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
24#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
25#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
26#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
27#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
28#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
29#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
30#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
31#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
32#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
33#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
34#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
35#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
36#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
37#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
38
39/*
40 * More handy macros for PCMCIA
41 *
42 * Arg is socket number
43 */
44#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
45#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
46#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
47
48/* MECR register defines */
49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
51
52#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
53#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
54#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
55#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
56#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
57#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
58#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
59#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
60#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
61#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
62#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
63#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
64#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
65#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
66
67
68#ifdef CONFIG_PXA27x
69
70#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
71
72#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
73#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
74#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
75#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
76#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
77#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
78#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
79#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
80#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
81
82#endif
83
84
85/*
86 * Power Manager
87 */
88
89#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
90#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
91#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
92#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
93#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
94#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
95#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
96#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
97#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
98#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
99#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
100#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
101#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
102
103#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
104#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
105#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
106#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
107#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
108#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
109#define PCMD(x) __REG2(0x40F00080, (x)<<2)
110#define PCMD0 __REG(0x40F00080 + 0 * 4)
111#define PCMD1 __REG(0x40F00080 + 1 * 4)
112#define PCMD2 __REG(0x40F00080 + 2 * 4)
113#define PCMD3 __REG(0x40F00080 + 3 * 4)
114#define PCMD4 __REG(0x40F00080 + 4 * 4)
115#define PCMD5 __REG(0x40F00080 + 5 * 4)
116#define PCMD6 __REG(0x40F00080 + 6 * 4)
117#define PCMD7 __REG(0x40F00080 + 7 * 4)
118#define PCMD8 __REG(0x40F00080 + 8 * 4)
119#define PCMD9 __REG(0x40F00080 + 9 * 4)
120#define PCMD10 __REG(0x40F00080 + 10 * 4)
121#define PCMD11 __REG(0x40F00080 + 11 * 4)
122#define PCMD12 __REG(0x40F00080 + 12 * 4)
123#define PCMD13 __REG(0x40F00080 + 13 * 4)
124#define PCMD14 __REG(0x40F00080 + 14 * 4)
125#define PCMD15 __REG(0x40F00080 + 15 * 4)
126#define PCMD16 __REG(0x40F00080 + 16 * 4)
127#define PCMD17 __REG(0x40F00080 + 17 * 4)
128#define PCMD18 __REG(0x40F00080 + 18 * 4)
129#define PCMD19 __REG(0x40F00080 + 19 * 4)
130#define PCMD20 __REG(0x40F00080 + 20 * 4)
131#define PCMD21 __REG(0x40F00080 + 21 * 4)
132#define PCMD22 __REG(0x40F00080 + 22 * 4)
133#define PCMD23 __REG(0x40F00080 + 23 * 4)
134#define PCMD24 __REG(0x40F00080 + 24 * 4)
135#define PCMD25 __REG(0x40F00080 + 25 * 4)
136#define PCMD26 __REG(0x40F00080 + 26 * 4)
137#define PCMD27 __REG(0x40F00080 + 27 * 4)
138#define PCMD28 __REG(0x40F00080 + 28 * 4)
139#define PCMD29 __REG(0x40F00080 + 29 * 4)
140#define PCMD30 __REG(0x40F00080 + 30 * 4)
141#define PCMD31 __REG(0x40F00080 + 31 * 4)
142
143#define PCMD_MBC (1<<12)
144#define PCMD_DCE (1<<11)
145#define PCMD_LC (1<<10)
146/* FIXME: PCMD_SQC need be checked. */
147#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
148 bit 9 should be 0 all day. */
149#define PVCR_VCSA (0x1<<14)
150#define PVCR_CommandDelay (0xf80)
151#define PCFR_PI2C_EN (0x1 << 6)
152
153#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
154#define PSSR_RDH (1 << 5) /* Read Disable Hold */
155#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
156#define PSSR_STS (1 << 3) /* Standby Mode Status */
157#define PSSR_VFS (1 << 2) /* VDD Fault Status */
158#define PSSR_BFS (1 << 1) /* Battery Fault Status */
159#define PSSR_SSS (1 << 0) /* Software Sleep Status */
160
161#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
162
163#define PCFR_RO (1 << 15) /* RDH Override */
164#define PCFR_PO (1 << 14) /* PH Override */
165#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
166#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
167#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
168#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
169#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
170#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
171#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
172#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
173#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
174#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
175
176#define RCSR_GPR (1 << 3) /* GPIO Reset */
177#define RCSR_SMR (1 << 2) /* Sleep Mode */
178#define RCSR_WDR (1 << 1) /* Watchdog Reset */
179#define RCSR_HWR (1 << 0) /* Hardware Reset */
180
181#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
182#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
183#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
184#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
185#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
186#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
187#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
188#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
189#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
190#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
191#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
192#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
193#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
194#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
195#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
196#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
197#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
198#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
199
200/*
201 * PXA2xx specific Core clock definitions
202 */
203#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
204#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
205#define CKEN __REG(0x41300004) /* Clock Enable Register */
206#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
207
208#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
209#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
210#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
211
212#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
213#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
214#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
215#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
216#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
217#define CKEN_IM (20) /* Internal Memory Clock Enable */
218#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
219#define CKEN_USIM (18) /* USIM Unit Clock Enable */
220#define CKEN_MSL (17) /* MSL Unit Clock Enable */
221#define CKEN_LCD (16) /* LCD Unit Clock Enable */
222#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
223#define CKEN_I2C (14) /* I2C Unit Clock Enable */
224#define CKEN_FICP (13) /* FICP Unit Clock Enable */
225#define CKEN_MMC (12) /* MMC Unit Clock Enable */
226#define CKEN_USB (11) /* USB Unit Clock Enable */
227#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
228#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
229#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
230#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
231#define CKEN_I2S (8) /* I2S Unit Clock Enable */
232#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
233#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
234#define CKEN_STUART (5) /* STUART Unit Clock Enable */
235#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
236#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
237#define CKEN_SSP (3) /* SSP Unit Clock Enable */
238#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
239#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
240#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
241#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
242
243#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
244#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
245
246#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
deleted file mode 100644
index 2206cb61a9f9..000000000000
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef PXA2XX_SPI_H_
20#define PXA2XX_SPI_H_
21
22#define PXA2XX_CS_ASSERT (0x01)
23#define PXA2XX_CS_DEASSERT (0x02)
24
25/* device.platform_data for SSP controller devices */
26struct pxa2xx_spi_master {
27 u32 clock_enable;
28 u16 num_chipselect;
29 u8 enable_dma;
30};
31
32/* spi_board_info.controller_data for SPI slave devices,
33 * copied to spi_device.platform_data ... mostly for dma tuning
34 */
35struct pxa2xx_spi_chip {
36 u8 tx_threshold;
37 u8 rx_threshold;
38 u8 dma_burst_size;
39 u32 timeout;
40 u8 enable_loopback;
41 void (*cs_control)(u32 command);
42};
43
44extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
45
46#endif /*PXA2XX_SPI_H_*/
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
deleted file mode 100644
index fe9364c83a28..000000000000
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ /dev/null
@@ -1,183 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
3 *
4 * PXA3xx specific register definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_PXA3XX_REGS_H
14#define __ASM_ARCH_PXA3XX_REGS_H
15
16/*
17 * Oscillator Configuration Register (OSCC)
18 */
19#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */
20
21#define OSCC_PEN (1 << 11) /* 13MHz POUT */
22
23
24/*
25 * Service Power Management Unit (MPMU)
26 */
27#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
28#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
29#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
30#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
31#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
32#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
33#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
34#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
35#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
36#define PCMD(x) __REG(0x40F50110 + ((x) << 2))
37
38/*
39 * Slave Power Managment Unit
40 */
41#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
42#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
43#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
44#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
45#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
46#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
47#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
48#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
49#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
50#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
51#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
52#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
53#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
54#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
55
56/*
57 * Application Subsystem Configuration bits.
58 */
59#define ASCR_RDH (1 << 31)
60#define ASCR_D1S (1 << 2)
61#define ASCR_D2S (1 << 1)
62#define ASCR_D3S (1 << 0)
63
64/*
65 * Application Reset Status bits.
66 */
67#define ARSR_GPR (1 << 3)
68#define ARSR_LPMR (1 << 2)
69#define ARSR_WDT (1 << 1)
70#define ARSR_HWR (1 << 0)
71
72/*
73 * Application Subsystem Wake-Up bits.
74 */
75#define ADXER_WRTC (1 << 31) /* RTC */
76#define ADXER_WOST (1 << 30) /* OS Timer */
77#define ADXER_WTSI (1 << 29) /* Touchscreen */
78#define ADXER_WUSBH (1 << 28) /* USB host */
79#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */
80#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/
81#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */
82#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */
83#define ADXER_WKP (1 << 21) /* Keypad */
84#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */
85#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */
86#define ADXER_WOTG (1 << 16) /* USBOTG input */
87#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */
88#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */
89#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */
90#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */
91#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */
92#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */
93#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */
94#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */
95#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */
96#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */
97#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */
98#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */
99#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */
100#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */
101#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */
102#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */
103
104/*
105 * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
106 */
107#define ADXR_L2 (1 << 8)
108#define ADXR_R5 (1 << 5)
109#define ADXR_R4 (1 << 4)
110#define ADXR_R3 (1 << 3)
111#define ADXR_R2 (1 << 2)
112#define ADXR_R1 (1 << 1)
113#define ADXR_R0 (1 << 0)
114
115/*
116 * Values for PWRMODE CP15 register
117 */
118#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */
119#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */
120#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */
121#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */
122#define PXA3xx_PM_S0D0C1 0x01
123
124/*
125 * Application Subsystem Clock
126 */
127#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
128#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
129#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
130#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
131#define CKENB __REG(0x41340010) /* B Clock Enable Register */
132#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
133
134/*
135 * Clock Enable Bit
136 */
137#define CKEN_LCD 1 /* < LCD Clock Enable */
138#define CKEN_USBH 2 /* < USB host clock enable */
139#define CKEN_CAMERA 3 /* < Camera interface clock enable */
140#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
141#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
142#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
143#define CKEN_SMC 9 /* < Static Memory Controller clock enable */
144#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
145#define CKEN_BOOT 11 /* < Boot rom clock enable */
146#define CKEN_MMC1 12 /* < MMC1 Clock enable */
147#define CKEN_MMC2 13 /* < MMC2 clock enable */
148#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
149#define CKEN_CIR 15 /* < Consumer IR Clock Enable */
150#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
151#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
152#define CKEN_TPM 19 /* < TPM clock enable */
153#define CKEN_UDC 20 /* < UDC clock enable */
154#define CKEN_BTUART 21 /* < BTUART clock enable */
155#define CKEN_FFUART 22 /* < FFUART clock enable */
156#define CKEN_STUART 23 /* < STUART clock enable */
157#define CKEN_AC97 24 /* < AC97 clock enable */
158#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
159#define CKEN_SSP1 26 /* < SSP1 clock enable */
160#define CKEN_SSP2 27 /* < SSP2 clock enable */
161#define CKEN_SSP3 28 /* < SSP3 clock enable */
162#define CKEN_SSP4 29 /* < SSP4 clock enable */
163#define CKEN_MSL0 30 /* < MSL0 clock enable */
164#define CKEN_PWM0 32 /* < PWM[0] clock enable */
165#define CKEN_PWM1 33 /* < PWM[1] clock enable */
166#define CKEN_I2C 36 /* < I2C clock enable */
167#define CKEN_INTC 38 /* < Interrupt controller clock enable */
168#define CKEN_GPIO 39 /* < GPIO clock enable */
169#define CKEN_1WIRE 40 /* < 1-wire clock enable */
170#define CKEN_HSIO2 41 /* < HSIO2 clock enable */
171#define CKEN_MINI_IM 48 /* < Mini-IM */
172#define CKEN_MINI_LCD 49 /* < Mini LCD */
173
174#if defined(CONFIG_CPU_PXA310)
175#define CKEN_MMC3 5 /* < MMC3 Clock Enable */
176#define CKEN_MVED 43 /* < MVED clock enable */
177#endif
178
179/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
180#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
181#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */
182
183#endif /* __ASM_ARCH_PXA3XX_REGS_H */
diff --git a/include/asm-arm/arch-pxa/pxa3xx_nand.h b/include/asm-arm/arch-pxa/pxa3xx_nand.h
deleted file mode 100644
index eb4b190b6657..000000000000
--- a/include/asm-arm/arch-pxa/pxa3xx_nand.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __ASM_ARCH_PXA3XX_NAND_H
2#define __ASM_ARCH_PXA3XX_NAND_H
3
4#include <linux/mtd/mtd.h>
5#include <linux/mtd/partitions.h>
6
7struct pxa3xx_nand_platform_data {
8
9 /* the data flash bus is shared between the Static Memory
10 * Controller and the Data Flash Controller, the arbiter
11 * controls the ownership of the bus
12 */
13 int enable_arbiter;
14
15 struct mtd_partition *parts;
16 unsigned int nr_parts;
17};
18
19extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
20#endif /* __ASM_ARCH_PXA3XX_NAND_H */
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
deleted file mode 100644
index daf018d0c604..000000000000
--- a/include/asm-arm/arch-pxa/pxafb.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pxafb.h
3 *
4 * Support for the xscale frame buffer.
5 *
6 * Author: Jean-Frederic Clere
7 * Created: Sep 22, 2003
8 * Copyright: jfclere@sinix.net
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/fb.h>
16#include <asm/arch/regs-lcd.h>
17
18/*
19 * Supported LCD connections
20 *
21 * bits 0 - 3: for LCD panel type:
22 *
23 * STN - for passive matrix
24 * DSTN - for dual scan passive matrix
25 * TFT - for active matrix
26 *
27 * bits 4 - 9 : for bus width
28 * bits 10-17 : for AC Bias Pin Frequency
29 * bit 18 : for output enable polarity
30 * bit 19 : for pixel clock edge
31 */
32#define LCD_CONN_TYPE(_x) ((_x) & 0x0f)
33#define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f)
34
35#define LCD_TYPE_UNKNOWN 0
36#define LCD_TYPE_MONO_STN 1
37#define LCD_TYPE_MONO_DSTN 2
38#define LCD_TYPE_COLOR_STN 3
39#define LCD_TYPE_COLOR_DSTN 4
40#define LCD_TYPE_COLOR_TFT 5
41#define LCD_TYPE_SMART_PANEL 6
42#define LCD_TYPE_MAX 7
43
44#define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN)
45#define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN)
46#define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN)
47#define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN)
48#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
49#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
50#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
51#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
52#define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL)
53#define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL)
54
55#define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
56#define LCD_BIAS_ACTIVE_HIGH (0 << 17)
57#define LCD_BIAS_ACTIVE_LOW (1 << 17)
58#define LCD_PCLK_EDGE_RISE (0 << 18)
59#define LCD_PCLK_EDGE_FALL (1 << 18)
60
61/*
62 * This structure describes the machine which we are running on.
63 * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
64 * of linux/drivers/video/pxafb.c
65 */
66struct pxafb_mode_info {
67 u_long pixclock;
68
69 u_short xres;
70 u_short yres;
71
72 u_char bpp;
73 u_int cmap_greyscale:1,
74 depth:8,
75 unused:23;
76
77 /* Parallel Mode Timing */
78 u_char hsync_len;
79 u_char left_margin;
80 u_char right_margin;
81
82 u_char vsync_len;
83 u_char upper_margin;
84 u_char lower_margin;
85 u_char sync;
86
87 /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
88 * Note:
89 * 1. all parameters in nanosecond (ns)
90 * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
91 * in pxa27x and pxa3xx, initialize them to the same value or
92 * the larger one will be used
93 * 3. same to {rd,wr}_pulse_width
94 */
95 unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
96 unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
97 unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
98 unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
99 unsigned cmd_inh_time; /* Command Inhibit time between two writes */
100 unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
101};
102
103struct pxafb_mach_info {
104 struct pxafb_mode_info *modes;
105 unsigned int num_modes;
106
107 unsigned int lcd_conn;
108
109 u_int fixed_modes:1,
110 cmap_inverse:1,
111 cmap_static:1,
112 unused:29;
113
114 /* The following should be defined in LCCR0
115 * LCCR0_Act or LCCR0_Pas Active or Passive
116 * LCCR0_Sngl or LCCR0_Dual Single/Dual panel
117 * LCCR0_Mono or LCCR0_Color Mono/Color
118 * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
119 * LCCR0_DMADel(Tcpu) (optional) DMA request delay
120 *
121 * The following should not be defined in LCCR0:
122 * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
123 * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
124 */
125 u_int lccr0;
126 /* The following should be defined in LCCR3
127 * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
128 * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
129 * LCCR3_Acb(X) AB Bias pin frequency
130 * LCCR3_DPC (optional) Double Pixel Clock mode (untested)
131 *
132 * The following should not be defined in LCCR3
133 * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
134 */
135 u_int lccr3;
136 /* The following should be defined in LCCR4
137 * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
138 *
139 * All other bits in LCCR4 should be left alone.
140 */
141 u_int lccr4;
142 void (*pxafb_backlight_power)(int);
143 void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
144 void (*smart_update)(struct fb_info *);
145};
146void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
147void set_pxa_fb_parent(struct device *parent_dev);
148unsigned long pxafb_get_hsync_time(struct device *dev);
149
150extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
151extern int pxafb_smart_flush(struct fb_info *info);
diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h
deleted file mode 100644
index 820a189684a9..000000000000
--- a/include/asm-arm/arch-pxa/regs-lcd.h
+++ /dev/null
@@ -1,180 +0,0 @@
1#ifndef __ASM_ARCH_REGS_LCD_H
2#define __ASM_ARCH_REGS_LCD_H
3
4#include <asm/arch/bitfield.h>
5
6/*
7 * LCD Controller Registers and Bits Definitions
8 */
9#define LCCR0 (0x000) /* LCD Controller Control Register 0 */
10#define LCCR1 (0x004) /* LCD Controller Control Register 1 */
11#define LCCR2 (0x008) /* LCD Controller Control Register 2 */
12#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
13#define LCCR4 (0x010) /* LCD Controller Control Register 4 */
14#define LCCR5 (0x014) /* LCD Controller Control Register 5 */
15#define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
16#define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
17#define LCSR (0x038) /* LCD Controller Status Register */
18#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */
19#define TMEDRGBR (0x040) /* TMED RGB Seed Register */
20#define TMEDCR (0x044) /* TMED Control Register */
21
22#define CMDCR (0x100) /* Command Control Register */
23#define PRSR (0x104) /* Panel Read Status Register */
24
25#define LCCR3_1BPP (0 << 24)
26#define LCCR3_2BPP (1 << 24)
27#define LCCR3_4BPP (2 << 24)
28#define LCCR3_8BPP (3 << 24)
29#define LCCR3_16BPP (4 << 24)
30#define LCCR3_18BPP (5 << 24)
31#define LCCR3_18BPP_P (6 << 24)
32#define LCCR3_19BPP (7 << 24)
33#define LCCR3_19BPP_P (1 << 29)
34#define LCCR3_24BPP ((1 << 29) | (1 << 24))
35#define LCCR3_25BPP ((1 << 29) | (2 << 24))
36
37#define LCCR3_PDFOR_0 (0 << 30)
38#define LCCR3_PDFOR_1 (1 << 30)
39#define LCCR3_PDFOR_2 (2 << 30)
40#define LCCR3_PDFOR_3 (3 << 30)
41
42#define LCCR4_PAL_FOR_0 (0 << 15)
43#define LCCR4_PAL_FOR_1 (1 << 15)
44#define LCCR4_PAL_FOR_2 (2 << 15)
45#define LCCR4_PAL_FOR_MASK (3 << 15)
46
47#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
48#define FSADR0 (0x204) /* DMA Channel 0 Frame Source Address Register */
49#define FIDR0 (0x208) /* DMA Channel 0 Frame ID Register */
50#define LDCMD0 (0x20C) /* DMA Channel 0 Command Register */
51#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
52#define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */
53#define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */
54#define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */
55#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
56#define FSADR6 (0x264) /* DMA Channel 6 Frame Source Address Register */
57#define FIDR6 (0x268) /* DMA Channel 6 Frame ID Register */
58
59#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
60#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
61#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
62#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
63#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */
64#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
65#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
66
67#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
68#define LCCR0_SFM (1 << 4) /* Start of frame mask */
69#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
70#define LCCR0_EFM (1 << 6) /* End of Frame mask */
71#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
72#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
73#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
74#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */
75#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
76#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
77#define LCCR0_DIS (1 << 10) /* LCD Disable */
78#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
79#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
80#define LCCR0_PDD_S 12
81#define LCCR0_BM (1 << 20) /* Branch mask */
82#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
83#define LCCR0_LCDT (1 << 22) /* LCD panel type */
84#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
85#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
86#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
87#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
88
89#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
90#define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
91
92#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
93#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
94
95#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
96#define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
97
98#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
99#define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
100
101#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
102#define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP))
103
104#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */
105#define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
106
107#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
108#define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW))
109
110#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
111#define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW))
112
113#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
114#define LCCR3_API_S 16
115#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
116#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
117#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
118#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
119#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
120
121#define LCCR3_OEP (1 << 23) /* Output Enable Polarity */
122#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
123#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
124
125#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
126#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
127#define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD)))
128
129#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
130#define LCCR3_Bpp(Bpp) (((Bpp) << FShft (LCCR3_BPP)))
131
132#define LCCR3_ACB Fld (8, 8) /* AC Bias */
133#define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB)))
134
135#define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */
136#define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */
137
138#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */
139#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */
140
141#define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */
142#define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */
143#define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */
144#define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */
145
146#define LCSR_LDD (1 << 0) /* LCD Disable Done */
147#define LCSR_SOF (1 << 1) /* Start of frame */
148#define LCSR_BER (1 << 2) /* Bus error */
149#define LCSR_ABC (1 << 3) /* AC Bias count */
150#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
151#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
152#define LCSR_OU (1 << 6) /* output FIFO underrun */
153#define LCSR_QD (1 << 7) /* quick disable */
154#define LCSR_EOF (1 << 8) /* end of frame */
155#define LCSR_BS (1 << 9) /* branch status */
156#define LCSR_SINT (1 << 10) /* subsequent interrupt */
157#define LCSR_RD_ST (1 << 11) /* read status */
158#define LCSR_CMD_INT (1 << 12) /* command interrupt */
159
160#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
161
162/* smartpanel related */
163#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */
164#define PRSR_A0 (1 << 8) /* Read Data Source */
165#define PRSR_ST_OK (1 << 9) /* Status OK */
166#define PRSR_CON_NT (1 << 10) /* Continue to Next Command */
167
168#define SMART_CMD_A0 (0x1 << 8)
169#define SMART_CMD_READ_STATUS_REG (0x0 << 9)
170#define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0)
171#define SMART_CMD_WRITE_COMMAND (0x1 << 9)
172#define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0)
173#define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0)
174#define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9)
175#define SMART_CMD_NOOP (0x4 << 9)
176#define SMART_CMD_INTERRUPT (0x5 << 9)
177
178#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
179#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff))
180#endif /* __ASM_ARCH_REGS_LCD_H */
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
deleted file mode 100644
index 3c04cde2cf1f..000000000000
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ /dev/null
@@ -1,127 +0,0 @@
1#ifndef __ASM_ARCH_REGS_SSP_H
2#define __ASM_ARCH_REGS_SSP_H
3
4/*
5 * SSP Serial Port Registers
6 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
8 */
9
10#define SSCR0 (0x00) /* SSP Control Register 0 */
11#define SSCR1 (0x04) /* SSP Control Register 1 */
12#define SSSR (0x08) /* SSP Status Register */
13#define SSITR (0x0C) /* SSP Interrupt Test Register */
14#define SSDR (0x10) /* SSP Data Write/Data Read Register */
15
16#define SSTO (0x28) /* SSP Time Out Register */
17#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
18#define SSTSA (0x30) /* SSP Tx Timeslot Active */
19#define SSRSA (0x34) /* SSP Rx Timeslot Active */
20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22
23#if defined(CONFIG_PXA3xx)
24#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
25#endif
26
27/* Common PXA2xx bits first */
28#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
29#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
30#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
31#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
32#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
33#define SSCR0_National (0x2 << 4) /* National Microwire */
34#define SSCR0_ECS (1 << 6) /* External clock select */
35#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
36
37#if defined(CONFIG_PXA25x)
38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
40
41#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
42#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
43#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
44#define SSCR0_EDSS (1 << 20) /* Extended data size select */
45#define SSCR0_NCS (1 << 21) /* Network clock select */
46#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
47#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
48#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
49#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
50#define SSCR0_ADC (1 << 30) /* Audio clock select */
51#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
52#endif
53
54#if defined(CONFIG_PXA3xx)
55#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
56#endif
57
58#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
59#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
60#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
61#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
62#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
63#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
64#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
65#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
66#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
67#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
68
69#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
70#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
71#define SSSR_BSY (1 << 4) /* SSP Busy */
72#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
73#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
74#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
75
76#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
77#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
78#define SSCR0_NCS (1 << 21) /* Network Clock Select */
79#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
80
81/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
82#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
83#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
84#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
85#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
86#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
87#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
88#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
89#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
90#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
91#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
92#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
93#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
94#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
95#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
96#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
97#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
98#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
99#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
100#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
101
102#define SSSR_BCE (1 << 23) /* Bit Count Error */
103#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
104#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
105#define SSSR_EOC (1 << 20) /* End Of Chain */
106#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
107#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
108
109#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
110#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
111#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
112#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
113#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
114#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
115#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
116#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
117#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
118
119#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
120#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
121#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
122#if defined(CONFIG_PXA3xx)
123#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
124#endif
125
126
127#endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h
deleted file mode 100644
index 3b1d4a72d4d1..000000000000
--- a/include/asm-arm/arch-pxa/sharpsl.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * SharpSL SSP Driver
3 */
4
5unsigned long corgi_ssp_ads7846_putget(unsigned long);
6unsigned long corgi_ssp_ads7846_get(void);
7void corgi_ssp_ads7846_put(unsigned long data);
8void corgi_ssp_ads7846_lock(void);
9void corgi_ssp_ads7846_unlock(void);
10void corgi_ssp_lcdtg_send (unsigned char adrs, unsigned char data);
11void corgi_ssp_blduty_set(int duty);
12int corgi_ssp_max1111_get(unsigned long data);
13
14/*
15 * SharpSL Touchscreen Driver
16 */
17
18struct corgits_machinfo {
19 unsigned long (*get_hsync_invperiod)(void);
20 void (*put_hsync)(void);
21 void (*wait_hsync)(void);
22};
23
24
25/*
26 * SharpSL Backlight
27 */
28extern void corgibl_limit_intensity(int limit);
29
30
31/*
32 * SharpSL Battery/PM Driver
33 */
34extern void sharpsl_battery_kick(void);
diff --git a/include/asm-arm/arch-pxa/spitz.h b/include/asm-arm/arch-pxa/spitz.h
deleted file mode 100644
index bd14365f7ed5..000000000000
--- a/include/asm-arm/arch-pxa/spitz.h
+++ /dev/null
@@ -1,158 +0,0 @@
1/*
2 * Hardware specific definitions for SL-Cx000 series of PDAs
3 *
4 * Copyright (c) 2005 Alexander Wykes
5 * Copyright (c) 2005 Richard Purdie
6 *
7 * Based on Sharp's 2.4 kernel patches
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14#ifndef __ASM_ARCH_SPITZ_H
15#define __ASM_ARCH_SPITZ_H 1
16#endif
17
18#include <linux/fb.h>
19
20/* Spitz/Akita GPIOs */
21
22#define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */
23#define SPITZ_GPIO_RESET (1)
24#define SPITZ_GPIO_nSD_DETECT (9)
25#define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */
26#define SPITZ_GPIO_AK_INT (13) /* Remote Control */
27#define SPITZ_GPIO_ADS7846_CS (14)
28#define SPITZ_GPIO_SYNC (16)
29#define SPITZ_GPIO_MAX1111_CS (20)
30#define SPITZ_GPIO_FATAL_BAT (21)
31#define SPITZ_GPIO_HSYNC (22)
32#define SPITZ_GPIO_nSD_CLK (32)
33#define SPITZ_GPIO_USB_DEVICE (35)
34#define SPITZ_GPIO_USB_HOST (37)
35#define SPITZ_GPIO_USB_CONNECT (41)
36#define SPITZ_GPIO_LCDCON_CS (53)
37#define SPITZ_GPIO_nPCE (54)
38#define SPITZ_GPIO_nSD_WP (81)
39#define SPITZ_GPIO_ON_RESET (89)
40#define SPITZ_GPIO_BAT_COVER (90)
41#define SPITZ_GPIO_CF_CD (94)
42#define SPITZ_GPIO_ON_KEY (95)
43#define SPITZ_GPIO_SWA (97)
44#define SPITZ_GPIO_SWB (96)
45#define SPITZ_GPIO_CHRG_FULL (101)
46#define SPITZ_GPIO_CO (101)
47#define SPITZ_GPIO_CF_IRQ (105)
48#define SPITZ_GPIO_AC_IN (115)
49#define SPITZ_GPIO_HP_IN (116)
50
51/* Spitz Only GPIOs */
52
53#define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */
54#define SPITZ_GPIO_CF2_CD (93)
55
56
57/* Spitz/Akita Keyboard Definitions */
58
59#define SPITZ_KEY_STROBE_NUM (11)
60#define SPITZ_KEY_SENSE_NUM (7)
61#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000
62#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000
63#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000
64#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880
65#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000
66#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4
67#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000
68#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000
69
70#define SPITZ_GPIO_KEY_STROBE0 88
71#define SPITZ_GPIO_KEY_STROBE1 23
72#define SPITZ_GPIO_KEY_STROBE2 24
73#define SPITZ_GPIO_KEY_STROBE3 25
74#define SPITZ_GPIO_KEY_STROBE4 26
75#define SPITZ_GPIO_KEY_STROBE5 27
76#define SPITZ_GPIO_KEY_STROBE6 52
77#define SPITZ_GPIO_KEY_STROBE7 103
78#define SPITZ_GPIO_KEY_STROBE8 107
79#define SPITZ_GPIO_KEY_STROBE9 108
80#define SPITZ_GPIO_KEY_STROBE10 114
81
82#define SPITZ_GPIO_KEY_SENSE0 12
83#define SPITZ_GPIO_KEY_SENSE1 17
84#define SPITZ_GPIO_KEY_SENSE2 91
85#define SPITZ_GPIO_KEY_SENSE3 34
86#define SPITZ_GPIO_KEY_SENSE4 36
87#define SPITZ_GPIO_KEY_SENSE5 38
88#define SPITZ_GPIO_KEY_SENSE6 39
89
90
91/* Spitz Scoop Device (No. 1) GPIOs */
92/* Suspend States in comments */
93#define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */
94#define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */
95#define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */
96#define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */
97#define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */
98#define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */
99#define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */
100#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */
101#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */
102
103#define SPITZ_SCP_IO_DIR (SPITZ_SCP_LED_GREEN | SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
104 SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_LED_ORANGE | \
105 SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
106#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
107#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
108#define SPITZ_SCP_SUS_SET 0
109
110/* Spitz Scoop Device (No. 2) GPIOs */
111/* Suspend States in comments */
112#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */
113#define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */
114#define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */
115#define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */
116#define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */
117#define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */
118#define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */
119#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */
120#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */
121
122#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
123 SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
124 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
125
126#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
127#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
128 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
129#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
130
131
132/* Spitz IRQ Definitions */
133
134#define SPITZ_IRQ_GPIO_KEY_INT IRQ_GPIO(SPITZ_GPIO_KEY_INT)
135#define SPITZ_IRQ_GPIO_AC_IN IRQ_GPIO(SPITZ_GPIO_AC_IN)
136#define SPITZ_IRQ_GPIO_AK_INT IRQ_GPIO(SPITZ_GPIO_AK_INT)
137#define SPITZ_IRQ_GPIO_HP_IN IRQ_GPIO(SPITZ_GPIO_HP_IN)
138#define SPITZ_IRQ_GPIO_TP_INT IRQ_GPIO(SPITZ_GPIO_TP_INT)
139#define SPITZ_IRQ_GPIO_SYNC IRQ_GPIO(SPITZ_GPIO_SYNC)
140#define SPITZ_IRQ_GPIO_ON_KEY IRQ_GPIO(SPITZ_GPIO_ON_KEY)
141#define SPITZ_IRQ_GPIO_SWA IRQ_GPIO(SPITZ_GPIO_SWA)
142#define SPITZ_IRQ_GPIO_SWB IRQ_GPIO(SPITZ_GPIO_SWB)
143#define SPITZ_IRQ_GPIO_BAT_COVER IRQ_GPIO(SPITZ_GPIO_BAT_COVER)
144#define SPITZ_IRQ_GPIO_FATAL_BAT IRQ_GPIO(SPITZ_GPIO_FATAL_BAT)
145#define SPITZ_IRQ_GPIO_CO IRQ_GPIO(SPITZ_GPIO_CO)
146#define SPITZ_IRQ_GPIO_CF_IRQ IRQ_GPIO(SPITZ_GPIO_CF_IRQ)
147#define SPITZ_IRQ_GPIO_CF_CD IRQ_GPIO(SPITZ_GPIO_CF_CD)
148#define SPITZ_IRQ_GPIO_CF2_IRQ IRQ_GPIO(SPITZ_GPIO_CF2_IRQ)
149#define SPITZ_IRQ_GPIO_nSD_INT IRQ_GPIO(SPITZ_GPIO_nSD_INT)
150#define SPITZ_IRQ_GPIO_nSD_DETECT IRQ_GPIO(SPITZ_GPIO_nSD_DETECT)
151
152/*
153 * Shared data structures
154 */
155extern struct platform_device spitzscoop_device;
156extern struct platform_device spitzscoop2_device;
157extern struct platform_device spitzssp_device;
158extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h
deleted file mode 100644
index a012882c9ee6..000000000000
--- a/include/asm-arm/arch-pxa/ssp.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * ssp.h
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This driver supports the following PXA CPU/SSP ports:-
11 *
12 * PXA250 SSP
13 * PXA255 SSP, NSSP
14 * PXA26x SSP, NSSP, ASSP
15 * PXA27x SSP1, SSP2, SSP3
16 * PXA3xx SSP1, SSP2, SSP3, SSP4
17 */
18
19#ifndef __ASM_ARCH_SSP_H
20#define __ASM_ARCH_SSP_H
21
22#include <linux/list.h>
23
24enum pxa_ssp_type {
25 SSP_UNDEFINED = 0,
26 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
27 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
28 PXA27x_SSP,
29};
30
31struct ssp_device {
32 struct platform_device *pdev;
33 struct list_head node;
34
35 struct clk *clk;
36 void __iomem *mmio_base;
37 unsigned long phys_base;
38
39 const char *label;
40 int port_id;
41 int type;
42 int use_count;
43 int irq;
44 int drcmr_rx;
45 int drcmr_tx;
46};
47
48/*
49 * SSP initialisation flags
50 */
51#define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */
52
53struct ssp_state {
54 u32 cr0;
55 u32 cr1;
56 u32 to;
57 u32 psp;
58};
59
60struct ssp_dev {
61 struct ssp_device *ssp;
62 u32 port;
63 u32 mode;
64 u32 flags;
65 u32 psp_flags;
66 u32 speed;
67 int irq;
68};
69
70int ssp_write_word(struct ssp_dev *dev, u32 data);
71int ssp_read_word(struct ssp_dev *dev, u32 *data);
72int ssp_flush(struct ssp_dev *dev);
73void ssp_enable(struct ssp_dev *dev);
74void ssp_disable(struct ssp_dev *dev);
75void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
76void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
77int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
78int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
79void ssp_exit(struct ssp_dev *dev);
80
81struct ssp_device *ssp_request(int port, const char *label);
82void ssp_free(struct ssp_device *);
83#endif /* __ASM_ARCH_SSP_H */
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
deleted file mode 100644
index 6956fc5235f8..000000000000
--- a/include/asm-arm/arch-pxa/system.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/system.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <asm/proc-fns.h>
14#include "hardware.h"
15#include "pxa2xx-regs.h"
16#include "pxa-regs.h"
17
18static inline void arch_idle(void)
19{
20 cpu_do_idle();
21}
22
23
24void arch_reset(char mode);
diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h
deleted file mode 100644
index 8d882f0b6a16..000000000000
--- a/include/asm-arm/arch-pxa/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/timex.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13
14#if defined(CONFIG_PXA25x)
15/* PXA250/210 timer base */
16#define CLOCK_TICK_RATE 3686400
17#elif defined(CONFIG_PXA27x)
18/* PXA27x timer base */
19#ifdef CONFIG_MACH_MAINSTONE
20#define CLOCK_TICK_RATE 3249600
21#else
22#define CLOCK_TICK_RATE 3250000
23#endif
24#else
25#define CLOCK_TICK_RATE 3250000
26#endif
diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h
deleted file mode 100644
index a72803f0461b..000000000000
--- a/include/asm-arm/arch-pxa/tosa.h
+++ /dev/null
@@ -1,198 +0,0 @@
1/*
2 * Hardware specific definitions for Sharp SL-C6000x series of PDAs
3 *
4 * Copyright (c) 2005 Dirk Opfer
5 *
6 * Based on Sharp's 2.4 kernel patches
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#ifndef _ASM_ARCH_TOSA_H_
14#define _ASM_ARCH_TOSA_H_ 1
15
16/* TOSA Chip selects */
17#define TOSA_LCDC_PHYS PXA_CS4_PHYS
18/* Internel Scoop */
19#define TOSA_CF_PHYS (PXA_CS2_PHYS + 0x00800000)
20/* Jacket Scoop */
21#define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000)
22
23/*
24 * SCOOP2 internal GPIOs
25 */
26#define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO
27#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11
28#define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1)
29#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2)
30#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3)
31#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4)
32#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16
33#define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6)
34#define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7)
35#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19
36
37/* GPIO Direction 1 : output mode / 0:input mode */
38#define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \
39 TOSA_SCOOP_AUD_PWR_ON)
40
41/*
42 * SCOOP2 jacket GPIOs
43 */
44#define TOSA_SCOOP_JC_GPIO_BASE (NR_BUILTIN_GPIO + 12)
45#define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0)
46#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1)
47#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2)
48#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3)
49#define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4)
50#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5)
51#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17
52#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7)
53#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19
54
55/* GPIO Direction 1 : output mode / 0:input mode */
56#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL)
57
58/*
59 * TC6393XB GPIOs
60 */
61#define TOSA_TC6393XB_GPIO_BASE (NR_BUILTIN_GPIO + 2 * 12)
62#define TOSA_TC6393XB_GPIO(i) (TOSA_TC6393XB_GPIO_BASE + (i))
63#define TOSA_TC6393XB_GPIO_BIT(gpio) (1 << (gpio - TOSA_TC6393XB_GPIO_BASE))
64
65#define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0)
66#define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1)
67#define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3)
68#define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4)
69#define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6)
70#define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7)
71#define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9)
72#define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10)
73#define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11)
74#define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12)
75#define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14)
76#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15)
77
78/*
79 * Timing Generator
80 */
81#define TG_PNLCTL 0x00
82#define TG_TPOSCTL 0x01
83#define TG_DUTYCTL 0x02
84#define TG_GPOSR 0x03
85#define TG_GPODR1 0x04
86#define TG_GPODR2 0x05
87#define TG_PINICTL 0x06
88#define TG_HPOSCTL 0x07
89
90/*
91 * PXA GPIOs
92 */
93#define TOSA_GPIO_POWERON (0)
94#define TOSA_GPIO_RESET (1)
95#define TOSA_GPIO_AC_IN (2)
96#define TOSA_GPIO_RECORD_BTN (3)
97#define TOSA_GPIO_SYNC (4) /* Cradle SYNC Button */
98#define TOSA_GPIO_USB_IN (5)
99#define TOSA_GPIO_JACKET_DETECT (7)
100#define TOSA_GPIO_nSD_DETECT (9)
101#define TOSA_GPIO_nSD_INT (10)
102#define TOSA_GPIO_TC6393XB_CLK (11)
103#define TOSA_GPIO_BAT1_CRG (12)
104#define TOSA_GPIO_CF_CD (13)
105#define TOSA_GPIO_BAT0_CRG (14)
106#define TOSA_GPIO_TC6393XB_INT (15)
107#define TOSA_GPIO_BAT0_LOW (17)
108#define TOSA_GPIO_TC6393XB_RDY (18)
109#define TOSA_GPIO_ON_RESET (19)
110#define TOSA_GPIO_EAR_IN (20)
111#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */
112#define TOSA_GPIO_ON_KEY (22)
113#define TOSA_GPIO_VGA_LINE (27)
114#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */
115#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */
116#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */
117#define TOSA_GPIO_IRDA_TX (47)
118#define TOSA_GPIO_TG_SPI_SCLK (81)
119#define TOSA_GPIO_TG_SPI_CS (82)
120#define TOSA_GPIO_TG_SPI_MOSI (83)
121#define TOSA_GPIO_BAT1_LOW (84)
122
123#define TOSA_GPIO_HP_IN GPIO_EAR_IN
124
125#define TOSA_GPIO_MAIN_BAT_LOW GPIO_BAT0_LOW
126
127#define TOSA_KEY_STROBE_NUM (11)
128#define TOSA_KEY_SENSE_NUM (7)
129
130#define TOSA_GPIO_HIGH_STROBE_BIT (0xfc000000)
131#define TOSA_GPIO_LOW_STROBE_BIT (0x0000001f)
132#define TOSA_GPIO_ALL_SENSE_BIT (0x00000fe0)
133#define TOSA_GPIO_ALL_SENSE_RSHIFT (5)
134#define TOSA_GPIO_STROBE_BIT(a) GPIO_bit(58+(a))
135#define TOSA_GPIO_SENSE_BIT(a) GPIO_bit(69+(a))
136#define TOSA_GAFR_HIGH_STROBE_BIT (0xfff00000)
137#define TOSA_GAFR_LOW_STROBE_BIT (0x000003ff)
138#define TOSA_GAFR_ALL_SENSE_BIT (0x00fffc00)
139#define TOSA_GPIO_KEY_SENSE(a) (69+(a))
140#define TOSA_GPIO_KEY_STROBE(a) (58+(a))
141
142/*
143 * Interrupts
144 */
145#define TOSA_IRQ_GPIO_WAKEUP IRQ_GPIO(TOSA_GPIO_WAKEUP)
146#define TOSA_IRQ_GPIO_AC_IN IRQ_GPIO(TOSA_GPIO_AC_IN)
147#define TOSA_IRQ_GPIO_RECORD_BTN IRQ_GPIO(TOSA_GPIO_RECORD_BTN)
148#define TOSA_IRQ_GPIO_SYNC IRQ_GPIO(TOSA_GPIO_SYNC)
149#define TOSA_IRQ_GPIO_USB_IN IRQ_GPIO(TOSA_GPIO_USB_IN)
150#define TOSA_IRQ_GPIO_JACKET_DETECT IRQ_GPIO(TOSA_GPIO_JACKET_DETECT)
151#define TOSA_IRQ_GPIO_nSD_INT IRQ_GPIO(TOSA_GPIO_nSD_INT)
152#define TOSA_IRQ_GPIO_nSD_DETECT IRQ_GPIO(TOSA_GPIO_nSD_DETECT)
153#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
154#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD)
155#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
156#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT)
157#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
158#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN)
159#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ)
160#define TOSA_IRQ_GPIO_ON_KEY IRQ_GPIO(TOSA_GPIO_ON_KEY)
161#define TOSA_IRQ_GPIO_VGA_LINE IRQ_GPIO(TOSA_GPIO_VGA_LINE)
162#define TOSA_IRQ_GPIO_TP_INT IRQ_GPIO(TOSA_GPIO_TP_INT)
163#define TOSA_IRQ_GPIO_JC_CF_IRQ IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ)
164#define TOSA_IRQ_GPIO_BAT_LOCKED IRQ_GPIO(TOSA_GPIO_BAT_LOCKED)
165#define TOSA_IRQ_GPIO_BAT1_LOW IRQ_GPIO(TOSA_GPIO_BAT1_LOW)
166#define TOSA_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(69+(a))
167
168#define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW)
169
170#define TOSA_KEY_SYNC KEY_102ND /* ??? */
171
172#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES
173#define TOSA_KEY_RECORD KEY_YEN
174#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA
175#define TOSA_KEY_CANCEL KEY_ESC
176#define TOSA_KEY_CENTER KEY_HIRAGANA
177#define TOSA_KEY_OK KEY_HENKAN
178#define TOSA_KEY_CALENDAR KEY_KATAKANAHIRAGANA
179#define TOSA_KEY_HOMEPAGE KEY_HANGEUL
180#define TOSA_KEY_LIGHT KEY_MUHENKAN
181#define TOSA_KEY_MENU KEY_HANJA
182#define TOSA_KEY_FN KEY_RIGHTALT
183#define TOSA_KEY_MAIL KEY_ZENKAKUHANKAKU
184#else
185#define TOSA_KEY_RECORD KEY_RECORD
186#define TOSA_KEY_ADDRESSBOOK KEY_ADDRESSBOOK
187#define TOSA_KEY_CANCEL KEY_CANCEL
188#define TOSA_KEY_CENTER KEY_SELECT /* ??? */
189#define TOSA_KEY_OK KEY_OK
190#define TOSA_KEY_CALENDAR KEY_CALENDAR
191#define TOSA_KEY_HOMEPAGE KEY_HOMEPAGE
192#define TOSA_KEY_LIGHT KEY_KBDILLUMTOGGLE
193#define TOSA_KEY_MENU KEY_MENU
194#define TOSA_KEY_FN KEY_FN
195#define TOSA_KEY_MAIL KEY_MAIL
196#endif
197
198#endif /* _ASM_ARCH_TOSA_H_ */
diff --git a/include/asm-arm/arch-pxa/tosa_bt.h b/include/asm-arm/arch-pxa/tosa_bt.h
deleted file mode 100644
index efc3c3d3b75d..000000000000
--- a/include/asm-arm/arch-pxa/tosa_bt.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Tosa bluetooth built-in chip control.
3 *
4 * Later it may be shared with some other platforms.
5 *
6 * Copyright (c) 2008 Dmitry Baryshkov
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#ifndef TOSA_BT_H
14#define TOSA_BT_H
15
16struct tosa_bt_data {
17 int gpio_pwr;
18 int gpio_reset;
19};
20
21#endif
22
diff --git a/include/asm-arm/arch-pxa/trizeps4.h b/include/asm-arm/arch-pxa/trizeps4.h
deleted file mode 100644
index 641d0ec110bb..000000000000
--- a/include/asm-arm/arch-pxa/trizeps4.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/************************************************************************
2 * Include file for TRIZEPS4 SoM and ConXS eval-board
3 * Copyright (c) Jürgen Schindele
4 * 2006
5 ************************************************************************/
6
7/*
8 * Includes/Defines
9 */
10#ifndef _TRIPEPS4_H_
11#define _TRIPEPS4_H_
12
13/* physical memory regions */
14#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
15#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */
16#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
17#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
18#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
19
20#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */
21#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */
22#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/
23#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/
24#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/
25
26/* virtual memory regions */
27#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
28
29#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */
30#define TRIZEPS4_CFSR_VIRT 0xF0100000
31#define TRIZEPS4_BOCR_VIRT 0xF0200000
32#define TRIZEPS4_DICR_VIRT 0xF0300000
33#define TRIZEPS4_IRCR_VIRT 0xF0400000
34#define TRIZEPS4_UPSR_VIRT 0xF0500000
35
36/* size of flash */
37#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
38
39/* Ethernet Controller Davicom DM9000 */
40#define GPIO_DM9000 101
41#define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
42
43/* UCB1400 audio / TS-controller */
44#define GPIO_UCB1400 1
45#define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400)
46
47/* PCMCIA socket Compact Flash */
48#define GPIO_PCD 11 /* PCMCIA Card Detect */
49#define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD)
50#define GPIO_PRDY 13 /* READY / nINT */
51#define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY)
52
53/* MMC socket */
54#define GPIO_MMC_DET 12
55#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET)
56
57/* LEDS using tx2 / rx2 */
58#define GPIO_SYS_BUSY_LED 46
59#define GPIO_HEARTBEAT_LED 47
60
61/* Off-module PIC on ConXS board */
62#define GPIO_PIC 0
63#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC)
64
65#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
66#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
67
68#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
69#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
70
71#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
72#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
73
74#ifndef __ASSEMBLY__
75#define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000)))
76#define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000)))
77#define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000)))
78#else
79#define ConXS_CFSR CFSR_P2V(0x0C000000)
80#define ConXS_BCR BCR_P2V(0x0E000000)
81#define ConXS_DCR DCR_P2V(0x0F800000)
82#endif
83
84#define ConXS_CFSR_BVD_MASK 0x0003
85#define ConXS_CFSR_BVD1 (1 << 0)
86#define ConXS_CFSR_BVD2 (1 << 1)
87#define ConXS_CFSR_VS_MASK 0x000C
88#define ConXS_CFSR_VS1 (1 << 2)
89#define ConXS_CFSR_VS2 (1 << 3)
90#define ConXS_CFSR_VS_5V (0x3 << 2)
91#define ConXS_CFSR_VS_3V3 0x0
92
93#define ConXS_BCR_S0_POW_EN0 (1 << 0)
94#define ConXS_BCR_S0_POW_EN1 (1 << 1)
95#define ConXS_BCR_L_DISP (1 << 4)
96#define ConXS_BCR_CF_BUF_EN (1 << 5)
97#define ConXS_BCR_CF_RESET (1 << 7)
98#define ConXS_BCR_S0_VCC_3V3 0x1
99#define ConXS_BCR_S0_VCC_5V0 0x2
100#define ConXS_BCR_S0_VPP_12V 0x4
101#define ConXS_BCR_S0_VPP_3V3 0x8
102
103#define ConXS_IRCR_MODE (1 << 0)
104#define ConXS_IRCR_SD (1 << 1)
105
106#endif /* _TRIPEPS4_H_ */
diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h
deleted file mode 100644
index 27aa3a91012f..000000000000
--- a/include/asm-arm/arch-pxa/udc.h
+++ /dev/null
@@ -1,8 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/udc.h
3 *
4 */
5#include <asm/mach/udc_pxa2xx.h>
6
7extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);
8
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
deleted file mode 100644
index f4551269aaf2..000000000000
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/uncompress.h
3 *
4 * Author: Nicolas Pitre
5 * Copyright: (C) 2001 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/serial_reg.h>
13#include <asm/arch/pxa-regs.h>
14#include <asm/mach-types.h>
15
16#define __REG(x) ((volatile unsigned long *)x)
17
18static volatile unsigned long *UART = FFUART;
19
20static inline void putc(char c)
21{
22 if (!(UART[UART_IER] & IER_UUE))
23 return;
24 while (!(UART[UART_LSR] & LSR_TDRQ))
25 barrier();
26 UART[UART_TX] = c;
27}
28
29/*
30 * This does not append a newline
31 */
32static inline void flush(void)
33{
34}
35
36static inline void arch_decomp_setup(void)
37{
38 if (machine_is_littleton())
39 UART = STUART;
40}
41
42/*
43 * nothing to do
44 */
45#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pxa/vmalloc.h b/include/asm-arm/arch-pxa/vmalloc.h
deleted file mode 100644
index 5bb450c7aa2c..000000000000
--- a/include/asm-arm/arch-pxa/vmalloc.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/vmalloc.h
3 *
4 * Author: Nicolas Pitre
5 * Copyright: (C) 2001 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#define VMALLOC_END (0xe8000000)
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
deleted file mode 100644
index 0d35ca04731e..000000000000
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ /dev/null
@@ -1,47 +0,0 @@
1#ifndef __ASM_ARCH_ZYLONITE_H
2#define __ASM_ARCH_ZYLONITE_H
3
4#define ZYLONITE_ETH_PHYS 0x14000000
5
6#define EXT_GPIO(x) (128 + (x))
7
8/* the following variables are processor specific and initialized
9 * by the corresponding zylonite_pxa3xx_init()
10 */
11struct platform_mmc_slot {
12 int gpio_cd;
13 int gpio_wp;
14};
15
16extern struct platform_mmc_slot zylonite_mmc_slot[];
17
18extern int gpio_eth_irq;
19extern int gpio_debug_led1;
20extern int gpio_debug_led2;
21
22extern int wm9713_irq;
23
24extern int lcd_id;
25extern int lcd_orientation;
26
27#ifdef CONFIG_CPU_PXA300
28extern void zylonite_pxa300_init(void);
29#else
30static inline void zylonite_pxa300_init(void)
31{
32 if (cpu_is_pxa300() || cpu_is_pxa310())
33 panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__);
34}
35#endif
36
37#ifdef CONFIG_CPU_PXA320
38extern void zylonite_pxa320_init(void);
39#else
40static inline void zylonite_pxa320_init(void)
41{
42 if (cpu_is_pxa320())
43 panic("%s: PXA320 not supported\n", __FUNCTION__);
44}
45#endif
46
47#endif /* __ASM_ARCH_ZYLONITE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 09:42:27 -0500