diff options
Diffstat (limited to 'include/asm-arm/arch-pxa')
-rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 24 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/udc.h | 30 |
2 files changed, 41 insertions, 13 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index e24f6b6c79ae..aec835b6f057 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
@@ -463,9 +463,6 @@ | |||
463 | * Serial Audio Controller | 463 | * Serial Audio Controller |
464 | */ | 464 | */ |
465 | 465 | ||
466 | /* FIXME: This clash with SA1111 defines */ | ||
467 | #ifndef _ASM_ARCH_SA1111 | ||
468 | |||
469 | #define SACR0 __REG(0x40400000) /* Global Control Register */ | 466 | #define SACR0 __REG(0x40400000) /* Global Control Register */ |
470 | #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ | 467 | #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ |
471 | #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ | 468 | #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ |
@@ -474,8 +471,8 @@ | |||
474 | #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ | 471 | #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ |
475 | #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ | 472 | #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ |
476 | 473 | ||
477 | #define SACR0_RFTH(x) (x << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ | 474 | #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ |
478 | #define SACR0_TFTH(x) (x << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ | 475 | #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ |
479 | #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ | 476 | #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ |
480 | #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ | 477 | #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ |
481 | #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ | 478 | #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ |
@@ -503,8 +500,6 @@ | |||
503 | #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ | 500 | #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ |
504 | #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ | 501 | #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ |
505 | 502 | ||
506 | #endif | ||
507 | |||
508 | /* | 503 | /* |
509 | * AC97 Controller registers | 504 | * AC97 Controller registers |
510 | */ | 505 | */ |
@@ -1682,15 +1677,18 @@ | |||
1682 | #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ | 1677 | #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ |
1683 | 1678 | ||
1684 | #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ | 1679 | #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ |
1685 | #define SSPSP_DMYSTOP(x) (x << 23) /* Dummy Stop */ | 1680 | #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ |
1686 | #define SSPSP_SFRMWDTH(x) (x << 16) /* Serial Frame Width */ | 1681 | #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ |
1687 | #define SSPSP_SFRMDLY(x) (x << 9) /* Serial Frame Delay */ | 1682 | #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ |
1688 | #define SSPSP_DMYSTRT(x) (x << 7) /* Dummy Start */ | 1683 | #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ |
1689 | #define SSPSP_STRTDLY(x) (x << 4) /* Start Delay */ | 1684 | #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ |
1690 | #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ | 1685 | #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ |
1691 | #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ | 1686 | #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ |
1692 | #define SSPSP_SCMODE(x) (x << 0) /* Serial Bit Rate Clock Mode */ | 1687 | #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ |
1693 | 1688 | ||
1689 | #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ | ||
1690 | #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ | ||
1691 | #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ | ||
1694 | 1692 | ||
1695 | #define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */ | 1693 | #define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */ |
1696 | #define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */ | 1694 | #define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */ |
diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h index 646480d37256..8bc6f9c3e3ea 100644 --- a/include/asm-arm/arch-pxa/udc.h +++ b/include/asm-arm/arch-pxa/udc.h | |||
@@ -9,3 +9,33 @@ | |||
9 | 9 | ||
10 | extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); | 10 | extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); |
11 | 11 | ||
12 | static inline int udc_gpio_to_irq(unsigned gpio) | ||
13 | { | ||
14 | return IRQ_GPIO(gpio & GPIO_MD_MASK_NR); | ||
15 | } | ||
16 | |||
17 | static inline void udc_gpio_init_vbus(unsigned gpio) | ||
18 | { | ||
19 | pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_IN); | ||
20 | } | ||
21 | |||
22 | static inline void udc_gpio_init_pullup(unsigned gpio) | ||
23 | { | ||
24 | pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_OUT | GPIO_DFLT_LOW); | ||
25 | } | ||
26 | |||
27 | static inline int udc_gpio_get(unsigned gpio) | ||
28 | { | ||
29 | return (GPLR(gpio) & GPIO_bit(gpio)) != 0; | ||
30 | } | ||
31 | |||
32 | static inline void udc_gpio_set(unsigned gpio, int is_on) | ||
33 | { | ||
34 | int mask = GPIO_bit(gpio); | ||
35 | |||
36 | if (is_on) | ||
37 | GPSR(gpio) = mask; | ||
38 | else | ||
39 | GPCR(gpio) = mask; | ||
40 | } | ||
41 | |||