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-rw-r--r--include/asm-arm/arch-pxa/dma.h22
-rw-r--r--include/asm-arm/arch-pxa/entry-macro.S30
-rw-r--r--include/asm-arm/arch-pxa/hardware.h36
-rw-r--r--include/asm-arm/arch-pxa/irqs.h26
-rw-r--r--include/asm-arm/arch-pxa/pm.h1
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h22
6 files changed, 73 insertions, 64 deletions
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
index bed042d71d68..3280ee2ddfa5 100644
--- a/include/asm-arm/arch-pxa/dma.h
+++ b/include/asm-arm/arch-pxa/dma.h
@@ -30,30 +30,12 @@ typedef enum {
30 DMA_PRIO_LOW = 2 30 DMA_PRIO_LOW = 2
31} pxa_dma_prio; 31} pxa_dma_prio;
32 32
33#if defined(CONFIG_PXA27x)
34
35#define PXA_DMA_CHANNELS 32
36
37#define pxa_for_each_dma_prio(ch, prio) \
38for ( \
39 ch = prio * 4; \
40 ch != (4 << prio) + 16; \
41 ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \
42)
43
44#elif defined(CONFIG_PXA25x)
45
46#define PXA_DMA_CHANNELS 16
47
48#define pxa_for_each_dma_prio(ch, prio) \
49 for (ch = prio * 4; ch != (4 << prio); ch++)
50
51#endif
52
53/* 33/*
54 * DMA registration 34 * DMA registration
55 */ 35 */
56 36
37int __init pxa_init_dma(int num_ch);
38
57int pxa_request_dma (char *name, 39int pxa_request_dma (char *name,
58 pxa_dma_prio prio, 40 pxa_dma_prio prio,
59 void (*irq_handler)(int, void *), 41 void (*irq_handler)(int, void *),
diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S
index 1d5fbb9b379a..b7e730851461 100644
--- a/include/asm-arm/arch-pxa/entry-macro.S
+++ b/include/asm-arm/arch-pxa/entry-macro.S
@@ -20,20 +20,38 @@
20 .endm 20 .endm
21 21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23#ifdef CONFIG_PXA27x 23 mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
24 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP 24 mov \tmp, \tmp, lsr #13
25 mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR 25 and \tmp, \tmp, #0x7 @ Core G
26#else 26 cmp \tmp, #1
27 bhi 1004f
28
27 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 29 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
28 add \base, \base, #0x00d00000 30 add \base, \base, #0x00d00000
29 ldr \irqstat, [\base, #0] @ ICIP 31 ldr \irqstat, [\base, #0] @ ICIP
30 ldr \irqnr, [\base, #4] @ ICMR 32 ldr \irqnr, [\base, #4] @ ICMR
31#endif 33 b 1002f
34
351004:
36 mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2
37 mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2
38 ands \irqstat, \irqstat, \irqnr
39 beq 1003f
40 rsb \irqstat, \irqnr, #0
41 and \irqstat, \irqstat, \irqnr
42 clz \irqnr, \irqstat
43 rsb \irqnr, \irqnr, #31
44 add \irqnr, \irqnr, #32
45 b 1001f
461003:
47 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
48 mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
491002:
32 ands \irqnr, \irqstat, \irqnr 50 ands \irqnr, \irqstat, \irqnr
33 beq 1001f 51 beq 1001f
34 rsb \irqstat, \irqnr, #0 52 rsb \irqstat, \irqnr, #0
35 and \irqstat, \irqstat, \irqnr 53 and \irqstat, \irqstat, \irqnr
36 clz \irqnr, \irqstat 54 clz \irqnr, \irqstat
37 rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP) 55 rsb \irqnr, \irqnr, #31
381001: 561001:
39 .endm 57 .endm
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index e2bdc2fbede1..386121746417 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -62,6 +62,42 @@
62 62
63#ifndef __ASSEMBLY__ 63#ifndef __ASSEMBLY__
64 64
65#define __cpu_is_pxa21x(id) \
66 ({ \
67 unsigned int _id = (id) >> 4 & 0xf3f; \
68 _id == 0x212; \
69 })
70
71#define __cpu_is_pxa25x(id) \
72 ({ \
73 unsigned int _id = (id) >> 4 & 0xfff; \
74 _id == 0x2d0 || _id == 0x290; \
75 })
76
77#define __cpu_is_pxa27x(id) \
78 ({ \
79 unsigned int _id = (id) >> 4 & 0xfff; \
80 _id == 0x411; \
81 })
82
83#define cpu_is_pxa21x() \
84 ({ \
85 unsigned int id = read_cpuid(CPUID_ID); \
86 __cpu_is_pxa21x(id); \
87 })
88
89#define cpu_is_pxa25x() \
90 ({ \
91 unsigned int id = read_cpuid(CPUID_ID); \
92 __cpu_is_pxa25x(id); \
93 })
94
95#define cpu_is_pxa27x() \
96 ({ \
97 unsigned int id = read_cpuid(CPUID_ID); \
98 __cpu_is_pxa27x(id); \
99 })
100
65/* 101/*
66 * Handy routine to set GPIO alternate functions 102 * Handy routine to set GPIO alternate functions
67 */ 103 */
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index 67ed43674c63..a07fe0f928cd 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -11,14 +11,9 @@
11 */ 11 */
12 12
13 13
14#ifdef CONFIG_PXA27x 14#define PXA_IRQ(x) (x)
15#define PXA_IRQ_SKIP 0
16#else
17#define PXA_IRQ_SKIP 7
18#endif
19
20#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP)
21 15
16#ifdef CONFIG_PXA27x
22#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ 17#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
23#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ 18#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
24#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ 19#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
@@ -26,6 +21,8 @@
26#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ 21#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
27#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ 22#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
28#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ 23#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
24#endif
25
29#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ 26#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
30#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ 27#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
31#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ 28#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
@@ -58,18 +55,15 @@
58#ifdef CONFIG_PXA27x 55#ifdef CONFIG_PXA27x
59#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ 56#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
60#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ 57#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
61
62#define PXA_INTERNAL_IRQS 34
63#else
64#define PXA_INTERNAL_IRQS 32
65#endif 58#endif
66 59
67#define GPIO_2_x_TO_IRQ(x) \ 60#define PXA_GPIO_IRQ_BASE (64)
68 PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS) 61#define PXA_GPIO_IRQ_NUM (128)
62
63#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
69#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) 64#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
70 65
71#define IRQ_TO_GPIO_2_x(i) \ 66#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
72 ((i) - IRQ_GPIO(2) + 2)
73#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) 67#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
74 68
75#if defined(CONFIG_PXA25x) 69#if defined(CONFIG_PXA25x)
@@ -84,7 +78,7 @@
84 * these. If you need more, increase IRQ_BOARD_END, but keep it 78 * these. If you need more, increase IRQ_BOARD_END, but keep it
85 * within sensible limits. 79 * within sensible limits.
86 */ 80 */
87#define IRQ_BOARD_START (IRQ_GPIO(PXA_LAST_GPIO) + 1) 81#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
88#define IRQ_BOARD_END (IRQ_BOARD_START + 16) 82#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
89 83
90#define IRQ_SA1111_START (IRQ_BOARD_END) 84#define IRQ_SA1111_START (IRQ_BOARD_END)
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h
index 7a8a1cdf430d..52243a62c4e7 100644
--- a/include/asm-arm/arch-pxa/pm.h
+++ b/include/asm-arm/arch-pxa/pm.h
@@ -9,4 +9,3 @@
9 9
10extern int pxa_pm_prepare(suspend_state_t state); 10extern int pxa_pm_prepare(suspend_state_t state);
11extern int pxa_pm_enter(suspend_state_t state); 11extern int pxa_pm_enter(suspend_state_t state);
12extern int pxa_pm_finish(suspend_state_t state);
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index dbcc9298b0c8..e68b593d69da 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1765,29 +1765,9 @@
1765#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL)) 1765#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
1766 1766
1767/* 1767/*
1768 * MultiMediaCard (MMC) controller 1768 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
1769 */ 1769 */
1770 1770
1771#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
1772#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
1773#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
1774#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
1775#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
1776#define MMC_RESTO __REG(0x41100014) /* Expected response time out */
1777#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
1778#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
1779#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
1780#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
1781#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
1782#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
1783#define MMC_CMD __REG(0x41100030) /* Index of current command */
1784#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
1785#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
1786#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
1787#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
1788#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
1789
1790
1791/* 1771/*
1792 * Core Clock 1772 * Core Clock
1793 */ 1773 */