diff options
Diffstat (limited to 'include/asm-arm/arch-pxa')
-rw-r--r-- | include/asm-arm/arch-pxa/cm-x270.h | 50 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/mfp-pxa27x.h | 1 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/palmtx.h | 106 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa27x-udc.h | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa2xx-gpio.h | 9 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxafb.h | 3 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/regs-lcd.h | 11 |
7 files changed, 129 insertions, 53 deletions
diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h deleted file mode 100644 index f8fac9e18009..000000000000 --- a/include/asm-arm/arch-pxa/cm-x270.h +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm/arch-pxa/cm-x270.h | ||
3 | * | ||
4 | * Copyright Compulab Ltd., 2003, 2007 | ||
5 | * Mike Rapoport <mike@compulab.co.il> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | |||
13 | /* CM-x270 device physical addresses */ | ||
14 | #define CMX270_CS1_PHYS (PXA_CS1_PHYS) | ||
15 | #define MARATHON_PHYS (PXA_CS2_PHYS) | ||
16 | #define CMX270_IDE104_PHYS (PXA_CS3_PHYS) | ||
17 | #define CMX270_IT8152_PHYS (PXA_CS4_PHYS) | ||
18 | |||
19 | /* Statically mapped regions */ | ||
20 | #define CMX270_VIRT_BASE (0xe8000000) | ||
21 | #define CMX270_IT8152_VIRT (CMX270_VIRT_BASE) | ||
22 | #define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M) | ||
23 | |||
24 | /* GPIO related definitions */ | ||
25 | #define GPIO_IT8152_IRQ (22) | ||
26 | |||
27 | #define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ) | ||
28 | #define PME_IRQ IRQ_GPIO(0) | ||
29 | #define CMX270_IDE_IRQ IRQ_GPIO(100) | ||
30 | #define CMX270_GPIRQ1 IRQ_GPIO(101) | ||
31 | #define CMX270_TOUCHIRQ IRQ_GPIO(96) | ||
32 | #define CMX270_ETHIRQ IRQ_GPIO(10) | ||
33 | #define CMX270_GFXIRQ IRQ_GPIO(95) | ||
34 | #define CMX270_NANDIRQ IRQ_GPIO(89) | ||
35 | #define CMX270_MMC_IRQ IRQ_GPIO(83) | ||
36 | |||
37 | /* PCMCIA related definitions */ | ||
38 | #define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x))) | ||
39 | #define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x))) | ||
40 | |||
41 | #define PCMCIA_S0_CD_VALID IRQ_GPIO(84) | ||
42 | #define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES | ||
43 | |||
44 | #define PCMCIA_S1_CD_VALID IRQ_GPIO(83) | ||
45 | #define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES | ||
46 | |||
47 | #define PCMCIA_S0_RDYINT IRQ_GPIO(82) | ||
48 | #define PCMCIA_S1_RDYINT IRQ_GPIO(81) | ||
49 | |||
50 | #define PCMCIA_RESET_GPIO 53 | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa27x.h b/include/asm-arm/arch-pxa/mfp-pxa27x.h index eb6eaa174f8d..bc73ab84167c 100644 --- a/include/asm-arm/arch-pxa/mfp-pxa27x.h +++ b/include/asm-arm/arch-pxa/mfp-pxa27x.h | |||
@@ -112,6 +112,7 @@ | |||
112 | #define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) | 112 | #define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) |
113 | #define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) | 113 | #define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) |
114 | #define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) | 114 | #define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) |
115 | #define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH) | ||
115 | 116 | ||
116 | /* I2C */ | 117 | /* I2C */ |
117 | #define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) | 118 | #define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) |
diff --git a/include/asm-arm/arch-pxa/palmtx.h b/include/asm-arm/arch-pxa/palmtx.h new file mode 100644 index 000000000000..1e8bccbda510 --- /dev/null +++ b/include/asm-arm/arch-pxa/palmtx.h | |||
@@ -0,0 +1,106 @@ | |||
1 | /* | ||
2 | * GPIOs and interrupts for Palm T|X Handheld Computer | ||
3 | * | ||
4 | * Based on palmld-gpio.h by Alex Osborne | ||
5 | * | ||
6 | * Authors: Marek Vasut <marek.vasut@gmail.com> | ||
7 | * Cristiano P. <cristianop@users.sourceforge.net> | ||
8 | * Jan Herman <2hp@seznam.cz> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #ifndef _INCLUDE_PALMTX_H_ | ||
17 | #define _INCLUDE_PALMTX_H_ | ||
18 | |||
19 | /** HERE ARE GPIOs **/ | ||
20 | |||
21 | /* GPIOs */ | ||
22 | #define GPIO_NR_PALMTX_GPIO_RESET 1 | ||
23 | |||
24 | #define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */ | ||
25 | #define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10 | ||
26 | #define GPIO_NR_PALMTX_EARPHONE_DETECT 107 | ||
27 | |||
28 | /* SD/MMC */ | ||
29 | #define GPIO_NR_PALMTX_SD_DETECT_N 14 | ||
30 | #define GPIO_NR_PALMTX_SD_POWER 114 /* probably */ | ||
31 | #define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */ | ||
32 | |||
33 | /* TOUCHSCREEN */ | ||
34 | #define GPIO_NR_PALMTX_WM9712_IRQ 27 | ||
35 | |||
36 | /* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ | ||
37 | #define GPIO_NR_PALMTX_IR_DISABLE 40 | ||
38 | |||
39 | /* USB */ | ||
40 | #define GPIO_NR_PALMTX_USB_DETECT_N 13 | ||
41 | #define GPIO_NR_PALMTX_USB_POWER 95 | ||
42 | #define GPIO_NR_PALMTX_USB_PULLUP 93 | ||
43 | |||
44 | /* LCD/BACKLIGHT */ | ||
45 | #define GPIO_NR_PALMTX_BL_POWER 84 | ||
46 | #define GPIO_NR_PALMTX_LCD_POWER 96 | ||
47 | |||
48 | /* LCD BORDER */ | ||
49 | #define GPIO_NR_PALMTX_BORDER_SWITCH 98 | ||
50 | #define GPIO_NR_PALMTX_BORDER_SELECT 22 | ||
51 | |||
52 | /* BLUETOOTH */ | ||
53 | #define GPIO_NR_PALMTX_BT_POWER 17 | ||
54 | #define GPIO_NR_PALMTX_BT_RESET 83 | ||
55 | |||
56 | /* PCMCIA (WiFi) */ | ||
57 | #define GPIO_NR_PALMTX_PCMCIA_POWER1 94 | ||
58 | #define GPIO_NR_PALMTX_PCMCIA_POWER2 108 | ||
59 | #define GPIO_NR_PALMTX_PCMCIA_RESET 79 | ||
60 | #define GPIO_NR_PALMTX_PCMCIA_READY 116 | ||
61 | |||
62 | /* NAND Flash ... this GPIO may be incorrect! */ | ||
63 | #define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79 | ||
64 | |||
65 | /* INTERRUPTS */ | ||
66 | #define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N) | ||
67 | #define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ) | ||
68 | #define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT) | ||
69 | #define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET) | ||
70 | |||
71 | /** HERE ARE INIT VALUES **/ | ||
72 | |||
73 | /* Various addresses */ | ||
74 | #define PALMTX_PCMCIA_PHYS 0x28000000 | ||
75 | #define PALMTX_PCMCIA_VIRT 0xf0000000 | ||
76 | #define PALMTX_PCMCIA_SIZE 0x100000 | ||
77 | |||
78 | #define PALMTX_PHYS_RAM_START 0xa0000000 | ||
79 | #define PALMTX_PHYS_IO_START 0x40000000 | ||
80 | |||
81 | #define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */ | ||
82 | #define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */ | ||
83 | |||
84 | /* TOUCHSCREEN */ | ||
85 | #define AC97_LINK_FRAME 21 | ||
86 | |||
87 | |||
88 | /* BATTERY */ | ||
89 | #define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ | ||
90 | #define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ | ||
91 | #define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */ | ||
92 | #define PALMTX_BAT_MIN_CURRENT 0 /* unknown */ | ||
93 | #define PALMTX_BAT_MAX_CHARGE 1 /* unknown */ | ||
94 | #define PALMTX_BAT_MIN_CHARGE 1 /* unknown */ | ||
95 | #define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */ | ||
96 | |||
97 | #define PALMTX_BAT_MEASURE_DELAY (HZ * 1) | ||
98 | |||
99 | /* BACKLIGHT */ | ||
100 | #define PALMTX_MAX_INTENSITY 0xFE | ||
101 | #define PALMTX_DEFAULT_INTENSITY 0x7E | ||
102 | #define PALMTX_LIMIT_MASK 0x7F | ||
103 | #define PALMTX_PRESCALER 0x3F | ||
104 | #define PALMTX_PERIOD_NS 3500 | ||
105 | |||
106 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h index bc1cf7d0773a..ab1443f8bd89 100644 --- a/include/asm-arm/arch-pxa/pxa27x-udc.h +++ b/include/asm-arm/arch-pxa/pxa27x-udc.h | |||
@@ -97,7 +97,7 @@ | |||
97 | #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ | 97 | #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ |
98 | #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ | 98 | #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ |
99 | #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ | 99 | #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ |
100 | #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ | 100 | #define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */ |
101 | 101 | ||
102 | #define UDCCSN(x) __REG2(0x40600100, (x) << 2) | 102 | #define UDCCSN(x) __REG2(0x40600100, (x) << 2) |
103 | #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ | 103 | #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ |
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h index a6e60f691617..6ef1dd09970b 100644 --- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h +++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h | |||
@@ -136,7 +136,11 @@ | |||
136 | #define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */ | 136 | #define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */ |
137 | #define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */ | 137 | #define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */ |
138 | #define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */ | 138 | #define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */ |
139 | #define GPIO96_FFRXD 96 /* FFUART recieve */ | ||
140 | #define GPIO98_FFRTS 98 /* FFUART request to send */ | ||
139 | #define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */ | 141 | #define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */ |
142 | #define GPIO99_FFTXD 99 /* FFUART transmit data */ | ||
143 | #define GPIO100_FFCTS 100 /* FFUART Clear to send */ | ||
140 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ | 144 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ |
141 | #define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */ | 145 | #define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */ |
142 | #define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */ | 146 | #define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */ |
@@ -318,6 +322,8 @@ | |||
318 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) | 322 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) |
319 | #define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) | 323 | #define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) |
320 | #define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) | 324 | #define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) |
325 | #define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN) | ||
326 | #define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT) | ||
321 | #define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN) | 327 | #define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN) |
322 | #define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN) | 328 | #define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN) |
323 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) | 329 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) |
@@ -326,8 +332,11 @@ | |||
326 | #define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN) | 332 | #define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN) |
327 | #define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) | 333 | #define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) |
328 | #define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) | 334 | #define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) |
335 | #define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN) | ||
329 | #define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) | 336 | #define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) |
330 | #define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN) | 337 | #define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN) |
338 | #define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT) | ||
339 | #define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT) | ||
331 | #define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) | 340 | #define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) |
332 | #define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) | 341 | #define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) |
333 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) | 342 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) |
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h index bbd22396841a..daf018d0c604 100644 --- a/include/asm-arm/arch-pxa/pxafb.h +++ b/include/asm-arm/arch-pxa/pxafb.h | |||
@@ -71,7 +71,8 @@ struct pxafb_mode_info { | |||
71 | 71 | ||
72 | u_char bpp; | 72 | u_char bpp; |
73 | u_int cmap_greyscale:1, | 73 | u_int cmap_greyscale:1, |
74 | unused:31; | 74 | depth:8, |
75 | unused:23; | ||
75 | 76 | ||
76 | /* Parallel Mode Timing */ | 77 | /* Parallel Mode Timing */ |
77 | u_char hsync_len; | 78 | u_char hsync_len; |
diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h index f762493f5141..820a189684a9 100644 --- a/include/asm-arm/arch-pxa/regs-lcd.h +++ b/include/asm-arm/arch-pxa/regs-lcd.h | |||
@@ -1,5 +1,8 @@ | |||
1 | #ifndef __ASM_ARCH_REGS_LCD_H | 1 | #ifndef __ASM_ARCH_REGS_LCD_H |
2 | #define __ASM_ARCH_REGS_LCD_H | 2 | #define __ASM_ARCH_REGS_LCD_H |
3 | |||
4 | #include <asm/arch/bitfield.h> | ||
5 | |||
3 | /* | 6 | /* |
4 | * LCD Controller Registers and Bits Definitions | 7 | * LCD Controller Registers and Bits Definitions |
5 | */ | 8 | */ |
@@ -24,6 +27,12 @@ | |||
24 | #define LCCR3_4BPP (2 << 24) | 27 | #define LCCR3_4BPP (2 << 24) |
25 | #define LCCR3_8BPP (3 << 24) | 28 | #define LCCR3_8BPP (3 << 24) |
26 | #define LCCR3_16BPP (4 << 24) | 29 | #define LCCR3_16BPP (4 << 24) |
30 | #define LCCR3_18BPP (5 << 24) | ||
31 | #define LCCR3_18BPP_P (6 << 24) | ||
32 | #define LCCR3_19BPP (7 << 24) | ||
33 | #define LCCR3_19BPP_P (1 << 29) | ||
34 | #define LCCR3_24BPP ((1 << 29) | (1 << 24)) | ||
35 | #define LCCR3_25BPP ((1 << 29) | (2 << 24)) | ||
27 | 36 | ||
28 | #define LCCR3_PDFOR_0 (0 << 30) | 37 | #define LCCR3_PDFOR_0 (0 << 30) |
29 | #define LCCR3_PDFOR_1 (1 << 30) | 38 | #define LCCR3_PDFOR_1 (1 << 30) |
@@ -69,7 +78,7 @@ | |||
69 | #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ | 78 | #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ |
70 | #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ | 79 | #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ |
71 | #define LCCR0_PDD_S 12 | 80 | #define LCCR0_PDD_S 12 |
72 | #define LCCR0_BM (1 << 20) /* Branch mask */ | 81 | #define LCCR0_BM (1 << 20) /* Branch mask */ |
73 | #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ | 82 | #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ |
74 | #define LCCR0_LCDT (1 << 22) /* LCD panel type */ | 83 | #define LCCR0_LCDT (1 << 22) /* LCD panel type */ |
75 | #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ | 84 | #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ |