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-rw-r--r--include/asm-arm/arch-pxa/pxafb.h151
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diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
deleted file mode 100644
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1/*
2 * linux/include/asm-arm/arch-pxa/pxafb.h
3 *
4 * Support for the xscale frame buffer.
5 *
6 * Author: Jean-Frederic Clere
7 * Created: Sep 22, 2003
8 * Copyright: jfclere@sinix.net
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/fb.h>
16#include <asm/arch/regs-lcd.h>
17
18/*
19 * Supported LCD connections
20 *
21 * bits 0 - 3: for LCD panel type:
22 *
23 * STN - for passive matrix
24 * DSTN - for dual scan passive matrix
25 * TFT - for active matrix
26 *
27 * bits 4 - 9 : for bus width
28 * bits 10-17 : for AC Bias Pin Frequency
29 * bit 18 : for output enable polarity
30 * bit 19 : for pixel clock edge
31 */
32#define LCD_CONN_TYPE(_x) ((_x) & 0x0f)
33#define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f)
34
35#define LCD_TYPE_UNKNOWN 0
36#define LCD_TYPE_MONO_STN 1
37#define LCD_TYPE_MONO_DSTN 2
38#define LCD_TYPE_COLOR_STN 3
39#define LCD_TYPE_COLOR_DSTN 4
40#define LCD_TYPE_COLOR_TFT 5
41#define LCD_TYPE_SMART_PANEL 6
42#define LCD_TYPE_MAX 7
43
44#define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN)
45#define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN)
46#define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN)
47#define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN)
48#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
49#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
50#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
51#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
52#define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL)
53#define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL)
54
55#define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
56#define LCD_BIAS_ACTIVE_HIGH (0 << 17)
57#define LCD_BIAS_ACTIVE_LOW (1 << 17)
58#define LCD_PCLK_EDGE_RISE (0 << 18)
59#define LCD_PCLK_EDGE_FALL (1 << 18)
60
61/*
62 * This structure describes the machine which we are running on.
63 * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
64 * of linux/drivers/video/pxafb.c
65 */
66struct pxafb_mode_info {
67 u_long pixclock;
68
69 u_short xres;
70 u_short yres;
71
72 u_char bpp;
73 u_int cmap_greyscale:1,
74 depth:8,
75 unused:23;
76
77 /* Parallel Mode Timing */
78 u_char hsync_len;
79 u_char left_margin;
80 u_char right_margin;
81
82 u_char vsync_len;
83 u_char upper_margin;
84 u_char lower_margin;
85 u_char sync;
86
87 /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
88 * Note:
89 * 1. all parameters in nanosecond (ns)
90 * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
91 * in pxa27x and pxa3xx, initialize them to the same value or
92 * the larger one will be used
93 * 3. same to {rd,wr}_pulse_width
94 */
95 unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
96 unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
97 unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
98 unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
99 unsigned cmd_inh_time; /* Command Inhibit time between two writes */
100 unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
101};
102
103struct pxafb_mach_info {
104 struct pxafb_mode_info *modes;
105 unsigned int num_modes;
106
107 unsigned int lcd_conn;
108
109 u_int fixed_modes:1,
110 cmap_inverse:1,
111 cmap_static:1,
112 unused:29;
113
114 /* The following should be defined in LCCR0
115 * LCCR0_Act or LCCR0_Pas Active or Passive
116 * LCCR0_Sngl or LCCR0_Dual Single/Dual panel
117 * LCCR0_Mono or LCCR0_Color Mono/Color
118 * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
119 * LCCR0_DMADel(Tcpu) (optional) DMA request delay
120 *
121 * The following should not be defined in LCCR0:
122 * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
123 * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
124 */
125 u_int lccr0;
126 /* The following should be defined in LCCR3
127 * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
128 * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
129 * LCCR3_Acb(X) AB Bias pin frequency
130 * LCCR3_DPC (optional) Double Pixel Clock mode (untested)
131 *
132 * The following should not be defined in LCCR3
133 * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
134 */
135 u_int lccr3;
136 /* The following should be defined in LCCR4
137 * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
138 *
139 * All other bits in LCCR4 should be left alone.
140 */
141 u_int lccr4;
142 void (*pxafb_backlight_power)(int);
143 void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
144 void (*smart_update)(struct fb_info *);
145};
146void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
147void set_pxa_fb_parent(struct device *parent_dev);
148unsigned long pxafb_get_hsync_time(struct device *dev);
149
150extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
151extern int pxafb_smart_flush(struct fb_info *info);
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