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-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h370
1 files changed, 72 insertions, 298 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 1bd398da07da..442494d71f12 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1597,176 +1597,10 @@
1597#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ 1597#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1598#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ 1598#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1599 1599
1600
1601/* 1600/*
1602 * SSP Serial Port Registers 1601 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
1603 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
1604 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
1605 */ 1602 */
1606 1603
1607 /* Common PXA2xx bits first */
1608#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
1609#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
1610#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
1611#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
1612#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
1613#define SSCR0_National (0x2 << 4) /* National Microwire */
1614#define SSCR0_ECS (1 << 6) /* External clock select */
1615#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
1616#if defined(CONFIG_PXA25x)
1617#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
1618#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
1619#elif defined(CONFIG_PXA27x)
1620#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
1621#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
1622#define SSCR0_EDSS (1 << 20) /* Extended data size select */
1623#define SSCR0_NCS (1 << 21) /* Network clock select */
1624#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
1625#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
1626#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
1627#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
1628#define SSCR0_ADC (1 << 30) /* Audio clock select */
1629#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
1630#endif
1631
1632#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
1633#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
1634#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
1635#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
1636#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
1637#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
1638#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
1639#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
1640#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
1641#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
1642
1643#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
1644#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
1645#define SSSR_BSY (1 << 4) /* SSP Busy */
1646#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
1647#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
1648#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
1649
1650#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
1651#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
1652#define SSCR0_NCS (1 << 21) /* Network Clock Select */
1653#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
1654
1655/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
1656#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
1657#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
1658#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
1659#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
1660#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
1661#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
1662#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
1663#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
1664#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
1665#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
1666#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
1667#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
1668#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
1669#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
1670#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
1671#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
1672#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
1673#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
1674
1675#define SSSR_BCE (1 << 23) /* Bit Count Error */
1676#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
1677#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
1678#define SSSR_EOC (1 << 20) /* End Of Chain */
1679#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
1680#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
1681
1682#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
1683#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
1684#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
1685#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
1686#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
1687#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
1688#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
1689#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
1690#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
1691
1692#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
1693#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
1694#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
1695
1696#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
1697#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
1698#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
1699#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
1700#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
1701
1702/* Support existing PXA25x drivers */
1703#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
1704#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
1705#define SSSR SSSR_P1 /* SSP Status Register */
1706#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
1707#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
1708
1709/* PXA27x ports */
1710#if defined (CONFIG_PXA27x)
1711#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1712#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1713#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
1714#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
1715#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
1716#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
1717#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
1718#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
1719#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
1720#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
1721#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1722#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
1723#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
1724#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
1725#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
1726#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
1727#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
1728#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
1729#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
1730#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
1731#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
1732#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1733#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
1734#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
1735#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
1736#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
1737#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
1738#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
1739#else /* PXA255 (only port 2) and PXA26x ports*/
1740#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1741#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1742#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
1743#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
1744#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
1745#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
1746#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1747#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
1748#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
1749#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
1750#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
1751#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
1752#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
1753#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1754#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
1755#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
1756#endif
1757
1758#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
1759#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
1760#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
1761#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
1762#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
1763#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
1764#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
1765#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
1766#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
1767#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
1768#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
1769
1770/* 1604/*
1771 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h 1605 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
1772 */ 1606 */
@@ -2014,71 +1848,8 @@
2014 1848
2015#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ 1849#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
2016 1850
2017/*
2018 * Memory controller
2019 */
2020
2021#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
2022#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
2023#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
2024#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
2025#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
2026#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2027#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
2028#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
2029#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
2030#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
2031#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
2032#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
2033#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
2034#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
2035#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
2036#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
2037#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
2038
2039/*
2040 * More handy macros for PCMCIA
2041 *
2042 * Arg is socket number
2043 */
2044#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
2045#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
2046#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
2047
2048/* MECR register defines */
2049#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
2050#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
2051
2052#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
2053#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
2054#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
2055#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
2056#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
2057#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
2058#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
2059#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
2060#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
2061#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
2062#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
2063#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
2064#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
2065#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
2066
2067
2068#ifdef CONFIG_PXA27x 1851#ifdef CONFIG_PXA27x
2069 1852
2070#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
2071
2072#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
2073#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
2074#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
2075#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
2076#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
2077#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
2078#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
2079#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
2080#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
2081
2082/* 1853/*
2083 * Keypad 1854 * Keypad
2084 */ 1855 */
@@ -2135,74 +1906,6 @@
2135#define KPAS_SO (0x1 << 31) 1906#define KPAS_SO (0x1 << 31)
2136#define KPASMKPx_SO (0x1 << 31) 1907#define KPASMKPx_SO (0x1 << 31)
2137 1908
2138/*
2139 * UHC: USB Host Controller (OHCI-like) register definitions
2140 */
2141#define UHC_BASE_PHYS (0x4C000000)
2142#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
2143#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
2144#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
2145#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
2146#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
2147#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
2148#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
2149#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
2150#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
2151#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
2152#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
2153#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
2154#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
2155#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
2156#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
2157#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2158#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2159#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2160
2161#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2162#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
2163
2164#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2165#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2166#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
2167#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
2168#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
2169
2170#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
2171#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
2172#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
2173#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
2174#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
2175#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
2176#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
2177#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
2178#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
2179#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
2180
2181#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
2182#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
2183#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
2184#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
2185#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
2186#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
2187#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
2188#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
2189#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
2190#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
2191#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
2192#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
2193
2194#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
2195#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
2196#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
2197#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
2198#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
2199#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
2200 Interrupt Enable*/
2201#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
2202#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
2203
2204#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
2205
2206/* Camera Interface */ 1909/* Camera Interface */
2207#define CICR0 __REG(0x50000000) 1910#define CICR0 __REG(0x50000000)
2208#define CICR1 __REG(0x50000004) 1911#define CICR1 __REG(0x50000004)
@@ -2350,6 +2053,77 @@
2350 2053
2351#endif 2054#endif
2352 2055
2056#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
2057/*
2058 * UHC: USB Host Controller (OHCI-like) register definitions
2059 */
2060#define UHC_BASE_PHYS (0x4C000000)
2061#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
2062#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
2063#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
2064#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
2065#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
2066#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
2067#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
2068#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
2069#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
2070#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
2071#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
2072#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
2073#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
2074#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
2075#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
2076#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2077#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2078#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2079
2080#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2081#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
2082
2083#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2084#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2085#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
2086#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
2087#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
2088
2089#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
2090#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
2091#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
2092#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
2093#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
2094#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
2095#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
2096#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
2097#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
2098#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
2099
2100#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
2101#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
2102#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
2103#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
2104#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
2105#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
2106#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
2107#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
2108#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
2109#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
2110#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
2111#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
2112
2113#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
2114#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
2115#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
2116#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
2117#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
2118#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
2119 Interrupt Enable*/
2120#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
2121#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
2122
2123#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
2124
2125#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
2126
2353/* PWRMODE register M field values */ 2127/* PWRMODE register M field values */
2354 2128
2355#define PWRMODE_IDLE 0x1 2129#define PWRMODE_IDLE 0x1
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 03:46:28 -0500