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diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
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1/*
2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __PXA_REGS_H
14#define __PXA_REGS_H
15
16#include <linux/config.h>
17
18/*
19 * PXA Chip selects
20 */
21
22#define PXA_CS0_PHYS 0x00000000
23#define PXA_CS1_PHYS 0x04000000
24#define PXA_CS2_PHYS 0x08000000
25#define PXA_CS3_PHYS 0x0C000000
26#define PXA_CS4_PHYS 0x10000000
27#define PXA_CS5_PHYS 0x14000000
28
29
30/*
31 * Personal Computer Memory Card International Association (PCMCIA) sockets
32 */
33
34#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
35#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
36#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
37#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
38#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
39
40#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
41#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
42#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
43#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
44
45#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
46#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
47#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
48#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
49
50#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
51 (0x20000000 + (Nb)*PCMCIASp)
52#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
53#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
54 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
55#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
56 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
57
58#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
59#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
60#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
61#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
62
63#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
64#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
65#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
66#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
67
68
69
70/*
71 * DMA Controller
72 */
73
74#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
75#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
76#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
77#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
78#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
79#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
80#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
81#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
82#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
83#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
84#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
85#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
86#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
87#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
88#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
89#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
90
91#define DCSR(x) __REG2(0x40000000, (x) << 2)
92
93#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
94#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
95#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
96#ifdef CONFIG_PXA27x
97#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
98#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
99#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
100#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
101#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
102#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
103#define DCSR_ENRINTR (1 << 9) /* The end of Receive */
104#endif
105#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
106#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
107#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
108#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
109#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
110
111#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
112
113#define DRCMR(n) __REG2(0x40000100, (n)<<2)
114#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
115#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
116#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
117#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
118#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
119#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
120#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
121#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
122#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
123#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
124#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
125#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
126#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
127#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
128#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
129#define DRCMR15 __REG(0x4000013c) /* Reserved */
130#define DRCMR16 __REG(0x40000140) /* Reserved */
131#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
132#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
133#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
134#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
135#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
136#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
137#define DRCMR23 __REG(0x4000015c) /* Reserved */
138#define DRCMR24 __REG(0x40000160) /* Reserved */
139#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
140#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
141#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
142#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
143#define DRCMR29 __REG(0x40000174) /* Reserved */
144#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
145#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
146#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
147#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
148#define DRCMR34 __REG(0x40000188) /* Reserved */
149#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
150#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
151#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
152#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
153#define DRCMR39 __REG(0x4000019C) /* Reserved */
154
155#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
156#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
157#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
158
159#define DRCMRRXSADR DRCMR2
160#define DRCMRTXSADR DRCMR3
161#define DRCMRRXBTRBR DRCMR4
162#define DRCMRTXBTTHR DRCMR5
163#define DRCMRRXFFRBR DRCMR6
164#define DRCMRTXFFTHR DRCMR7
165#define DRCMRRXMCDR DRCMR8
166#define DRCMRRXMODR DRCMR9
167#define DRCMRTXMODR DRCMR10
168#define DRCMRRXPCDR DRCMR11
169#define DRCMRTXPCDR DRCMR12
170#define DRCMRRXSSDR DRCMR13
171#define DRCMRTXSSDR DRCMR14
172#define DRCMRRXSS2DR DRCMR15
173#define DRCMRTXSS2DR DRCMR16
174#define DRCMRRXICDR DRCMR17
175#define DRCMRTXICDR DRCMR18
176#define DRCMRRXSTRBR DRCMR19
177#define DRCMRTXSTTHR DRCMR20
178#define DRCMRRXMMC DRCMR21
179#define DRCMRTXMMC DRCMR22
180#define DRCMRRXSS3DR DRCMR66
181#define DRCMRTXSS3DR DRCMR67
182#define DRCMRUDC(x) DRCMR((x) + 24)
183
184#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
185#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
186
187#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
188#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
189#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
190#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
191#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
192#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
193#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
194#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
195#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
196#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
197#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
198#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
199#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
200#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
201#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
202#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
203#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
204#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
205#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
206#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
207#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
208#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
209#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
210#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
211#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
212#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
213#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
214#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
215#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
216#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
217#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
218#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
219#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
220#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
221#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
222#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
223#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
224#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
225#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
226#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
227#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
228#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
229#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
230#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
231#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
232#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
233#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
234#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
235#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
236#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
237#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
238#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
239#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
240#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
241#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
242#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
243#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
244#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
245#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
246#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
247#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
248#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
249#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
250#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
251
252#define DDADR(x) __REG2(0x40000200, (x) << 4)
253#define DSADR(x) __REG2(0x40000204, (x) << 4)
254#define DTADR(x) __REG2(0x40000208, (x) << 4)
255#define DCMD(x) __REG2(0x4000020c, (x) << 4)
256
257#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
258#define DDADR_STOP (1 << 0) /* Stop (read / write) */
259
260#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
261#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
262#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
263#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
264#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
265#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
266#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
267#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
268#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
269#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
270#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
271#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
272#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
273#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
274
275
276/*
277 * UARTs
278 */
279
280/* Full Function UART (FFUART) */
281#define FFUART FFRBR
282#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
283#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
284#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
285#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
286#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
287#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
288#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
289#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
290#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
291#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
292#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
293#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
294#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
295
296/* Bluetooth UART (BTUART) */
297#define BTUART BTRBR
298#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
299#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
300#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
301#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
302#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
303#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
304#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
305#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
306#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
307#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
308#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
309#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
310#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
311
312/* Standard UART (STUART) */
313#define STUART STRBR
314#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
315#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
316#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
317#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
318#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
319#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
320#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
321#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
322#define STMSR __REG(0x40700018) /* Reserved */
323#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
324#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
325#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
326#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
327
328#define IER_DMAE (1 << 7) /* DMA Requests Enable */
329#define IER_UUE (1 << 6) /* UART Unit Enable */
330#define IER_NRZE (1 << 5) /* NRZ coding Enable */
331#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
332#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
333#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
334#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
335#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
336
337#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
338#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
339#define IIR_TOD (1 << 3) /* Time Out Detected */
340#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
341#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
342#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
343
344#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
345#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
346#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
347#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
348#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
349#define FCR_ITL_1 (0)
350#define FCR_ITL_8 (FCR_ITL1)
351#define FCR_ITL_16 (FCR_ITL2)
352#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
353
354#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
355#define LCR_SB (1 << 6) /* Set Break */
356#define LCR_STKYP (1 << 5) /* Sticky Parity */
357#define LCR_EPS (1 << 4) /* Even Parity Select */
358#define LCR_PEN (1 << 3) /* Parity Enable */
359#define LCR_STB (1 << 2) /* Stop Bit */
360#define LCR_WLS1 (1 << 1) /* Word Length Select */
361#define LCR_WLS0 (1 << 0) /* Word Length Select */
362
363#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
364#define LSR_TEMT (1 << 6) /* Transmitter Empty */
365#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
366#define LSR_BI (1 << 4) /* Break Interrupt */
367#define LSR_FE (1 << 3) /* Framing Error */
368#define LSR_PE (1 << 2) /* Parity Error */
369#define LSR_OE (1 << 1) /* Overrun Error */
370#define LSR_DR (1 << 0) /* Data Ready */
371
372#define MCR_LOOP (1 << 4)
373#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
374#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
375#define MCR_RTS (1 << 1) /* Request to Send */
376#define MCR_DTR (1 << 0) /* Data Terminal Ready */
377
378#define MSR_DCD (1 << 7) /* Data Carrier Detect */
379#define MSR_RI (1 << 6) /* Ring Indicator */
380#define MSR_DSR (1 << 5) /* Data Set Ready */
381#define MSR_CTS (1 << 4) /* Clear To Send */
382#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
383#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
384#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
385#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
386
387/*
388 * IrSR (Infrared Selection Register)
389 */
390#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
391#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
392#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
393#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
394#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
395
396
397/*
398 * I2C registers
399 */
400
401#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
402#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
403#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
404#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
405#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
406
407#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
408#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
409#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
410#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
411#define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
412
413#define ICR_START (1 << 0) /* start bit */
414#define ICR_STOP (1 << 1) /* stop bit */
415#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
416#define ICR_TB (1 << 3) /* transfer byte bit */
417#define ICR_MA (1 << 4) /* master abort */
418#define ICR_SCLE (1 << 5) /* master clock enable */
419#define ICR_IUE (1 << 6) /* unit enable */
420#define ICR_GCD (1 << 7) /* general call disable */
421#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
422#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
423#define ICR_BEIE (1 << 10) /* enable bus error ints */
424#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
425#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
426#define ICR_SADIE (1 << 13) /* slave address detected int enable */
427#define ICR_UR (1 << 14) /* unit reset */
428
429#define ISR_RWM (1 << 0) /* read/write mode */
430#define ISR_ACKNAK (1 << 1) /* ack/nak status */
431#define ISR_UB (1 << 2) /* unit busy */
432#define ISR_IBB (1 << 3) /* bus busy */
433#define ISR_SSD (1 << 4) /* slave stop detected */
434#define ISR_ALD (1 << 5) /* arbitration loss detected */
435#define ISR_ITE (1 << 6) /* tx buffer empty */
436#define ISR_IRF (1 << 7) /* rx buffer full */
437#define ISR_GCAD (1 << 8) /* general call address detected */
438#define ISR_SAD (1 << 9) /* slave address detected */
439#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
440
441
442/*
443 * Serial Audio Controller
444 */
445
446/* FIXME: This clash with SA1111 defines */
447#ifndef _ASM_ARCH_SA1111
448
449#define SACR0 __REG(0x40400000) /* Global Control Register */
450#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
451#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
452#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
453#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
454#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
455#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
456
457#define SACR0_RFTH(x) (x << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
458#define SACR0_TFTH(x) (x << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
459#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
460#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
461#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
462#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
463#define SACR0_ENB (1 << 0) /* Enable I2S Link */
464#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
465#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
466#define SACR1_DREC (1 << 3) /* Disable Recording Function */
467#define SACR1_AMSL (1 << 1) /* Specify Alternate Mode */
468
469#define SASR0_I2SOFF (1 << 7) /* Controller Status */
470#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
471#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
472#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
473#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
474#define SASR0_BSY (1 << 2) /* I2S Busy */
475#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
476#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
477
478#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
479#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
480
481#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
482#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
483#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
484#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
485
486#endif
487
488/*
489 * AC97 Controller registers
490 */
491
492#define POCR __REG(0x40500000) /* PCM Out Control Register */
493#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
494#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
495
496#define PICR __REG(0x40500004) /* PCM In Control Register */
497#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
498#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
499
500#define MCCR __REG(0x40500008) /* Mic In Control Register */
501#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
502#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
503
504#define GCR __REG(0x4050000C) /* Global Control Register */
505#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
506#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
507#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
508#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
509#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
510#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
511#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
512#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
513#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
514#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
515#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
516
517#define POSR __REG(0x40500010) /* PCM Out Status Register */
518#define POSR_FIFOE (1 << 4) /* FIFO error */
519#define POSR_FSR (1 << 2) /* FIFO Service Request */
520
521#define PISR __REG(0x40500014) /* PCM In Status Register */
522#define PISR_FIFOE (1 << 4) /* FIFO error */
523#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
524#define PISR_FSR (1 << 2) /* FIFO Service Request */
525
526#define MCSR __REG(0x40500018) /* Mic In Status Register */
527#define MCSR_FIFOE (1 << 4) /* FIFO error */
528#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
529#define MCSR_FSR (1 << 2) /* FIFO Service Request */
530
531#define GSR __REG(0x4050001C) /* Global Status Register */
532#define GSR_CDONE (1 << 19) /* Command Done */
533#define GSR_SDONE (1 << 18) /* Status Done */
534#define GSR_RDCS (1 << 15) /* Read Completion Status */
535#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
536#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
537#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
538#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
539#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
540#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
541#define GSR_PCR (1 << 8) /* Primary Codec Ready */
542#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
543#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
544#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
545#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
546#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
547#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
548#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
549
550#define CAR __REG(0x40500020) /* CODEC Access Register */
551#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
552
553#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
554#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
555
556#define MOCR __REG(0x40500100) /* Modem Out Control Register */
557#define MOCR_FEIE (1 << 3) /* FIFO Error */
558#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
559
560#define MICR __REG(0x40500108) /* Modem In Control Register */
561#define MICR_FEIE (1 << 3) /* FIFO Error */
562#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
563
564#define MOSR __REG(0x40500110) /* Modem Out Status Register */
565#define MOSR_FIFOE (1 << 4) /* FIFO error */
566#define MOSR_FSR (1 << 2) /* FIFO Service Request */
567
568#define MISR __REG(0x40500118) /* Modem In Status Register */
569#define MISR_FIFOE (1 << 4) /* FIFO error */
570#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
571#define MISR_FSR (1 << 2) /* FIFO Service Request */
572
573#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
574
575#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
576#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
577#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
578#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
579
580
581/*
582 * USB Device Controller
583 * PXA25x and PXA27x USB device controller registers are different.
584 */
585#if defined(CONFIG_PXA25x)
586
587#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
588#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
589#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
590
591#define UDCCR __REG(0x40600000) /* UDC Control Register */
592#define UDCCR_UDE (1 << 0) /* UDC enable */
593#define UDCCR_UDA (1 << 1) /* UDC active */
594#define UDCCR_RSM (1 << 2) /* Device resume */
595#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
596#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
597#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
598#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
599#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
600
601#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
602#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
603#define UDCCS0_IPR (1 << 1) /* IN packet ready */
604#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
605#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
606#define UDCCS0_SST (1 << 4) /* Sent stall */
607#define UDCCS0_FST (1 << 5) /* Force stall */
608#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
609#define UDCCS0_SA (1 << 7) /* Setup active */
610
611/* Bulk IN - Endpoint 1,6,11 */
612#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
613#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
614#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
615
616#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
617#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
618#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
619#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
620#define UDCCS_BI_SST (1 << 4) /* Sent stall */
621#define UDCCS_BI_FST (1 << 5) /* Force stall */
622#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
623
624/* Bulk OUT - Endpoint 2,7,12 */
625#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
626#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
627#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
628
629#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
630#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
631#define UDCCS_BO_DME (1 << 3) /* DMA enable */
632#define UDCCS_BO_SST (1 << 4) /* Sent stall */
633#define UDCCS_BO_FST (1 << 5) /* Force stall */
634#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
635#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
636
637/* Isochronous IN - Endpoint 3,8,13 */
638#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
639#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
640#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
641
642#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
643#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
644#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
645#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
646#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
647
648/* Isochronous OUT - Endpoint 4,9,14 */
649#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
650#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
651#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
652
653#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
654#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
655#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
656#define UDCCS_IO_DME (1 << 3) /* DMA enable */
657#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
658#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
659
660/* Interrupt IN - Endpoint 5,10,15 */
661#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
662#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
663#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
664
665#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
666#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
667#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
668#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
669#define UDCCS_INT_SST (1 << 4) /* Sent stall */
670#define UDCCS_INT_FST (1 << 5) /* Force stall */
671#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
672
673#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
674#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
675#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
676#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
677#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
678#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
679#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
680#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
681#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
682#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
683#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
684#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
685#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
686#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
687#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
688#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
689#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
690#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
691#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
692#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
693#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
694#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
695#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
696#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
697
698#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
699
700#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
701#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
702#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
703#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
704#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
705#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
706#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
707#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
708
709#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
710
711#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
712#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
713#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
714#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
715#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
716#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
717#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
718#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
719
720#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
721
722#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
723#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
724#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
725#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
726#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
727#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
728#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
729#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
730
731#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
732
733#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
734#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
735#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
736#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
737#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
738#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
739#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
740#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
741
742#elif defined(CONFIG_PXA27x)
743
744#define UDCCR __REG(0x40600000) /* UDC Control Register */
745#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
746#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
747 Protocol Port Support */
748#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
749 Support */
750#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
751 Enable */
752#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
753#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
754#define UDCCR_ACN_S 11
755#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
756#define UDCCR_AIN_S 8
757#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
758 Setting Number */
759#define UDCCR_AAISN_S 5
760#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
761 Configuration */
762#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
763 Error */
764#define UDCCR_UDR (1 << 2) /* UDC Resume */
765#define UDCCR_UDA (1 << 1) /* UDC Active */
766#define UDCCR_UDE (1 << 0) /* UDC Enable */
767
768#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
769#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
770#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
771#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
772
773#define UDC_INT_FIFOERROR (0x2)
774#define UDC_INT_PACKETCMP (0x1)
775
776#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
777#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
778#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
779#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
780#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
781#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
782
783#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
784#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
785#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
786#define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */
787#define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */
788#define UDCISR1_IERU (1 << 29) /* IntEn - Resume */
789#define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */
790#define UDCISR1_IERS (1 << 27) /* IntEn - Reset */
791
792
793#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
794#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
795#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
796#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
797 Rising Edge Interrupt Enable */
798#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
799 Falling Edge Interrupt Enable */
800#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
801 Interrupt Enable */
802#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
803 Interrupt Enable */
804#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
805 Interrupt Enable */
806#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
807 Interrupt Enable */
808#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
809 Interrupt Enable */
810#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
811 Interrupt Enable */
812#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
813 Edge Interrupt Enable */
814#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
815 Edge Interrupt Enable */
816#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
817 Interrupt Enable */
818#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
819 Interrupt Enable */
820
821#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
822#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
823#define UDCCSR0_SA (1 << 7) /* Setup Active */
824#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
825#define UDCCSR0_FST (1 << 5) /* Force Stall */
826#define UDCCSR0_SST (1 << 4) /* Sent Stall */
827#define UDCCSR0_DME (1 << 3) /* DMA Enable */
828#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
829#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
830#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
831
832#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
833#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
834#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
835#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
836#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
837#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
838#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
839#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
840#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
841#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
842#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
843#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
844#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
845#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
846#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
847#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
848#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
849#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
850#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
851#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
852#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
853#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
854#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
855
856#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
857#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
858#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
859#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
860#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
861#define UDCCSR_FST (1 << 5) /* Force STALL */
862#define UDCCSR_SST (1 << 4) /* Sent STALL */
863#define UDCCSR_DME (1 << 3) /* DMA Enable */
864#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
865#define UDCCSR_PC (1 << 1) /* Packet Complete */
866#define UDCCSR_FS (1 << 0) /* FIFO needs service */
867
868#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
869#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
870#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
871#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
872#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
873#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
874#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
875#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
876#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
877#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
878#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
879#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
880#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
881#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
882#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
883#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
884#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
885#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
886#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
887#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
888#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
889#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
890#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
891#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
892#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
893
894#define UDCDN(x) __REG2(0x40600300, (x)<<2)
895#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
896#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
897#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
898#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
899#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
900#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
901#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
902#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
903#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
904#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
905#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
906#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
907#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
908#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
909#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
910#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
911#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
912#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
913#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
914#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
915#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
916#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
917#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
918#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
919#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
920#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
921
922#define UDCCN(x) __REG2(0x40600400, (x)<<2)
923#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
924#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
925#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
926#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
927#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
928#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
929#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
930#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
931#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
932#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
933#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
934#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
935#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
936#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
937#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
938#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
939#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
940#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
941#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
942#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
943#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
944#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
945#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
946
947#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
948#define UDCCONR_CN_S (25)
949#define UDCCONR_IN (0x07 << 22) /* Interface Number */
950#define UDCCONR_IN_S (22)
951#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
952#define UDCCONR_AISN_S (19)
953#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
954#define UDCCONR_EN_S (15)
955#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
956#define UDCCONR_ET_S (13)
957#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
958#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
959#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
960#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
961#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
962#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
963#define UDCCONR_MPS_S (2)
964#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
965#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
966
967
968#define UDC_INT_FIFOERROR (0x2)
969#define UDC_INT_PACKETCMP (0x1)
970
971#define UDC_FNR_MASK (0x7ff)
972
973#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
974#define UDC_BCR_MASK (0x3ff)
975#endif
976
977/*
978 * Fast Infrared Communication Port
979 */
980
981#define FICP __REG(0x40800000) /* Start of FICP area */
982#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
983#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
984#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
985#define ICDR __REG(0x4080000c) /* ICP Data Register */
986#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
987#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
988
989#define ICCR0_AME (1 << 7) /* Adress match enable */
990#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
991#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
992#define ICCR0_RXE (1 << 4) /* Receive enable */
993#define ICCR0_TXE (1 << 3) /* Transmit enable */
994#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
995#define ICCR0_LBM (1 << 1) /* Loopback mode */
996#define ICCR0_ITR (1 << 0) /* IrDA transmission */
997
998#ifdef CONFIG_PXA27x
999#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
1000#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
1001#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
1002#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
1003#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
1004#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
1005#endif
1006
1007#ifdef CONFIG_PXA27x
1008#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
1009#endif
1010#define ICSR0_FRE (1 << 5) /* Framing error */
1011#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
1012#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
1013#define ICSR0_RAB (1 << 2) /* Receiver abort */
1014#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
1015#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
1016
1017#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
1018#define ICSR1_CRE (1 << 5) /* CRC error */
1019#define ICSR1_EOF (1 << 4) /* End of frame */
1020#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
1021#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
1022#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
1023#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
1024
1025
1026/*
1027 * Real Time Clock
1028 */
1029
1030#define RCNR __REG(0x40900000) /* RTC Count Register */
1031#define RTAR __REG(0x40900004) /* RTC Alarm Register */
1032#define RTSR __REG(0x40900008) /* RTC Status Register */
1033#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
1034#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
1035
1036#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
1037#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
1038#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
1039#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
1040#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
1041#define RTSR_AL (1 << 0) /* RTC alarm detected */
1042
1043
1044/*
1045 * OS Timer & Match Registers
1046 */
1047
1048#define OSMR0 __REG(0x40A00000) /* */
1049#define OSMR1 __REG(0x40A00004) /* */
1050#define OSMR2 __REG(0x40A00008) /* */
1051#define OSMR3 __REG(0x40A0000C) /* */
1052#define OSMR4 __REG(0x40A00080) /* */
1053#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
1054#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
1055#define OMCR4 __REG(0x40A000C0) /* */
1056#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
1057#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
1058#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
1059
1060#define OSSR_M3 (1 << 3) /* Match status channel 3 */
1061#define OSSR_M2 (1 << 2) /* Match status channel 2 */
1062#define OSSR_M1 (1 << 1) /* Match status channel 1 */
1063#define OSSR_M0 (1 << 0) /* Match status channel 0 */
1064
1065#define OWER_WME (1 << 0) /* Watchdog Match Enable */
1066
1067#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
1068#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
1069#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
1070#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
1071
1072
1073/*
1074 * Pulse Width Modulator
1075 */
1076
1077#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
1078#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
1079#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
1080
1081#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
1082#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
1083#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
1084
1085
1086/*
1087 * Interrupt Controller
1088 */
1089
1090#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
1091#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
1092#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
1093#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
1094#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
1095#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
1096
1097
1098/*
1099 * General Purpose I/O
1100 */
1101
1102#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
1103#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
1104#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
1105
1106#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
1107#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
1108#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
1109
1110#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
1111#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
1112#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
1113
1114#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
1115#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
1116#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
1117
1118#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
1119#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
1120#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
1121
1122#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1123#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
1124#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
1125
1126#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
1127#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
1128#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
1129
1130#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
1131#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
1132#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
1133#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
1134#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
1135#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
1136#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
1137#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
1138
1139#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
1140#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
1141#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
1142#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
1143#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1144#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
1145#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
1146
1147/* More handy macros. The argument is a literal GPIO number. */
1148
1149#define GPIO_bit(x) (1 << ((x) & 0x1f))
1150
1151#ifdef CONFIG_PXA27x
1152
1153/* Interrupt Controller */
1154
1155#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
1156#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
1157#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
1158#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
1159#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
1160
1161#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1162#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1163#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1164#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1165#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1166#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1167#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1168#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1169
1170#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
1171#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
1172#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
1173#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
1174#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
1175#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
1176#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
1177#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
1178 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
1179#else
1180
1181#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1182#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1183#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1184#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1185#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1186#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1187#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1188#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1189
1190#endif
1191
1192
1193/* GPIO alternate function assignments */
1194
1195#define GPIO1_RST 1 /* reset */
1196#define GPIO6_MMCCLK 6 /* MMC Clock */
1197#define GPIO7_48MHz 7 /* 48 MHz clock output */
1198#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
1199#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
1200#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
1201#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
1202#define GPIO12_32KHz 12 /* 32 kHz out */
1203#define GPIO13_MBGNT 13 /* memory controller grant */
1204#define GPIO14_MBREQ 14 /* alternate bus master request */
1205#define GPIO15_nCS_1 15 /* chip select 1 */
1206#define GPIO16_PWM0 16 /* PWM0 output */
1207#define GPIO17_PWM1 17 /* PWM1 output */
1208#define GPIO18_RDY 18 /* Ext. Bus Ready */
1209#define GPIO19_DREQ1 19 /* External DMA Request */
1210#define GPIO20_DREQ0 20 /* External DMA Request */
1211#define GPIO23_SCLK 23 /* SSP clock */
1212#define GPIO24_SFRM 24 /* SSP Frame */
1213#define GPIO25_STXD 25 /* SSP transmit */
1214#define GPIO26_SRXD 26 /* SSP receive */
1215#define GPIO27_SEXTCLK 27 /* SSP ext_clk */
1216#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
1217#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
1218#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
1219#define GPIO31_SYNC 31 /* AC97/I2S sync */
1220#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
1221#define GPIO32_SYSCLK 32 /* I2S System Clock */
1222#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */
1223#define GPIO33_nCS_5 33 /* chip select 5 */
1224#define GPIO34_FFRXD 34 /* FFUART receive */
1225#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
1226#define GPIO35_FFCTS 35 /* FFUART Clear to send */
1227#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
1228#define GPIO37_FFDSR 37 /* FFUART data set ready */
1229#define GPIO38_FFRI 38 /* FFUART Ring Indicator */
1230#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
1231#define GPIO39_FFTXD 39 /* FFUART transmit data */
1232#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
1233#define GPIO41_FFRTS 41 /* FFUART request to send */
1234#define GPIO42_BTRXD 42 /* BTUART receive data */
1235#define GPIO43_BTTXD 43 /* BTUART transmit data */
1236#define GPIO44_BTCTS 44 /* BTUART clear to send */
1237#define GPIO45_BTRTS 45 /* BTUART request to send */
1238#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
1239#define GPIO46_ICPRXD 46 /* ICP receive data */
1240#define GPIO46_STRXD 46 /* STD_UART receive data */
1241#define GPIO47_ICPTXD 47 /* ICP transmit data */
1242#define GPIO47_STTXD 47 /* STD_UART transmit data */
1243#define GPIO48_nPOE 48 /* Output Enable for Card Space */
1244#define GPIO49_nPWE 49 /* Write Enable for Card Space */
1245#define GPIO50_nPIOR 50 /* I/O Read for Card Space */
1246#define GPIO51_nPIOW 51 /* I/O Write for Card Space */
1247#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
1248#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
1249#define GPIO53_MMCCLK 53 /* MMC Clock */
1250#define GPIO54_MMCCLK 54 /* MMC Clock */
1251#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
1252#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */
1253#define GPIO55_nPREG 55 /* Card Address bit 26 */
1254#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
1255#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
1256#define GPIO58_LDD_0 58 /* LCD data pin 0 */
1257#define GPIO59_LDD_1 59 /* LCD data pin 1 */
1258#define GPIO60_LDD_2 60 /* LCD data pin 2 */
1259#define GPIO61_LDD_3 61 /* LCD data pin 3 */
1260#define GPIO62_LDD_4 62 /* LCD data pin 4 */
1261#define GPIO63_LDD_5 63 /* LCD data pin 5 */
1262#define GPIO64_LDD_6 64 /* LCD data pin 6 */
1263#define GPIO65_LDD_7 65 /* LCD data pin 7 */
1264#define GPIO66_LDD_8 66 /* LCD data pin 8 */
1265#define GPIO66_MBREQ 66 /* alternate bus master req */
1266#define GPIO67_LDD_9 67 /* LCD data pin 9 */
1267#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
1268#define GPIO68_LDD_10 68 /* LCD data pin 10 */
1269#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
1270#define GPIO69_LDD_11 69 /* LCD data pin 11 */
1271#define GPIO69_MMCCLK 69 /* MMC_CLK */
1272#define GPIO70_LDD_12 70 /* LCD data pin 12 */
1273#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
1274#define GPIO71_LDD_13 71 /* LCD data pin 13 */
1275#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
1276#define GPIO72_LDD_14 72 /* LCD data pin 14 */
1277#define GPIO72_32kHz 72 /* 32 kHz clock */
1278#define GPIO73_LDD_15 73 /* LCD data pin 15 */
1279#define GPIO73_MBGNT 73 /* Memory controller grant */
1280#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
1281#define GPIO75_LCD_LCLK 75 /* LCD line clock */
1282#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
1283#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
1284#define GPIO78_nCS_2 78 /* chip select 2 */
1285#define GPIO79_nCS_3 79 /* chip select 3 */
1286#define GPIO80_nCS_4 80 /* chip select 4 */
1287#define GPIO81_NSCLK 81 /* NSSP clock */
1288#define GPIO82_NSFRM 82 /* NSSP Frame */
1289#define GPIO83_NSTXD 83 /* NSSP transmit */
1290#define GPIO84_NSRXD 84 /* NSSP receive */
1291#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
1292#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
1293#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
1294#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
1295#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
1296#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
1297#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
1298#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
1299#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
1300
1301/* GPIO alternate function mode & direction */
1302
1303#define GPIO_IN 0x000
1304#define GPIO_OUT 0x080
1305#define GPIO_ALT_FN_1_IN 0x100
1306#define GPIO_ALT_FN_1_OUT 0x180
1307#define GPIO_ALT_FN_2_IN 0x200
1308#define GPIO_ALT_FN_2_OUT 0x280
1309#define GPIO_ALT_FN_3_IN 0x300
1310#define GPIO_ALT_FN_3_OUT 0x380
1311#define GPIO_MD_MASK_NR 0x07f
1312#define GPIO_MD_MASK_DIR 0x080
1313#define GPIO_MD_MASK_FN 0x300
1314#define GPIO_DFLT_LOW 0x400
1315#define GPIO_DFLT_HIGH 0x800
1316
1317#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
1318#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
1319#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)
1320#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
1321#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
1322#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
1323#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
1324#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
1325#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
1326#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
1327#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
1328#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
1329#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
1330#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
1331#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
1332#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
1333#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
1334#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
1335#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
1336#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
1337#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
1338#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
1339#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
1340#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
1341#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
1342#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
1343#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
1344#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
1345#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
1346#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
1347#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
1348#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)
1349#define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT)
1350#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
1351#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
1352#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
1353#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
1354#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
1355#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
1356#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
1357#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
1358#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
1359#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
1360#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
1361#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
1362#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
1363#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
1364#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
1365#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
1366#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
1367#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
1368#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
1369#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
1370#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
1371#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
1372#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
1373#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
1374#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
1375#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
1376#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
1377#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
1378#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
1379#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
1380#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
1381#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
1382#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
1383#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
1384#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
1385#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
1386#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
1387#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
1388#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
1389#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
1390#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
1391#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
1392#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
1393#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
1394#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
1395#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
1396#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
1397#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
1398#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
1399#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
1400#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
1401#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
1402#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
1403#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
1404#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
1405#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
1406#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
1407#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
1408#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
1409#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
1410#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
1411#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
1412#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
1413#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)
1414#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
1415#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)
1416#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)
1417#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)
1418#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)
1419#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
1420#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
1421#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
1422#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
1423#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
1424#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
1425#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
1426#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
1427#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
1428#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
1429#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
1430#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
1431#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
1432#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_OUT)
1433#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
1434
1435/*
1436 * Power Manager
1437 */
1438
1439#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
1440#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
1441#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
1442#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
1443#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
1444#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
1445#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
1446#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
1447#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
1448#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
1449#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
1450#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
1451#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
1452
1453#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
1454#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
1455#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
1456#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
1457#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
1458#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
1459#define PCMD(x) __REG2(0x40F00080, (x)<<2)
1460#define PCMD0 __REG(0x40F00080 + 0 * 4)
1461#define PCMD1 __REG(0x40F00080 + 1 * 4)
1462#define PCMD2 __REG(0x40F00080 + 2 * 4)
1463#define PCMD3 __REG(0x40F00080 + 3 * 4)
1464#define PCMD4 __REG(0x40F00080 + 4 * 4)
1465#define PCMD5 __REG(0x40F00080 + 5 * 4)
1466#define PCMD6 __REG(0x40F00080 + 6 * 4)
1467#define PCMD7 __REG(0x40F00080 + 7 * 4)
1468#define PCMD8 __REG(0x40F00080 + 8 * 4)
1469#define PCMD9 __REG(0x40F00080 + 9 * 4)
1470#define PCMD10 __REG(0x40F00080 + 10 * 4)
1471#define PCMD11 __REG(0x40F00080 + 11 * 4)
1472#define PCMD12 __REG(0x40F00080 + 12 * 4)
1473#define PCMD13 __REG(0x40F00080 + 13 * 4)
1474#define PCMD14 __REG(0x40F00080 + 14 * 4)
1475#define PCMD15 __REG(0x40F00080 + 15 * 4)
1476#define PCMD16 __REG(0x40F00080 + 16 * 4)
1477#define PCMD17 __REG(0x40F00080 + 17 * 4)
1478#define PCMD18 __REG(0x40F00080 + 18 * 4)
1479#define PCMD19 __REG(0x40F00080 + 19 * 4)
1480#define PCMD20 __REG(0x40F00080 + 20 * 4)
1481#define PCMD21 __REG(0x40F00080 + 21 * 4)
1482#define PCMD22 __REG(0x40F00080 + 22 * 4)
1483#define PCMD23 __REG(0x40F00080 + 23 * 4)
1484#define PCMD24 __REG(0x40F00080 + 24 * 4)
1485#define PCMD25 __REG(0x40F00080 + 25 * 4)
1486#define PCMD26 __REG(0x40F00080 + 26 * 4)
1487#define PCMD27 __REG(0x40F00080 + 27 * 4)
1488#define PCMD28 __REG(0x40F00080 + 28 * 4)
1489#define PCMD29 __REG(0x40F00080 + 29 * 4)
1490#define PCMD30 __REG(0x40F00080 + 30 * 4)
1491#define PCMD31 __REG(0x40F00080 + 31 * 4)
1492
1493#define PCMD_MBC (1<<12)
1494#define PCMD_DCE (1<<11)
1495#define PCMD_LC (1<<10)
1496/* FIXME: PCMD_SQC need be checked. */
1497#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
1498 bit 9 should be 0 all day. */
1499#define PVCR_VCSA (0x1<<14)
1500#define PVCR_CommandDelay (0xf80)
1501#define PCFR_PI2C_EN (0x1 << 6)
1502
1503#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1504#define PSSR_RDH (1 << 5) /* Read Disable Hold */
1505#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1506#define PSSR_VFS (1 << 2) /* VDD Fault Status */
1507#define PSSR_BFS (1 << 1) /* Battery Fault Status */
1508#define PSSR_SSS (1 << 0) /* Software Sleep Status */
1509
1510#define PCFR_RO (1 << 15) /* RDH Override */
1511#define PCFR_PO (1 << 14) /* PH Override */
1512#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
1513#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
1514#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
1515#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
1516#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
1517#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1518#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1519#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
1520#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
1521
1522#define RCSR_GPR (1 << 3) /* GPIO Reset */
1523#define RCSR_SMR (1 << 2) /* Sleep Mode */
1524#define RCSR_WDR (1 << 1) /* Watchdog Reset */
1525#define RCSR_HWR (1 << 0) /* Hardware Reset */
1526
1527#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
1528#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1529#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1530#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1531#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1532#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1533#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1534#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1535#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1536#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1537#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1538#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1539#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1540#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1541#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1542#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1543#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1544#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1545
1546
1547/*
1548 * SSP Serial Port Registers
1549 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
1550 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
1551 */
1552
1553 /* Common PXA2xx bits first */
1554#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
1555#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
1556#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
1557#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
1558#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
1559#define SSCR0_National (0x2 << 4) /* National Microwire */
1560#define SSCR0_ECS (1 << 6) /* External clock select */
1561#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
1562#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
1563#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
1564
1565#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
1566#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
1567#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
1568#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
1569#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
1570#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
1571#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
1572#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
1573#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
1574#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
1575
1576#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
1577#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
1578#define SSSR_BSY (1 << 4) /* SSP Busy */
1579#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
1580#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
1581#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
1582
1583#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
1584#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
1585#define SSCR0_NCS (1 << 21) /* Network Clock Select */
1586#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
1587
1588/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
1589#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
1590#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
1591#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
1592#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
1593#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
1594#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
1595#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
1596#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
1597#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
1598#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
1599#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
1600#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
1601#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
1602#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
1603#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
1604#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
1605#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
1606
1607#define SSSR_BCE (1 << 23) /* Bit Count Error */
1608#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
1609#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
1610#define SSSR_EOC (1 << 20) /* End Of Chain */
1611#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
1612#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
1613
1614#define SSPSP_DMYSTOP(x) (x << 23) /* Dummy Stop */
1615#define SSPSP_SFRMWDTH(x) (x << 16) /* Serial Frame Width */
1616#define SSPSP_SFRMDLY(x) (x << 9) /* Serial Frame Delay */
1617#define SSPSP_DMYSTRT(x) (x << 7) /* Dummy Start */
1618#define SSPSP_STRTDLY(x) (x << 4) /* Start Delay */
1619#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
1620#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
1621#define SSPSP_SCMODE(x) (x << 0) /* Serial Bit Rate Clock Mode */
1622
1623
1624#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
1625#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
1626#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
1627#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
1628#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
1629
1630/* Support existing PXA25x drivers */
1631#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
1632#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
1633#define SSSR SSSR_P1 /* SSP Status Register */
1634#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
1635#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
1636
1637/* PXA27x ports */
1638#if defined (CONFIG_PXA27x)
1639#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1640#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1641#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
1642#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
1643#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
1644#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
1645#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1646#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
1647#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
1648#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
1649#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
1650#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
1651#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
1652#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1653#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
1654#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
1655#else /* PXA255 (only port 2) and PXA26x ports*/
1656#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1657#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1658#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
1659#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
1660#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
1661#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
1662#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1663#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
1664#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
1665#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
1666#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
1667#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
1668#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
1669#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1670#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
1671#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
1672#endif
1673
1674#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
1675#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
1676#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
1677#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
1678#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
1679#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
1680#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
1681
1682/*
1683 * MultiMediaCard (MMC) controller
1684 */
1685
1686#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
1687#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
1688#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
1689#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
1690#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
1691#define MMC_RESTO __REG(0x41100014) /* Expected response time out */
1692#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
1693#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
1694#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
1695#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
1696#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
1697#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
1698#define MMC_CMD __REG(0x41100030) /* Index of current command */
1699#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
1700#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
1701#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
1702#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
1703#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
1704
1705
1706/*
1707 * Core Clock
1708 */
1709
1710#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
1711#define CKEN __REG(0x41300004) /* Clock Enable Register */
1712#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
1713#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
1714
1715#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1716#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1717#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1718
1719#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
1720#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
1721#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
1722#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
1723#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
1724#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
1725#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
1726#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
1727#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
1728#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
1729#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
1730#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
1731#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
1732#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
1733#define CKEN10_ASSP (1 << 10) /* ASSP (SSP3) Clock Enable */
1734#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
1735#define CKEN9_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */
1736#define CKEN9_NSSP (1 << 9) /* NSSP (SSP2) Clock Enable */
1737#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
1738#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
1739#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
1740#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
1741#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
1742#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
1743#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
1744#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
1745#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
1746#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
1747
1748#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1749#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1750
1751
1752/*
1753 * LCD
1754 */
1755
1756#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
1757#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
1758#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
1759#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
1760#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
1761#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
1762#define LCSR __REG(0x44000038) /* LCD Controller Status Register */
1763#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
1764#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
1765#define TMEDCR __REG(0x44000044) /* TMED Control Register */
1766
1767#define LCCR3_1BPP (0 << 24)
1768#define LCCR3_2BPP (1 << 24)
1769#define LCCR3_4BPP (2 << 24)
1770#define LCCR3_8BPP (3 << 24)
1771#define LCCR3_16BPP (4 << 24)
1772
1773#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
1774#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
1775#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
1776#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
1777#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
1778#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
1779#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
1780#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
1781
1782#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
1783#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
1784#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
1785#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
1786#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display */
1787 /* Select */
1788#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
1789#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
1790
1791#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
1792#define LCCR0_SFM (1 << 4) /* Start of frame mask */
1793#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
1794#define LCCR0_EFM (1 << 6) /* End of Frame mask */
1795#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
1796#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
1797#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
1798#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome */
1799 /* display mode) */
1800#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
1801 /* display */
1802#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
1803 /* display */
1804#define LCCR0_DIS (1 << 10) /* LCD Disable */
1805#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
1806#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
1807#define LCCR0_PDD_S 12
1808#define LCCR0_BM (1 << 20) /* Branch mask */
1809#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
1810
1811#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
1812#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
1813 (((Pixel) - 1) << FShft (LCCR1_PPL))
1814
1815#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
1816#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
1817 /* pulse Width [1..64 Tpix] */ \
1818 (((Tpix) - 1) << FShft (LCCR1_HSW))
1819
1820#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
1821 /* count - 1 [Tpix] */
1822#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
1823 /* [1..256 Tpix] */ \
1824 (((Tpix) - 1) << FShft (LCCR1_ELW))
1825
1826#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
1827 /* Wait count - 1 [Tpix] */
1828#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
1829 /* [1..256 Tpix] */ \
1830 (((Tpix) - 1) << FShft (LCCR1_BLW))
1831
1832
1833#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1834#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
1835 (((Line) - 1) << FShft (LCCR2_LPP))
1836
1837#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
1838 /* Width - 1 [Tln] (L_FCLK) */
1839#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
1840 /* Width [1..64 Tln] */ \
1841 (((Tln) - 1) << FShft (LCCR2_VSW))
1842
1843#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
1844 /* count [Tln] */
1845#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
1846 /* [0..255 Tln] */ \
1847 ((Tln) << FShft (LCCR2_EFW))
1848
1849#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
1850 /* Wait count [Tln] */
1851#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
1852 /* [0..255 Tln] */ \
1853 ((Tln) << FShft (LCCR2_BFW))
1854
1855#if 0
1856#define LCCR3_PCD (0xff) /* Pixel clock divisor */
1857#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
1858#define LCCR3_ACB_S 8
1859#endif
1860
1861#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
1862#define LCCR3_API_S 16
1863#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
1864#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
1865#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
1866#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
1867#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
1868
1869#define LCCR3_OEP (1 << 23) /* Output Enable Polarity (L_BIAS, */
1870 /* active display mode) */
1871#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
1872#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
1873
1874#if 0
1875#define LCCR3_BPP (7 << 24) /* bits per pixel */
1876#define LCCR3_BPP_S 24
1877#endif
1878#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
1879
1880
1881#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
1882#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
1883 (((Div) << FShft (LCCR3_PCD)))
1884
1885
1886#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
1887#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
1888 (((Bpp) << FShft (LCCR3_BPP)))
1889
1890#define LCCR3_ACB Fld (8, 8) /* AC Bias */
1891#define LCCR3_Acb(Acb) /* BAC Bias */ \
1892 (((Acb) << FShft (LCCR3_ACB)))
1893
1894#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
1895 /* pulse active High */
1896#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
1897
1898#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
1899 /* active High */
1900#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
1901 /* active Low */
1902
1903#define LCSR_LDD (1 << 0) /* LCD Disable Done */
1904#define LCSR_SOF (1 << 1) /* Start of frame */
1905#define LCSR_BER (1 << 2) /* Bus error */
1906#define LCSR_ABC (1 << 3) /* AC Bias count */
1907#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
1908#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
1909#define LCSR_OU (1 << 6) /* output FIFO underrun */
1910#define LCSR_QD (1 << 7) /* quick disable */
1911#define LCSR_EOF (1 << 8) /* end of frame */
1912#define LCSR_BS (1 << 9) /* branch status */
1913#define LCSR_SINT (1 << 10) /* subsequent interrupt */
1914
1915#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1916
1917#define LCSR_LDD (1 << 0) /* LCD Disable Done */
1918#define LCSR_SOF (1 << 1) /* Start of frame */
1919#define LCSR_BER (1 << 2) /* Bus error */
1920#define LCSR_ABC (1 << 3) /* AC Bias count */
1921#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
1922#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
1923#define LCSR_OU (1 << 6) /* output FIFO underrun */
1924#define LCSR_QD (1 << 7) /* quick disable */
1925#define LCSR_EOF (1 << 8) /* end of frame */
1926#define LCSR_BS (1 << 9) /* branch status */
1927#define LCSR_SINT (1 << 10) /* subsequent interrupt */
1928
1929#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1930
1931/*
1932 * Memory controller
1933 */
1934
1935#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
1936#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
1937#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
1938#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
1939#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
1940#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
1941#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
1942#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
1943#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
1944#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
1945#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
1946#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
1947#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
1948#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
1949#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
1950#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
1951#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
1952
1953/*
1954 * More handy macros for PCMCIA
1955 *
1956 * Arg is socket number
1957 */
1958#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
1959#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
1960#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
1961
1962/* MECR register defines */
1963#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
1964#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
1965
1966#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
1967#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
1968#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
1969#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
1970#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
1971#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
1972#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
1973#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
1974#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
1975#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
1976#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
1977#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
1978#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
1979
1980
1981#ifdef CONFIG_PXA27x
1982
1983/*
1984 * Keypad
1985 */
1986#define KPC __REG(0x41500000) /* Keypad Interface Control register */
1987#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
1988#define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
1989#define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */
1990#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
1991#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
1992#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
1993#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
1994#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
1995#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
1996
1997#define KPC_AS (0x1 << 30) /* Automatic Scan bit */
1998#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
1999#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
2000#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
2001#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
2002#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
2003#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
2004#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
2005#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
2006#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
2007#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
2008#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
2009#define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
2010#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
2011#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
2012#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */
2013#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
2014#define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */
2015#define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */
2016#define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */
2017#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
2018#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
2019
2020#define KPDK_DKP (0x1 << 31)
2021#define KPDK_DK7 (0x1 << 7)
2022#define KPDK_DK6 (0x1 << 6)
2023#define KPDK_DK5 (0x1 << 5)
2024#define KPDK_DK4 (0x1 << 4)
2025#define KPDK_DK3 (0x1 << 3)
2026#define KPDK_DK2 (0x1 << 2)
2027#define KPDK_DK1 (0x1 << 1)
2028#define KPDK_DK0 (0x1 << 0)
2029
2030#define KPREC_OF1 (0x1 << 31)
2031#define kPREC_UF1 (0x1 << 30)
2032#define KPREC_OF0 (0x1 << 15)
2033#define KPREC_UF0 (0x1 << 14)
2034
2035#define KPMK_MKP (0x1 << 31)
2036#define KPAS_SO (0x1 << 31)
2037#define KPASMKPx_SO (0x1 << 31)
2038
2039/*
2040 * UHC: USB Host Controller (OHCI-like) register definitions
2041 */
2042#define UHC_BASE_PHYS (0x4C000000)
2043#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
2044#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
2045#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
2046#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
2047#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
2048#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
2049#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
2050#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
2051#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
2052#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
2053#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
2054#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
2055#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
2056#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
2057#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
2058#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2059#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2060#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2061#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2062#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2063#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2064#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
2065#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
2066#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
2067
2068#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
2069#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
2070#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
2071#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
2072#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
2073#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
2074#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
2075#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
2076#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
2077#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
2078
2079#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
2080#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
2081#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
2082#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
2083#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
2084#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
2085#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
2086#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
2087#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
2088#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
2089#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
2090#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
2091
2092#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
2093#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
2094#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
2095#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
2096#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
2097#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
2098 Interrupt Enable*/
2099#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
2100#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
2101
2102#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
2103
2104/* Camera Interface */
2105#define CICR0 __REG(0x50000000)
2106#define CICR1 __REG(0x50000004)
2107#define CICR2 __REG(0x50000008)
2108#define CICR3 __REG(0x5000000C)
2109#define CICR4 __REG(0x50000010)
2110#define CISR __REG(0x50000014)
2111#define CIFR __REG(0x50000018)
2112#define CITOR __REG(0x5000001C)
2113#define CIBR0 __REG(0x50000028)
2114#define CIBR1 __REG(0x50000030)
2115#define CIBR2 __REG(0x50000038)
2116
2117#define CICR0_DMAEN (1 << 31) /* DMA request enable */
2118#define CICR0_PAR_EN (1 << 30) /* Parity enable */
2119#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
2120#define CICR0_ENB (1 << 28) /* Camera interface enable */
2121#define CICR0_DIS (1 << 27) /* Camera interface disable */
2122#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
2123#define CICR0_TOM (1 << 9) /* Time-out mask */
2124#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
2125#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
2126#define CICR0_EOLM (1 << 6) /* End-of-line mask */
2127#define CICR0_PERRM (1 << 5) /* Parity-error mask */
2128#define CICR0_QDM (1 << 4) /* Quick-disable mask */
2129#define CICR0_CDM (1 << 3) /* Disable-done mask */
2130#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
2131#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
2132#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
2133
2134#define CICR1_TBIT (1 << 31) /* Transparency bit */
2135#define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */
2136#define CICR1_PPL (0x3f << 15) /* Pixels per line mask */
2137#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
2138#define CICR1_RGB_F (1 << 11) /* RGB format */
2139#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
2140#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
2141#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
2142#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
2143#define CICR1_DW (0x7 << 0) /* Data width mask */
2144
2145#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
2146 wait count mask */
2147#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
2148 wait count mask */
2149#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
2150#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
2151 wait count mask */
2152#define CICR2_FSW (0x7 << 0) /* Frame stabilization
2153 wait count mask */
2154
2155#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
2156 wait count mask */
2157#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
2158 wait count mask */
2159#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
2160#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
2161 wait count mask */
2162#define CICR3_LPF (0x3ff << 0) /* Lines per frame mask */
2163
2164#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
2165#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
2166#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
2167#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
2168#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
2169#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
2170#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
2171#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
2172
2173#define CISR_FTO (1 << 15) /* FIFO time-out */
2174#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
2175#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
2176#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
2177#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
2178#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
2179#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
2180#define CISR_EOL (1 << 8) /* End of line */
2181#define CISR_PAR_ERR (1 << 7) /* Parity error */
2182#define CISR_CQD (1 << 6) /* Camera interface quick disable */
2183#define CISR_SOF (1 << 5) /* Start of frame */
2184#define CISR_CDD (1 << 4) /* Camera interface disable done */
2185#define CISR_EOF (1 << 3) /* End of frame */
2186#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
2187#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
2188#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
2189
2190#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
2191#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
2192#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
2193#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
2194#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
2195#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
2196#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
2197#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
2198
2199#define SRAM_SIZE 0x40000 /* 4x64K */
2200
2201#define SRAM_MEM_PHYS 0x5C000000
2202
2203#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
2204#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
2205
2206#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
2207#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
2208#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
2209#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
2210
2211#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
2212#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
2213#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
2214#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
2215
2216#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
2217#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
2218#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
2219#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
2220
2221#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
2222#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
2223#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
2224#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
2225
2226#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
2227#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
2228#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
2229#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
2230
2231#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
2232
2233#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
2234#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
2235#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
2236
2237#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
2238#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
2239#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
2240
2241#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
2242#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
2243#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
2244
2245#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
2246#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
2247#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
2248
2249#endif
2250
2251#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 17:44:13 -0500