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-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 083e03c5639f..e24f6b6c79ae 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1626,7 +1626,7 @@
1626#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ 1626#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
1627#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ 1627#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
1628#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ 1628#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
1629#define SSCR0_SlotsPerFrm(x) ((x) - 1) /* Time slots per frame [1..8] */ 1629#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
1630#define SSCR0_ADC (1 << 30) /* Audio clock select */ 1630#define SSCR0_ADC (1 << 30) /* Audio clock select */
1631#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ 1631#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
1632#endif 1632#endif
@@ -1655,6 +1655,7 @@
1655#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */ 1655#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
1656 1656
1657/* extra bits in PXA255, PXA26x and PXA27x SSP ports */ 1657/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
1658#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
1658#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ 1659#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
1659#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ 1660#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
1660#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ 1661#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */