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-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h158
1 files changed, 2 insertions, 156 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 68d742877308..dce9308626b7 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -825,120 +825,9 @@
825#endif 825#endif
826 826
827/* 827/*
828 * Power Manager 828 * Power Manager - see pxa2xx-regs.h
829 */ 829 */
830 830
831#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
832#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
833#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
834#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
835#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
836#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
837#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
838#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
839#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
840#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
841#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
842#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
843#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
844
845#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
846#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
847#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
848#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
849#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
850#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
851#define PCMD(x) __REG2(0x40F00080, (x)<<2)
852#define PCMD0 __REG(0x40F00080 + 0 * 4)
853#define PCMD1 __REG(0x40F00080 + 1 * 4)
854#define PCMD2 __REG(0x40F00080 + 2 * 4)
855#define PCMD3 __REG(0x40F00080 + 3 * 4)
856#define PCMD4 __REG(0x40F00080 + 4 * 4)
857#define PCMD5 __REG(0x40F00080 + 5 * 4)
858#define PCMD6 __REG(0x40F00080 + 6 * 4)
859#define PCMD7 __REG(0x40F00080 + 7 * 4)
860#define PCMD8 __REG(0x40F00080 + 8 * 4)
861#define PCMD9 __REG(0x40F00080 + 9 * 4)
862#define PCMD10 __REG(0x40F00080 + 10 * 4)
863#define PCMD11 __REG(0x40F00080 + 11 * 4)
864#define PCMD12 __REG(0x40F00080 + 12 * 4)
865#define PCMD13 __REG(0x40F00080 + 13 * 4)
866#define PCMD14 __REG(0x40F00080 + 14 * 4)
867#define PCMD15 __REG(0x40F00080 + 15 * 4)
868#define PCMD16 __REG(0x40F00080 + 16 * 4)
869#define PCMD17 __REG(0x40F00080 + 17 * 4)
870#define PCMD18 __REG(0x40F00080 + 18 * 4)
871#define PCMD19 __REG(0x40F00080 + 19 * 4)
872#define PCMD20 __REG(0x40F00080 + 20 * 4)
873#define PCMD21 __REG(0x40F00080 + 21 * 4)
874#define PCMD22 __REG(0x40F00080 + 22 * 4)
875#define PCMD23 __REG(0x40F00080 + 23 * 4)
876#define PCMD24 __REG(0x40F00080 + 24 * 4)
877#define PCMD25 __REG(0x40F00080 + 25 * 4)
878#define PCMD26 __REG(0x40F00080 + 26 * 4)
879#define PCMD27 __REG(0x40F00080 + 27 * 4)
880#define PCMD28 __REG(0x40F00080 + 28 * 4)
881#define PCMD29 __REG(0x40F00080 + 29 * 4)
882#define PCMD30 __REG(0x40F00080 + 30 * 4)
883#define PCMD31 __REG(0x40F00080 + 31 * 4)
884
885#define PCMD_MBC (1<<12)
886#define PCMD_DCE (1<<11)
887#define PCMD_LC (1<<10)
888/* FIXME: PCMD_SQC need be checked. */
889#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
890 bit 9 should be 0 all day. */
891#define PVCR_VCSA (0x1<<14)
892#define PVCR_CommandDelay (0xf80)
893#define PCFR_PI2C_EN (0x1 << 6)
894
895#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
896#define PSSR_RDH (1 << 5) /* Read Disable Hold */
897#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
898#define PSSR_STS (1 << 3) /* Standby Mode Status */
899#define PSSR_VFS (1 << 2) /* VDD Fault Status */
900#define PSSR_BFS (1 << 1) /* Battery Fault Status */
901#define PSSR_SSS (1 << 0) /* Software Sleep Status */
902
903#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
904
905#define PCFR_RO (1 << 15) /* RDH Override */
906#define PCFR_PO (1 << 14) /* PH Override */
907#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
908#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
909#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
910#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
911#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
912#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
913#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
914#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
915#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
916#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
917
918#define RCSR_GPR (1 << 3) /* GPIO Reset */
919#define RCSR_SMR (1 << 2) /* Sleep Mode */
920#define RCSR_WDR (1 << 1) /* Watchdog Reset */
921#define RCSR_HWR (1 << 0) /* Hardware Reset */
922
923#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
924#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
925#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
926#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
927#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
928#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
929#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
930#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
931#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
932#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
933#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
934#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
935#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
936#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
937#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
938#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
939#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
940#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
941
942/* 831/*
943 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h 832 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
944 */ 833 */
@@ -948,52 +837,9 @@
948 */ 837 */
949 838
950/* 839/*
951 * Core Clock 840 * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
952 */ 841 */
953 842
954#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
955#define CKEN __REG(0x41300004) /* Clock Enable Register */
956#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
957#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
958
959#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
960#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
961#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
962
963#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
964#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
965#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
966#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
967#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
968#define CKEN_IM (20) /* Internal Memory Clock Enable */
969#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
970#define CKEN_USIM (18) /* USIM Unit Clock Enable */
971#define CKEN_MSL (17) /* MSL Unit Clock Enable */
972#define CKEN_LCD (16) /* LCD Unit Clock Enable */
973#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
974#define CKEN_I2C (14) /* I2C Unit Clock Enable */
975#define CKEN_FICP (13) /* FICP Unit Clock Enable */
976#define CKEN_MMC (12) /* MMC Unit Clock Enable */
977#define CKEN_USB (11) /* USB Unit Clock Enable */
978#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
979#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
980#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
981#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
982#define CKEN_I2S (8) /* I2S Unit Clock Enable */
983#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
984#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
985#define CKEN_STUART (5) /* STUART Unit Clock Enable */
986#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
987#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
988#define CKEN_SSP (3) /* SSP Unit Clock Enable */
989#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
990#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
991#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
992#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
993
994#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
995#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
996
997#ifdef CONFIG_PXA27x 843#ifdef CONFIG_PXA27x
998 844
999/* Camera Interface */ 845/* Camera Interface */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 14:32:39 -0500