1 files changed, 11 insertions, 11 deletions

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index f5cc65dd7d0d..083e03c5639f 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -99,7 +99,7 @@
 #define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
 #define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
 #define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
-#define DCSR_ENRINTR    (1 << 9)        /* The end of Receive */
+#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
 #endif
 #define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
 #define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
@@ -803,12 +803,11 @@
 #define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
 #define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCISR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
-#define UDCISR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
-#define UDCISR1_IERU    (1 << 29)       /* IntEn - Resume */
-#define UDCISR1_IESU    (1 << 28)       /* IntEn - Suspend */
-#define UDCISR1_IERS    (1 << 27)       /* IntEn - Reset */
-
+#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
+#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
+#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
+#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
+#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
 
 #define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
 #define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
@@ -1681,6 +1680,7 @@
 #define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
 #define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
 
+#define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
 #define SSPSP_DMYSTOP(x)        (x << 23)       /* Dummy Stop */
 #define SSPSP_SFRMWDTH(x)       (x << 16)       /* Serial Frame Width */
 #define SSPSP_SFRMDLY(x)        (x << 9)        /* Serial Frame Delay */
@@ -2241,7 +2241,7 @@
 
 #define CICR1_TBIT      (1 << 31)       /* Transparency bit */
 #define CICR1_RGBT_CONV (0x3 << 30)     /* RGBT conversion mask */
-#define CICR1_PPL       (0x3f << 15)    /* Pixels per line mask */
+#define CICR1_PPL       (0x7ff << 15)   /* Pixels per line mask */
 #define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
 #define CICR1_RGB_F     (1 << 11)       /* RGB format */
 #define CICR1_YCBCR_F   (1 << 10)       /* YCbCr format */
@@ -2267,7 +2267,7 @@
 #define CICR3_VSW       (0x3f << 10)    /* Vertical sync pulse width mask */
 #define CICR3_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
                                            wait count mask */
-#define CICR3_LPF       (0x3ff << 0)    /* Lines per frame mask */
+#define CICR3_LPF       (0x7ff << 0)    /* Lines per frame mask */
 
 #define CICR4_MCLK_DLY  (0x3 << 24)     /* MCLK Data Capture Delay mask */
 #define CICR4_PCLK_EN   (1 << 23)       /* Pixel clock enable */
@@ -2288,8 +2288,8 @@
 #define CISR_EOL        (1 << 8)        /* End of line */
 #define CISR_PAR_ERR    (1 << 7)        /* Parity error */
 #define CISR_CQD        (1 << 6)        /* Camera interface quick disable */
-#define CISR_SOF        (1 << 5)        /* Start of frame */
-#define CISR_CDD        (1 << 4)        /* Camera interface disable done */
+#define CISR_CDD        (1 << 5)        /* Camera interface disable done */
+#define CISR_SOF        (1 << 4)        /* Start of frame */
 #define CISR_EOF        (1 << 3)        /* End of frame */
 #define CISR_IFO_2      (1 << 2)        /* FIFO overrun for Channel 2 */
 #define CISR_IFO_1      (1 << 1)        /* FIFO overrun for Channel 1 */