diff options
Diffstat (limited to 'include/asm-arm/arch-pxa/pxa-regs.h')
| -rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 330 |
1 files changed, 6 insertions, 324 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 2357a73340d4..a322012f16ac 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
| @@ -1129,6 +1129,11 @@ | |||
| 1129 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | 1129 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ |
| 1130 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | 1130 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ |
| 1131 | 1131 | ||
| 1132 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
| 1133 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
| 1134 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
| 1135 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
| 1136 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
| 1132 | 1137 | ||
| 1133 | /* | 1138 | /* |
| 1134 | * General Purpose I/O | 1139 | * General Purpose I/O |
| @@ -1200,12 +1205,6 @@ | |||
| 1200 | 1205 | ||
| 1201 | /* Interrupt Controller */ | 1206 | /* Interrupt Controller */ |
| 1202 | 1207 | ||
| 1203 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
| 1204 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
| 1205 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
| 1206 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
| 1207 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
| 1208 | |||
| 1209 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | 1208 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) |
| 1210 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | 1209 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) |
| 1211 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | 1210 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) |
| @@ -1237,267 +1236,6 @@ | |||
| 1237 | 1236 | ||
| 1238 | #endif | 1237 | #endif |
| 1239 | 1238 | ||
| 1240 | |||
| 1241 | /* GPIO alternate function assignments */ | ||
| 1242 | |||
| 1243 | #define GPIO1_RST 1 /* reset */ | ||
| 1244 | #define GPIO6_MMCCLK 6 /* MMC Clock */ | ||
| 1245 | #define GPIO7_48MHz 7 /* 48 MHz clock output */ | ||
| 1246 | #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ | ||
| 1247 | #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ | ||
| 1248 | #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ | ||
| 1249 | #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ | ||
| 1250 | #define GPIO12_32KHz 12 /* 32 kHz out */ | ||
| 1251 | #define GPIO13_MBGNT 13 /* memory controller grant */ | ||
| 1252 | #define GPIO14_MBREQ 14 /* alternate bus master request */ | ||
| 1253 | #define GPIO15_nCS_1 15 /* chip select 1 */ | ||
| 1254 | #define GPIO16_PWM0 16 /* PWM0 output */ | ||
| 1255 | #define GPIO17_PWM1 17 /* PWM1 output */ | ||
| 1256 | #define GPIO18_RDY 18 /* Ext. Bus Ready */ | ||
| 1257 | #define GPIO19_DREQ1 19 /* External DMA Request */ | ||
| 1258 | #define GPIO20_DREQ0 20 /* External DMA Request */ | ||
| 1259 | #define GPIO23_SCLK 23 /* SSP clock */ | ||
| 1260 | #define GPIO24_SFRM 24 /* SSP Frame */ | ||
| 1261 | #define GPIO25_STXD 25 /* SSP transmit */ | ||
| 1262 | #define GPIO26_SRXD 26 /* SSP receive */ | ||
| 1263 | #define GPIO27_SEXTCLK 27 /* SSP ext_clk */ | ||
| 1264 | #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ | ||
| 1265 | #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ | ||
| 1266 | #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ | ||
| 1267 | #define GPIO31_SYNC 31 /* AC97/I2S sync */ | ||
| 1268 | #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ | ||
| 1269 | #define GPIO32_SYSCLK 32 /* I2S System Clock */ | ||
| 1270 | #define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ | ||
| 1271 | #define GPIO33_nCS_5 33 /* chip select 5 */ | ||
| 1272 | #define GPIO34_FFRXD 34 /* FFUART receive */ | ||
| 1273 | #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ | ||
| 1274 | #define GPIO35_FFCTS 35 /* FFUART Clear to send */ | ||
| 1275 | #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ | ||
| 1276 | #define GPIO37_FFDSR 37 /* FFUART data set ready */ | ||
| 1277 | #define GPIO38_FFRI 38 /* FFUART Ring Indicator */ | ||
| 1278 | #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ | ||
| 1279 | #define GPIO39_FFTXD 39 /* FFUART transmit data */ | ||
| 1280 | #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ | ||
| 1281 | #define GPIO41_FFRTS 41 /* FFUART request to send */ | ||
| 1282 | #define GPIO42_BTRXD 42 /* BTUART receive data */ | ||
| 1283 | #define GPIO42_HWRXD 42 /* HWUART receive data */ | ||
| 1284 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ | ||
| 1285 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ | ||
| 1286 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ | ||
| 1287 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ | ||
| 1288 | #define GPIO45_BTRTS 45 /* BTUART request to send */ | ||
| 1289 | #define GPIO45_HWRTS 45 /* HWUART request to send */ | ||
| 1290 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ | ||
| 1291 | #define GPIO46_ICPRXD 46 /* ICP receive data */ | ||
| 1292 | #define GPIO46_STRXD 46 /* STD_UART receive data */ | ||
| 1293 | #define GPIO47_ICPTXD 47 /* ICP transmit data */ | ||
| 1294 | #define GPIO47_STTXD 47 /* STD_UART transmit data */ | ||
| 1295 | #define GPIO48_nPOE 48 /* Output Enable for Card Space */ | ||
| 1296 | #define GPIO49_nPWE 49 /* Write Enable for Card Space */ | ||
| 1297 | #define GPIO50_nPIOR 50 /* I/O Read for Card Space */ | ||
| 1298 | #define GPIO51_nPIOW 51 /* I/O Write for Card Space */ | ||
| 1299 | #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ | ||
| 1300 | #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ | ||
| 1301 | #define GPIO53_MMCCLK 53 /* MMC Clock */ | ||
| 1302 | #define GPIO54_MMCCLK 54 /* MMC Clock */ | ||
| 1303 | #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ | ||
| 1304 | #define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ | ||
| 1305 | #define GPIO55_nPREG 55 /* Card Address bit 26 */ | ||
| 1306 | #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ | ||
| 1307 | #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ | ||
| 1308 | #define GPIO58_LDD_0 58 /* LCD data pin 0 */ | ||
| 1309 | #define GPIO59_LDD_1 59 /* LCD data pin 1 */ | ||
| 1310 | #define GPIO60_LDD_2 60 /* LCD data pin 2 */ | ||
| 1311 | #define GPIO61_LDD_3 61 /* LCD data pin 3 */ | ||
| 1312 | #define GPIO62_LDD_4 62 /* LCD data pin 4 */ | ||
| 1313 | #define GPIO63_LDD_5 63 /* LCD data pin 5 */ | ||
| 1314 | #define GPIO64_LDD_6 64 /* LCD data pin 6 */ | ||
| 1315 | #define GPIO65_LDD_7 65 /* LCD data pin 7 */ | ||
| 1316 | #define GPIO66_LDD_8 66 /* LCD data pin 8 */ | ||
| 1317 | #define GPIO66_MBREQ 66 /* alternate bus master req */ | ||
| 1318 | #define GPIO67_LDD_9 67 /* LCD data pin 9 */ | ||
| 1319 | #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ | ||
| 1320 | #define GPIO68_LDD_10 68 /* LCD data pin 10 */ | ||
| 1321 | #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ | ||
| 1322 | #define GPIO69_LDD_11 69 /* LCD data pin 11 */ | ||
| 1323 | #define GPIO69_MMCCLK 69 /* MMC_CLK */ | ||
| 1324 | #define GPIO70_LDD_12 70 /* LCD data pin 12 */ | ||
| 1325 | #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ | ||
| 1326 | #define GPIO71_LDD_13 71 /* LCD data pin 13 */ | ||
| 1327 | #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ | ||
| 1328 | #define GPIO72_LDD_14 72 /* LCD data pin 14 */ | ||
| 1329 | #define GPIO72_32kHz 72 /* 32 kHz clock */ | ||
| 1330 | #define GPIO73_LDD_15 73 /* LCD data pin 15 */ | ||
| 1331 | #define GPIO73_MBGNT 73 /* Memory controller grant */ | ||
| 1332 | #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ | ||
| 1333 | #define GPIO75_LCD_LCLK 75 /* LCD line clock */ | ||
| 1334 | #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ | ||
| 1335 | #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ | ||
| 1336 | #define GPIO78_nCS_2 78 /* chip select 2 */ | ||
| 1337 | #define GPIO79_nCS_3 79 /* chip select 3 */ | ||
| 1338 | #define GPIO80_nCS_4 80 /* chip select 4 */ | ||
| 1339 | #define GPIO81_NSCLK 81 /* NSSP clock */ | ||
| 1340 | #define GPIO82_NSFRM 82 /* NSSP Frame */ | ||
| 1341 | #define GPIO83_NSTXD 83 /* NSSP transmit */ | ||
| 1342 | #define GPIO84_NSRXD 84 /* NSSP receive */ | ||
| 1343 | #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ | ||
| 1344 | #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ | ||
| 1345 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ | ||
| 1346 | #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ | ||
| 1347 | #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ | ||
| 1348 | #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ | ||
| 1349 | #define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */ | ||
| 1350 | #define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */ | ||
| 1351 | #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ | ||
| 1352 | #define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ | ||
| 1353 | #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ | ||
| 1354 | |||
| 1355 | /* GPIO alternate function mode & direction */ | ||
| 1356 | |||
| 1357 | #define GPIO_IN 0x000 | ||
| 1358 | #define GPIO_OUT 0x080 | ||
| 1359 | #define GPIO_ALT_FN_1_IN 0x100 | ||
| 1360 | #define GPIO_ALT_FN_1_OUT 0x180 | ||
| 1361 | #define GPIO_ALT_FN_2_IN 0x200 | ||
| 1362 | #define GPIO_ALT_FN_2_OUT 0x280 | ||
| 1363 | #define GPIO_ALT_FN_3_IN 0x300 | ||
| 1364 | #define GPIO_ALT_FN_3_OUT 0x380 | ||
| 1365 | #define GPIO_MD_MASK_NR 0x07f | ||
| 1366 | #define GPIO_MD_MASK_DIR 0x080 | ||
| 1367 | #define GPIO_MD_MASK_FN 0x300 | ||
| 1368 | #define GPIO_DFLT_LOW 0x400 | ||
| 1369 | #define GPIO_DFLT_HIGH 0x800 | ||
| 1370 | |||
| 1371 | #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) | ||
| 1372 | #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) | ||
| 1373 | #define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT) | ||
| 1374 | #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) | ||
| 1375 | #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) | ||
| 1376 | #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) | ||
| 1377 | #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) | ||
| 1378 | #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) | ||
| 1379 | #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) | ||
| 1380 | #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) | ||
| 1381 | #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) | ||
| 1382 | #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) | ||
| 1383 | #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) | ||
| 1384 | #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) | ||
| 1385 | #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) | ||
| 1386 | #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) | ||
| 1387 | #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) | ||
| 1388 | #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) | ||
| 1389 | #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) | ||
| 1390 | #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) | ||
| 1391 | #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) | ||
| 1392 | #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) | ||
| 1393 | #define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) | ||
| 1394 | #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) | ||
| 1395 | #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) | ||
| 1396 | #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) | ||
| 1397 | #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) | ||
| 1398 | #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) | ||
| 1399 | #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) | ||
| 1400 | #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) | ||
| 1401 | #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) | ||
| 1402 | #define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT) | ||
| 1403 | #define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT) | ||
| 1404 | #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) | ||
| 1405 | #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) | ||
| 1406 | #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) | ||
| 1407 | #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) | ||
| 1408 | #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) | ||
| 1409 | #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) | ||
| 1410 | #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) | ||
| 1411 | #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) | ||
| 1412 | #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) | ||
| 1413 | #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) | ||
| 1414 | #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) | ||
| 1415 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) | ||
| 1416 | #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) | ||
| 1417 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) | ||
| 1418 | #define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) | ||
| 1419 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) | ||
| 1420 | #define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) | ||
| 1421 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) | ||
| 1422 | #define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) | ||
| 1423 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) | ||
| 1424 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) | ||
| 1425 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) | ||
| 1426 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) | ||
| 1427 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) | ||
| 1428 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 1429 | #define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) | ||
| 1430 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 1431 | #define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) | ||
| 1432 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) | ||
| 1433 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) | ||
| 1434 | #define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 1435 | #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) | ||
| 1436 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) | ||
| 1437 | #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) | ||
| 1438 | #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) | ||
| 1439 | #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) | ||
| 1440 | #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) | ||
| 1441 | #define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 1442 | #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 1443 | #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) | ||
| 1444 | #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) | ||
| 1445 | #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) | ||
| 1446 | #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) | ||
| 1447 | #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) | ||
| 1448 | #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) | ||
| 1449 | #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) | ||
| 1450 | #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) | ||
| 1451 | #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) | ||
| 1452 | #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) | ||
| 1453 | #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) | ||
| 1454 | #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) | ||
| 1455 | #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) | ||
| 1456 | #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) | ||
| 1457 | #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) | ||
| 1458 | #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) | ||
| 1459 | #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) | ||
| 1460 | #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) | ||
| 1461 | #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) | ||
| 1462 | #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) | ||
| 1463 | #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) | ||
| 1464 | #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) | ||
| 1465 | #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) | ||
| 1466 | #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) | ||
| 1467 | #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) | ||
| 1468 | #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) | ||
| 1469 | #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) | ||
| 1470 | #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) | ||
| 1471 | #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) | ||
| 1472 | #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) | ||
| 1473 | #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) | ||
| 1474 | #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) | ||
| 1475 | #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) | ||
| 1476 | #define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT) | ||
| 1477 | #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) | ||
| 1478 | #define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT) | ||
| 1479 | #define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN) | ||
| 1480 | #define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT) | ||
| 1481 | #define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN) | ||
| 1482 | #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) | ||
| 1483 | #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) | ||
| 1484 | #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) | ||
| 1485 | #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) | ||
| 1486 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) | ||
| 1487 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) | ||
| 1488 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) | ||
| 1489 | #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) | ||
| 1490 | #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) | ||
| 1491 | #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 1492 | #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 1493 | #define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 1494 | #define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 1495 | #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) | ||
| 1496 | #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) | ||
| 1497 | #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) | ||
| 1498 | #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) | ||
| 1499 | #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) | ||
| 1500 | |||
| 1501 | /* | 1239 | /* |
| 1502 | * Power Manager | 1240 | * Power Manager |
| 1503 | */ | 1241 | */ |
| @@ -1866,62 +1604,6 @@ | |||
| 1866 | 1604 | ||
| 1867 | #ifdef CONFIG_PXA27x | 1605 | #ifdef CONFIG_PXA27x |
| 1868 | 1606 | ||
| 1869 | /* | ||
| 1870 | * Keypad | ||
| 1871 | */ | ||
| 1872 | #define KPC __REG(0x41500000) /* Keypad Interface Control register */ | ||
| 1873 | #define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */ | ||
| 1874 | #define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */ | ||
| 1875 | #define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */ | ||
| 1876 | #define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */ | ||
| 1877 | #define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ | ||
| 1878 | #define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ | ||
| 1879 | #define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ | ||
| 1880 | #define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ | ||
| 1881 | #define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */ | ||
| 1882 | |||
| 1883 | #define KPC_AS (0x1 << 30) /* Automatic Scan bit */ | ||
| 1884 | #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ | ||
| 1885 | #define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ | ||
| 1886 | #define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ | ||
| 1887 | #define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ | ||
| 1888 | #define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ | ||
| 1889 | #define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ | ||
| 1890 | #define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ | ||
| 1891 | #define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ | ||
| 1892 | #define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ | ||
| 1893 | #define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ | ||
| 1894 | #define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ | ||
| 1895 | #define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7) | ||
| 1896 | #define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ | ||
| 1897 | #define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ | ||
| 1898 | #define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */ | ||
| 1899 | #define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ | ||
| 1900 | #define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */ | ||
| 1901 | #define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */ | ||
| 1902 | #define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */ | ||
| 1903 | #define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ | ||
| 1904 | #define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ | ||
| 1905 | |||
| 1906 | #define KPDK_DKP (0x1 << 31) | ||
| 1907 | #define KPDK_DK7 (0x1 << 7) | ||
| 1908 | #define KPDK_DK6 (0x1 << 6) | ||
| 1909 | #define KPDK_DK5 (0x1 << 5) | ||
| 1910 | #define KPDK_DK4 (0x1 << 4) | ||
| 1911 | #define KPDK_DK3 (0x1 << 3) | ||
| 1912 | #define KPDK_DK2 (0x1 << 2) | ||
| 1913 | #define KPDK_DK1 (0x1 << 1) | ||
| 1914 | #define KPDK_DK0 (0x1 << 0) | ||
| 1915 | |||
| 1916 | #define KPREC_OF1 (0x1 << 31) | ||
| 1917 | #define kPREC_UF1 (0x1 << 30) | ||
| 1918 | #define KPREC_OF0 (0x1 << 15) | ||
| 1919 | #define KPREC_UF0 (0x1 << 14) | ||
| 1920 | |||
| 1921 | #define KPMK_MKP (0x1 << 31) | ||
| 1922 | #define KPAS_SO (0x1 << 31) | ||
| 1923 | #define KPASMKPx_SO (0x1 << 31) | ||
| 1924 | |||
| 1925 | /* Camera Interface */ | 1607 | /* Camera Interface */ |
| 1926 | #define CICR0 __REG(0x50000000) | 1608 | #define CICR0 __REG(0x50000000) |
| 1927 | #define CICR1 __REG(0x50000004) | 1609 | #define CICR1 __REG(0x50000004) |
| @@ -1953,7 +1635,7 @@ | |||
| 1953 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | 1635 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ |
| 1954 | 1636 | ||
| 1955 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | 1637 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ |
| 1956 | #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */ | 1638 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ |
| 1957 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | 1639 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ |
| 1958 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | 1640 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ |
| 1959 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | 1641 | #define CICR1_RGB_F (1 << 11) /* RGB format */ |