diff options
Diffstat (limited to 'include/asm-arm/arch-pxa/pxa-regs.h')
| -rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 442494d71f12..16ed24dbda4e 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
| @@ -737,25 +737,25 @@ | |||
| 737 | 737 | ||
| 738 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ | 738 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ |
| 739 | 739 | ||
| 740 | #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ | 740 | #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ |
| 741 | #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */ | 741 | #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ |
| 742 | #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */ | 742 | #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ |
| 743 | #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ | 743 | #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ |
| 744 | #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ | 744 | #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ |
| 745 | #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ | 745 | #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ |
| 746 | #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ | 746 | #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ |
| 747 | #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ | 747 | #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ |
| 748 | 748 | ||
| 749 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ | 749 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ |
| 750 | 750 | ||
| 751 | #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ | 751 | #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ |
| 752 | #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ | 752 | #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ |
| 753 | #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ | 753 | #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ |
| 754 | #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ | 754 | #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ |
| 755 | #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ | 755 | #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ |
| 756 | #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ | 756 | #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ |
| 757 | #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ | 757 | #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ |
| 758 | #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ | 758 | #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ |
| 759 | 759 | ||
| 760 | #elif defined(CONFIG_PXA27x) | 760 | #elif defined(CONFIG_PXA27x) |
| 761 | 761 | ||
| @@ -1020,7 +1020,7 @@ | |||
| 1020 | #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ | 1020 | #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ |
| 1021 | #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ | 1021 | #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ |
| 1022 | 1022 | ||
| 1023 | #define ICCR0_AME (1 << 7) /* Adress match enable */ | 1023 | #define ICCR0_AME (1 << 7) /* Address match enable */ |
| 1024 | #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ | 1024 | #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ |
| 1025 | #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ | 1025 | #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ |
| 1026 | #define ICCR0_RXE (1 << 4) /* Receive enable */ | 1026 | #define ICCR0_RXE (1 << 4) /* Receive enable */ |