1 files changed, 12 insertions, 14 deletions

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index e24f6b6c79ae..139c9d954818 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -463,9 +463,6 @@
  * Serial Audio Controller
  */
 
-/* FIXME: This clash with SA1111 defines */
-#ifndef _ASM_ARCH_SA1111
-
 #define SACR0           __REG(0x40400000)  /* Global Control Register */
 #define SACR1           __REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
 #define SASR0           __REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
@@ -474,8 +471,8 @@
 #define SADIV           __REG(0x40400060)  /* Audio Clock Divider Register. */
 #define SADR            __REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
 
-#define SACR0_RFTH(x)   (x << 12)       /* Rx FIFO Interrupt or DMA Trigger Threshold */
-#define SACR0_TFTH(x)   (x << 8)        /* Tx FIFO Interrupt or DMA Trigger Threshold */
+#define SACR0_RFTH(x)   ((x) << 12)     /* Rx FIFO Interrupt or DMA Trigger Threshold */
+#define SACR0_TFTH(x)   ((x) << 8)      /* Tx FIFO Interrupt or DMA Trigger Threshold */
 #define SACR0_STRF      (1 << 5)        /* FIFO Select for EFWR Special Function */
 #define SACR0_EFWR      (1 << 4)        /* Enable EFWR Function  */
 #define SACR0_RST       (1 << 3)        /* FIFO, i2s Register Reset */
@@ -503,8 +500,6 @@
 #define SAIMR_RFS       (1 << 4)        /* Enable Rx FIFO Service Interrupt */
 #define SAIMR_TFS       (1 << 3)        /* Enable Tx FIFO Service Interrupt */
 
-#endif
-
 /*
  * AC97 Controller registers
  */
@@ -1481,7 +1476,7 @@
 #define GPIO112_MMCCMD_MD       (112 | GPIO_ALT_FN_1_OUT)
 #define GPIO113_I2S_SYSCLK_MD   (113 | GPIO_ALT_FN_1_OUT)
 #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
-#define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_OUT)
+#define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_IN)
 #define GPIO118_I2CSDA_MD       (118 | GPIO_ALT_FN_1_IN)
 
 /*
@@ -1682,15 +1677,18 @@
 #define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
 
 #define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
-#define SSPSP_DMYSTOP(x)        (x << 23)       /* Dummy Stop */
-#define SSPSP_SFRMWDTH(x)       (x << 16)       /* Serial Frame Width */
-#define SSPSP_SFRMDLY(x)        (x << 9)        /* Serial Frame Delay */
-#define SSPSP_DMYSTRT(x)        (x << 7)        /* Dummy Start */
-#define SSPSP_STRTDLY(x)        (x << 4)        /* Start Delay */
+#define SSPSP_DMYSTOP(x)        ((x) << 23)     /* Dummy Stop */
+#define SSPSP_SFRMWDTH(x)       ((x) << 16)     /* Serial Frame Width */
+#define SSPSP_SFRMDLY(x)        ((x) << 9)      /* Serial Frame Delay */
+#define SSPSP_DMYSTRT(x)        ((x) << 7)      /* Dummy Start */
+#define SSPSP_STRTDLY(x)        ((x) << 4)      /* Start Delay */
 #define SSPSP_ETDS                      (1 << 3)        /* End of Transfer data State */
 #define SSPSP_SFRMP                     (1 << 2)        /* Serial Frame Polarity */
-#define SSPSP_SCMODE(x)         (x << 0)        /* Serial Bit Rate Clock Mode */
+#define SSPSP_SCMODE(x)         ((x) << 0)      /* Serial Bit Rate Clock Mode */
 
+#define SSACD_SCDB              (1 << 3)        /* SSPSYSCLK Divider Bypass */
+#define SSACD_ACPS(x)           ((x) << 4)      /* Audio clock PLL select */
+#define SSACD_ACDS(x)           ((x) << 0)      /* Audio clock divider select */
 
 #define SSCR0_P1        __REG(0x41000000)  /* SSP Port 1 Control Register 0 */
 #define SSCR1_P1        __REG(0x41000004)  /* SSP Port 1 Control Register 1 */