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-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index dae138b9cac5..1409c5bd703f 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -108,6 +108,7 @@
108#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ 108#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
109#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ 109#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
110 110
111#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
111#define DINT __REG(0x400000f0) /* DMA Interrupt Register */ 112#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
112 113
113#define DRCMR(n) __REG2(0x40000100, (n)<<2) 114#define DRCMR(n) __REG2(0x40000100, (n)<<2)
@@ -1614,8 +1615,21 @@
1614#define SSCR0_National (0x2 << 4) /* National Microwire */ 1615#define SSCR0_National (0x2 << 4) /* National Microwire */
1615#define SSCR0_ECS (1 << 6) /* External clock select */ 1616#define SSCR0_ECS (1 << 6) /* External clock select */
1616#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ 1617#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
1618#if defined(CONFIG_PXA25x)
1617#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ 1619#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
1618#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ 1620#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
1621#elif defined(CONFIG_PXA27x)
1622#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
1623#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
1624#define SSCR0_EDSS (1 << 20) /* Extended data size select */
1625#define SSCR0_NCS (1 << 21) /* Network clock select */
1626#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
1627#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
1628#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
1629#define SSCR0_SlotsPerFrm(c) ((x) - 1) /* Time slots per frame [1..8] */
1630#define SSCR0_ADC (1 << 30) /* Audio clock select */
1631#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
1632#endif
1619 1633
1620#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ 1634#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
1621#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ 1635#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */