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-rw-r--r--include/asm-arm/arch-pxa/idp.h199
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diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h
deleted file mode 100644
index 21aa8ac35c1c..000000000000
--- a/include/asm-arm/arch-pxa/idp.h
+++ /dev/null
@@ -1,199 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/idp.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
9 *
10 * 2001-09-13: Cliff Brake <cbrake@accelent.com>
11 * Initial code
12 *
13 * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
14 * <http://www.vibren.com> <http://bec-systems.com>
15 * Changes for 2.6 kernel.
16 */
17
18
19/*
20 * Note: this file must be safe to include in assembly files
21 *
22 * Support for the Vibren PXA255 IDP requires rev04 or later
23 * IDP hardware.
24 */
25
26
27#define IDP_FLASH_PHYS (PXA_CS0_PHYS)
28#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
29#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
30#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
31#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
32#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
33#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
34
35
36/*
37 * virtual memory map
38 */
39
40#define IDP_COREVOLT_VIRT (0xf0000000)
41#define IDP_COREVOLT_SIZE (1*1024*1024)
42
43#define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
44#define IDP_CPLD_SIZE (1*1024*1024)
45
46#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
47#error Your custom IO space is getting a bit large !!
48#endif
49
50#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
51#define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
52
53#ifndef __ASSEMBLY__
54# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
55#else
56# define __CPLD_REG(x) CPLD_P2V(x)
57#endif
58
59/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
60
61#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
62#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
63#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
64#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
65#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
66#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
67#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
68#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
69#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
70#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
71#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28)
72#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C)
73#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30)
74#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34)
75
76#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50)
77#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54)
78#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58)
79#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C)
80
81/* FPGA register virtual addresses */
82
83#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV)
84#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
85#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL)
86#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
87#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
88#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN)
89#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
90#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
91#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
92#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
93#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
94#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL)
95#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD)
96#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE)
97
98#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW)
99#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
100#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
101#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS)
102
103
104/*
105 * Bit masks for various registers
106 */
107
108// IDP_CPLD_PCCARD_PWR
109#define PCC0_PWR0 (1 << 0)
110#define PCC0_PWR1 (1 << 1)
111#define PCC0_PWR2 (1 << 2)
112#define PCC0_PWR3 (1 << 3)
113#define PCC1_PWR0 (1 << 4)
114#define PCC1_PWR1 (1 << 5)
115#define PCC1_PWR2 (1 << 6)
116#define PCC1_PWR3 (1 << 7)
117
118// IDP_CPLD_PCCARD_EN
119#define PCC0_RESET (1 << 6)
120#define PCC1_RESET (1 << 7)
121#define PCC0_ENABLE (1 << 0)
122#define PCC1_ENABLE (1 << 1)
123
124// IDP_CPLD_PCCARDx_STATUS
125#define _PCC_WRPROT (1 << 7) // 7-4 read as low true
126#define _PCC_RESET (1 << 6)
127#define _PCC_IRQ (1 << 5)
128#define _PCC_INPACK (1 << 4)
129#define PCC_BVD2 (1 << 3)
130#define PCC_BVD1 (1 << 2)
131#define PCC_VS2 (1 << 1)
132#define PCC_VS1 (1 << 0)
133
134#define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
135
136/* A listing of interrupts used by external hardware devices */
137
138#define TOUCH_PANEL_IRQ IRQ_GPIO(5)
139#define IDE_IRQ IRQ_GPIO(21)
140
141#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
142
143#define ETHERNET_IRQ IRQ_GPIO(4)
144#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING
145
146#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
147
148#define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
149#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
150
151#define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
152#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
153
154#define PCMCIA_S0_RDYINT IRQ_GPIO(19)
155#define PCMCIA_S1_RDYINT IRQ_GPIO(22)
156
157
158/*
159 * Macros for LED Driver
160 */
161
162/* leds 0 = ON */
163#define IDP_HB_LED (1<<5)
164#define IDP_BUSY_LED (1<<6)
165
166#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
167
168/*
169 * macros for MTD driver
170 */
171
172#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1))
173#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1))
174
175/*
176 * macros for matrix keyboard driver
177 */
178
179#define KEYBD_MATRIX_NUMBER_INPUTS 7
180#define KEYBD_MATRIX_NUMBER_OUTPUTS 14
181
182#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE
183#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE
184
185#define KEYBD_MATRIX_SETTLING_TIME_US 100
186#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2
187
188#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
189{\
190 IDP_CPLD_KB_COL_LOW = outputs;\
191 IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
192}
193
194#define KEYBD_MATRIX_GET_INPUTS(inputs) \
195{\
196 inputs = (IDP_CPLD_KB_ROW & 0x7f);\
197}
198
199
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