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-rw-r--r--include/asm-arm/arch-orion/debug-macro.S17
-rw-r--r--include/asm-arm/arch-orion/dma.h1
-rw-r--r--include/asm-arm/arch-orion/entry-macro.S31
-rw-r--r--include/asm-arm/arch-orion/gpio.h28
-rw-r--r--include/asm-arm/arch-orion/hardware.h24
-rw-r--r--include/asm-arm/arch-orion/io.h27
-rw-r--r--include/asm-arm/arch-orion/irqs.h61
-rw-r--r--include/asm-arm/arch-orion/memory.h15
-rw-r--r--include/asm-arm/arch-orion/orion.h143
-rw-r--r--include/asm-arm/arch-orion/platform.h25
-rw-r--r--include/asm-arm/arch-orion/system.h31
-rw-r--r--include/asm-arm/arch-orion/timex.h12
-rw-r--r--include/asm-arm/arch-orion/uncompress.h44
-rw-r--r--include/asm-arm/arch-orion/vmalloc.h5
14 files changed, 464 insertions, 0 deletions
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S
new file mode 100644
index 000000000000..e2a80641f214
--- /dev/null
+++ b/include/asm-arm/arch-orion/debug-macro.S
@@ -0,0 +1,17 @@
1/*
2 * linux/include/asm-arm/arch-orion/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11 .macro addruart,rx
12 mov \rx, #0xf1000000
13 orr \rx, \rx, #0x00012000
14 .endm
15
16#define UART_SHIFT 2
17#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-orion/dma.h
@@ -0,0 +1 @@
/* empty */
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S
new file mode 100644
index 000000000000..b76075a7e44b
--- /dev/null
+++ b/include/asm-arm/arch-orion/entry-macro.S
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-orion/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Orion platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/orion.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =MAIN_IRQ_CAUSE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 ldr \irqstat, [\base, #0] @ main cause
25 ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
26 mov \irqnr, #0 @ default irqnr
27 @ find cause bits that are unmasked
28 ands \irqstat, \irqstat, \tmp @ clear Z flag if any
29 clzne \irqnr, \irqstat @ calc irqnr
30 rsbne \irqnr, \irqnr, #31
31 .endm
diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion/gpio.h
new file mode 100644
index 000000000000..d66284f9a14c
--- /dev/null
+++ b/include/asm-arm/arch-orion/gpio.h
@@ -0,0 +1,28 @@
1/*
2 * include/asm-arm/arch-orion/gpio.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9extern int gpio_request(unsigned pin, const char *label);
10extern void gpio_free(unsigned pin);
11extern int gpio_direction_input(unsigned pin);
12extern int gpio_direction_output(unsigned pin, int value);
13extern int gpio_get_value(unsigned pin);
14extern void gpio_set_value(unsigned pin, int value);
15extern void orion_gpio_set_blink(unsigned pin, int blink);
16extern void gpio_display(void); /* debug */
17
18static inline int gpio_to_irq(int pin)
19{
20 return pin + IRQ_ORION_GPIO_START;
21}
22
23static inline int irq_to_gpio(int irq)
24{
25 return irq - IRQ_ORION_GPIO_START;
26}
27
28#include <asm-generic/gpio.h> /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h
new file mode 100644
index 000000000000..8a12d213fbdc
--- /dev/null
+++ b/include/asm-arm/arch-orion/hardware.h
@@ -0,0 +1,24 @@
1/*
2 * include/asm-arm/arch-orion/hardware.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __ASM_ARCH_HARDWARE_H__
11#define __ASM_ARCH_HARDWARE_H__
12
13#include "orion.h"
14
15#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
16#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
17
18#define pcibios_assign_all_busses() 1
19
20#define PCIBIOS_MIN_IO 0x1000
21#define PCIBIOS_MIN_MEM 0x01000000
22#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
23
24#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h
new file mode 100644
index 000000000000..e0b8c39b9167
--- /dev/null
+++ b/include/asm-arm/arch-orion/io.h
@@ -0,0 +1,27 @@
1/*
2 * include/asm-arm/arch-orion/io.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARM_ARCH_IO_H
12#define __ASM_ARM_ARCH_IO_H
13
14#include "orion.h"
15
16#define IO_SPACE_LIMIT 0xffffffff
17#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE
18
19static inline void __iomem *__io(unsigned long addr)
20{
21 return (void __iomem *)addr;
22}
23
24#define __io(a) __io(a)
25#define __mem_pci(a) (a)
26
27#endif
diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h
new file mode 100644
index 000000000000..eea65ca6076a
--- /dev/null
+++ b/include/asm-arm/arch-orion/irqs.h
@@ -0,0 +1,61 @@
1/*
2 * include/asm-arm/arch-orion/irqs.h
3 *
4 * IRQ definitions for Orion SoC
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __ASM_ARCH_IRQS_H__
14#define __ASM_ARCH_IRQS_H__
15
16#include "orion.h" /* need GPIO_MAX */
17
18/*
19 * Orion Main Interrupt Controller
20 */
21#define IRQ_ORION_BRIDGE 0
22#define IRQ_ORION_DOORBELL_H2C 1
23#define IRQ_ORION_DOORBELL_C2H 2
24#define IRQ_ORION_UART0 3
25#define IRQ_ORION_UART1 4
26#define IRQ_ORION_I2C 5
27#define IRQ_ORION_GPIO_0_7 6
28#define IRQ_ORION_GPIO_8_15 7
29#define IRQ_ORION_GPIO_16_23 8
30#define IRQ_ORION_GPIO_24_31 9
31#define IRQ_ORION_PCIE0_ERR 10
32#define IRQ_ORION_PCIE0_INT 11
33#define IRQ_ORION_USB1_CTRL 12
34#define IRQ_ORION_DEV_BUS_ERR 14
35#define IRQ_ORION_PCI_ERR 15
36#define IRQ_ORION_USB_BR_ERR 16
37#define IRQ_ORION_USB0_CTRL 17
38#define IRQ_ORION_ETH_RX 18
39#define IRQ_ORION_ETH_TX 19
40#define IRQ_ORION_ETH_MISC 20
41#define IRQ_ORION_ETH_SUM 21
42#define IRQ_ORION_ETH_ERR 22
43#define IRQ_ORION_IDMA_ERR 23
44#define IRQ_ORION_IDMA_0 24
45#define IRQ_ORION_IDMA_1 25
46#define IRQ_ORION_IDMA_2 26
47#define IRQ_ORION_IDMA_3 27
48#define IRQ_ORION_CESA 28
49#define IRQ_ORION_SATA 29
50#define IRQ_ORION_XOR0 30
51#define IRQ_ORION_XOR1 31
52
53/*
54 * Orion General Purpose Pins
55 */
56#define IRQ_ORION_GPIO_START 32
57#define NR_GPIO_IRQS GPIO_MAX
58
59#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
60
61#endif /* __ASM_ARCH_IRQS_H__ */
diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion/memory.h
new file mode 100644
index 000000000000..d954dba87ced
--- /dev/null
+++ b/include/asm-arm/arch-orion/memory.h
@@ -0,0 +1,15 @@
1/*
2 * include/asm-arm/arch-orion/memory.h
3 *
4 * Marvell Orion memory definitions
5 */
6
7#ifndef __ASM_ARCH_MMU_H
8#define __ASM_ARCH_MMU_H
9
10#define PHYS_OFFSET UL(0x00000000)
11
12#define __virt_to_bus(x) __virt_to_phys(x)
13#define __bus_to_virt(x) __phys_to_virt(x)
14
15#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
new file mode 100644
index 000000000000..f787f752e58c
--- /dev/null
+++ b/include/asm-arm/arch-orion/orion.h
@@ -0,0 +1,143 @@
1/*
2 * include/asm-arm/arch-orion/orion.h
3 *
4 * Generic definitions of Orion SoC flavors:
5 * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __ASM_ARCH_ORION_H__
15#define __ASM_ARCH_ORION_H__
16
17/*******************************************************************************
18 * Orion Address Map
19 * Use the same mapping (1:1 virtual:physical) of internal registers and
20 * PCI system (PCI+PCIE) for all machines.
21 * Each machine defines the rest of its mapping (e.g. device bus flashes)
22 ******************************************************************************/
23#define ORION_REGS_BASE 0xf1000000
24#define ORION_REGS_SIZE SZ_1M
25
26#define ORION_PCI_SYS_MEM_BASE 0xe0000000
27#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
28#define ORION_PCIE_MEM_SIZE SZ_128M
29#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
30#define ORION_PCI_MEM_SIZE SZ_128M
31
32#define ORION_PCI_SYS_IO_BASE 0xf2000000
33#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
34#define ORION_PCIE_IO_SIZE SZ_1M
35#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
36#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
37#define ORION_PCI_IO_SIZE SZ_1M
38#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
39/* Relevant only for Orion-NAS */
40#define ORION_PCIE_WA_BASE 0xf0000000
41#define ORION_PCIE_WA_SIZE SZ_16M
42
43/*******************************************************************************
44 * Supported Devices & Revisions
45 ******************************************************************************/
46/* Orion-1 (88F5181) */
47#define MV88F5181_DEV_ID 0x5181
48#define MV88F5181_REV_B1 3
49/* Orion-NAS (88F5182) */
50#define MV88F5182_DEV_ID 0x5182
51#define MV88F5182_REV_A2 2
52/* Orion-2 (88F5281) */
53#define MV88F5281_DEV_ID 0x5281
54#define MV88F5281_REV_D1 5
55#define MV88F5281_REV_D2 6
56
57/*******************************************************************************
58 * Orion Registers Map
59 ******************************************************************************/
60#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
61#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
62#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
63#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
64#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
65#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
66#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
67#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
68#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
69
70#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
71#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
72#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
73#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
74#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
75#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
76#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
77#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
78#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
79
80/*******************************************************************************
81 * Device Bus Registers
82 ******************************************************************************/
83#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
84#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
85#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
86#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
87#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
88#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
89#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
90#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
91#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
92#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
93#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
94#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
95#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
96#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
97#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
98#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
99#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
100#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
101#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
102#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
103#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
104#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
105#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
106#define GPIO_MAX 32
107
108/***************************************************************************
109 * Orion CPU Bridge Registers
110 **************************************************************************/
111#define CPU_CONF ORION_BRIDGE_REG(0x100)
112#define CPU_CTRL ORION_BRIDGE_REG(0x104)
113#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
114#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
115#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
116#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
117#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
118#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
119#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
120#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
121#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
122#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
123
124#ifndef __ASSEMBLY__
125
126/*******************************************************************************
127 * Helpers to access Orion registers
128 ******************************************************************************/
129#include <asm/types.h>
130#include <asm/io.h>
131
132#define orion_read(r) __raw_readl(r)
133#define orion_write(r, val) __raw_writel(val, r)
134
135/*
136 * These are not preempt safe. Locks, if needed, must be taken care by caller.
137 */
138#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask))
139#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask))
140
141#endif /* __ASSEMBLY__ */
142
143#endif /* __ASM_ARCH_ORION_H__ */
diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/arch-orion/platform.h
new file mode 100644
index 000000000000..143c38e2fa0b
--- /dev/null
+++ b/include/asm-arm/arch-orion/platform.h
@@ -0,0 +1,25 @@
1/*
2 * asm-arm/arch-orion/platform.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_PLATFORM_H__
12#define __ASM_ARCH_PLATFORM_H__
13
14/*
15 * Device bus NAND private data
16 */
17struct orion_nand_data {
18 struct mtd_partition *parts;
19 u32 nr_parts;
20 u8 ale; /* address line number connected to ALE */
21 u8 cle; /* address line number connected to CLE */
22 u8 width; /* buswidth */
23};
24
25#endif
diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion/system.h
new file mode 100644
index 000000000000..17704c68f90e
--- /dev/null
+++ b/include/asm-arm/arch-orion/system.h
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-orion/system.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H
13
14#include <asm/arch/hardware.h>
15#include <asm/arch/orion.h>
16
17static inline void arch_idle(void)
18{
19 cpu_do_idle();
20}
21
22static inline void arch_reset(char mode)
23{
24 /*
25 * Enable and issue soft reset
26 */
27 orion_setbits(CPU_RESET_MASK, (1 << 2));
28 orion_setbits(CPU_SOFT_RESET, 1);
29}
30
31#endif
diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h
new file mode 100644
index 000000000000..26c2c91eecf0
--- /dev/null
+++ b/include/asm-arm/arch-orion/timex.h
@@ -0,0 +1,12 @@
1/*
2 * include/asm-arm/arch-orion/timex.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#define ORION_TCLK 166666667
12#define CLOCK_TICK_RATE ORION_TCLK
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h
new file mode 100644
index 000000000000..a1a222fb438c
--- /dev/null
+++ b/include/asm-arm/arch-orion/uncompress.h
@@ -0,0 +1,44 @@
1/*
2 * include/asm-arm/arch-orion/uncompress.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/orion.h>
12
13#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
14#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
15
16#define LSR_THRE 0x20
17
18static void putc(const char c)
19{
20 int j = 0x1000;
21 while (--j && !(*MV_UART_LSR & LSR_THRE))
22 barrier();
23 *MV_UART_THR = c;
24}
25
26static void flush(void)
27{
28}
29
30static void orion_early_putstr(const char *ptr)
31{
32 char c;
33 while ((c = *ptr++) != '\0') {
34 if (c == '\n')
35 putc('\r');
36 putc(c);
37 }
38}
39
40/*
41 * nothing to do
42 */
43#define arch_decomp_setup()
44#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion/vmalloc.h
new file mode 100644
index 000000000000..23e2a102fe0c
--- /dev/null
+++ b/include/asm-arm/arch-orion/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-orion/vmalloc.h
3 */
4
5#define VMALLOC_END 0xf0000000
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 04:47:15 -0500