diff options
Diffstat (limited to 'include/asm-arm/arch-orion')
-rw-r--r-- | include/asm-arm/arch-orion/debug-macro.S | 9 | ||||
-rw-r--r-- | include/asm-arm/arch-orion/entry-macro.S | 4 | ||||
-rw-r--r-- | include/asm-arm/arch-orion/hardware.h | 13 | ||||
-rw-r--r-- | include/asm-arm/arch-orion/orion.h | 102 | ||||
-rw-r--r-- | include/asm-arm/arch-orion/uncompress.h | 14 | ||||
-rw-r--r-- | include/asm-arm/arch-orion/vmalloc.h | 2 |
6 files changed, 79 insertions, 65 deletions
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S index e2a80641f214..2746220f5d85 100644 --- a/include/asm-arm/arch-orion/debug-macro.S +++ b/include/asm-arm/arch-orion/debug-macro.S | |||
@@ -8,9 +8,14 @@ | |||
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <asm/arch/orion.h> | ||
12 | |||
11 | .macro addruart,rx | 13 | .macro addruart,rx |
12 | mov \rx, #0xf1000000 | 14 | mrc p15, 0, \rx, c1, c0 |
13 | orr \rx, \rx, #0x00012000 | 15 | tst \rx, #1 @ MMU enabled? |
16 | ldreq \rx, =ORION_REGS_PHYS_BASE | ||
17 | ldrne \rx, =ORION_REGS_VIRT_BASE | ||
18 | orr \rx, \rx, #0x00012000 | ||
14 | .endm | 19 | .endm |
15 | 20 | ||
16 | #define UART_SHIFT 2 | 21 | #define UART_SHIFT 2 |
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S index b76075a7e44b..cda096b2acfd 100644 --- a/include/asm-arm/arch-orion/entry-macro.S +++ b/include/asm-arm/arch-orion/entry-macro.S | |||
@@ -3,8 +3,8 @@ | |||
3 | * | 3 | * |
4 | * Low-level IRQ helper macros for Orion platforms | 4 | * Low-level IRQ helper macros for Orion platforms |
5 | * | 5 | * |
6 | * This file is licensed under the terms of the GNU General Public | 6 | * This file is licensed under the terms of the GNU General Public |
7 | * License version 2. This program is licensed "as is" without any | 7 | * License version 2. This program is licensed "as is" without any |
8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
9 | */ | 9 | */ |
10 | 10 | ||
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h index 8a12d213fbdc..65da374de735 100644 --- a/include/asm-arm/arch-orion/hardware.h +++ b/include/asm-arm/arch-orion/hardware.h | |||
@@ -4,7 +4,6 @@ | |||
4 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
7 | * | ||
8 | */ | 7 | */ |
9 | 8 | ||
10 | #ifndef __ASM_ARCH_HARDWARE_H__ | 9 | #ifndef __ASM_ARCH_HARDWARE_H__ |
@@ -12,13 +11,11 @@ | |||
12 | 11 | ||
13 | #include "orion.h" | 12 | #include "orion.h" |
14 | 13 | ||
15 | #define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE | 14 | #define pcibios_assign_all_busses() 1 |
16 | #define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE | ||
17 | 15 | ||
18 | #define pcibios_assign_all_busses() 1 | 16 | #define PCIBIOS_MIN_IO 0x00001000 |
17 | #define PCIBIOS_MIN_MEM 0x01000000 | ||
18 | #define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE | ||
19 | 19 | ||
20 | #define PCIBIOS_MIN_IO 0x1000 | ||
21 | #define PCIBIOS_MIN_MEM 0x01000000 | ||
22 | #define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */ | ||
23 | 20 | ||
24 | #endif /* _ASM_ARCH_HARDWARE_H */ | 21 | #endif |
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h index f787f752e58c..673a418a7419 100644 --- a/include/asm-arm/arch-orion/orion.h +++ b/include/asm-arm/arch-orion/orion.h | |||
@@ -14,32 +14,40 @@ | |||
14 | #ifndef __ASM_ARCH_ORION_H__ | 14 | #ifndef __ASM_ARCH_ORION_H__ |
15 | #define __ASM_ARCH_ORION_H__ | 15 | #define __ASM_ARCH_ORION_H__ |
16 | 16 | ||
17 | /******************************************************************************* | 17 | /***************************************************************************** |
18 | * Orion Address Map | 18 | * Orion Address Map |
19 | * Use the same mapping (1:1 virtual:physical) of internal registers and | 19 | * |
20 | * PCI system (PCI+PCIE) for all machines. | 20 | * virt phys size |
21 | * Each machine defines the rest of its mapping (e.g. device bus flashes) | 21 | * fdd00000 f1000000 1M on-chip peripheral registers |
22 | ******************************************************************************/ | 22 | * fde00000 f2000000 1M PCIe I/O space |
23 | #define ORION_REGS_BASE 0xf1000000 | 23 | * fdf00000 f2100000 1M PCI I/O space |
24 | * fe000000 f0000000 16M PCIe WA space (Orion-NAS only) | ||
25 | ****************************************************************************/ | ||
26 | #define ORION_REGS_PHYS_BASE 0xf1000000 | ||
27 | #define ORION_REGS_VIRT_BASE 0xfdd00000 | ||
24 | #define ORION_REGS_SIZE SZ_1M | 28 | #define ORION_REGS_SIZE SZ_1M |
25 | 29 | ||
26 | #define ORION_PCI_SYS_MEM_BASE 0xe0000000 | 30 | #define ORION_PCIE_IO_PHYS_BASE 0xf2000000 |
27 | #define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE | 31 | #define ORION_PCIE_IO_VIRT_BASE 0xfde00000 |
28 | #define ORION_PCIE_MEM_SIZE SZ_128M | 32 | #define ORION_PCIE_IO_BUS_BASE 0x00000000 |
29 | #define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE) | ||
30 | #define ORION_PCI_MEM_SIZE SZ_128M | ||
31 | |||
32 | #define ORION_PCI_SYS_IO_BASE 0xf2000000 | ||
33 | #define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE | ||
34 | #define ORION_PCIE_IO_SIZE SZ_1M | 33 | #define ORION_PCIE_IO_SIZE SZ_1M |
35 | #define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE) | 34 | |
36 | #define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE) | 35 | #define ORION_PCI_IO_PHYS_BASE 0xf2100000 |
36 | #define ORION_PCI_IO_VIRT_BASE 0xfdf00000 | ||
37 | #define ORION_PCI_IO_BUS_BASE 0x00100000 | ||
37 | #define ORION_PCI_IO_SIZE SZ_1M | 38 | #define ORION_PCI_IO_SIZE SZ_1M |
38 | #define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE) | 39 | |
39 | /* Relevant only for Orion-NAS */ | 40 | /* Relevant only for Orion-NAS */ |
40 | #define ORION_PCIE_WA_BASE 0xf0000000 | 41 | #define ORION_PCIE_WA_PHYS_BASE 0xf0000000 |
42 | #define ORION_PCIE_WA_VIRT_BASE 0xfe000000 | ||
41 | #define ORION_PCIE_WA_SIZE SZ_16M | 43 | #define ORION_PCIE_WA_SIZE SZ_16M |
42 | 44 | ||
45 | #define ORION_PCIE_MEM_PHYS_BASE 0xe0000000 | ||
46 | #define ORION_PCIE_MEM_SIZE SZ_128M | ||
47 | |||
48 | #define ORION_PCI_MEM_PHYS_BASE 0xe8000000 | ||
49 | #define ORION_PCI_MEM_SIZE SZ_128M | ||
50 | |||
43 | /******************************************************************************* | 51 | /******************************************************************************* |
44 | * Supported Devices & Revisions | 52 | * Supported Devices & Revisions |
45 | ******************************************************************************/ | 53 | ******************************************************************************/ |
@@ -57,25 +65,42 @@ | |||
57 | /******************************************************************************* | 65 | /******************************************************************************* |
58 | * Orion Registers Map | 66 | * Orion Registers Map |
59 | ******************************************************************************/ | 67 | ******************************************************************************/ |
60 | #define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000) | 68 | #define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000) |
61 | #define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000) | 69 | #define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x)) |
62 | #define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000) | 70 | |
63 | #define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000) | 71 | #define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000) |
64 | #define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000) | 72 | #define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000) |
65 | #define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000) | 73 | #define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x)) |
66 | #define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000) | 74 | #define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000) |
67 | #define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000) | 75 | #define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000) |
68 | #define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000) | 76 | #define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000) |
69 | 77 | #define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100) | |
70 | #define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x)) | 78 | #define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100) |
71 | #define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x)) | 79 | |
72 | #define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x)) | 80 | #define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) |
73 | #define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x)) | 81 | #define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) |
74 | #define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x)) | 82 | |
75 | #define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x)) | 83 | #define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) |
76 | #define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x)) | 84 | #define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) |
77 | #define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x)) | 85 | |
78 | #define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x)) | 86 | #define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000) |
87 | #define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x)) | ||
88 | |||
89 | #define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000) | ||
90 | #define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000) | ||
91 | #define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x)) | ||
92 | |||
93 | #define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000) | ||
94 | #define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000) | ||
95 | #define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x)) | ||
96 | |||
97 | #define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000) | ||
98 | #define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000) | ||
99 | #define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x)) | ||
100 | |||
101 | #define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000) | ||
102 | #define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000) | ||
103 | #define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x)) | ||
79 | 104 | ||
80 | /******************************************************************************* | 105 | /******************************************************************************* |
81 | * Device Bus Registers | 106 | * Device Bus Registers |
@@ -100,9 +125,6 @@ | |||
100 | #define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) | 125 | #define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) |
101 | #define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) | 126 | #define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) |
102 | #define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) | 127 | #define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) |
103 | #define I2C_BASE ORION_DEV_BUS_REG(0x1000) | ||
104 | #define UART0_BASE ORION_DEV_BUS_REG(0x2000) | ||
105 | #define UART1_BASE ORION_DEV_BUS_REG(0x2100) | ||
106 | #define GPIO_MAX 32 | 128 | #define GPIO_MAX 32 |
107 | 129 | ||
108 | /*************************************************************************** | 130 | /*************************************************************************** |
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h index a1a222fb438c..59f44039909a 100644 --- a/include/asm-arm/arch-orion/uncompress.h +++ b/include/asm-arm/arch-orion/uncompress.h | |||
@@ -10,8 +10,8 @@ | |||
10 | 10 | ||
11 | #include <asm/arch/orion.h> | 11 | #include <asm/arch/orion.h> |
12 | 12 | ||
13 | #define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14)) | 13 | #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) |
14 | #define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0)) | 14 | #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) |
15 | 15 | ||
16 | #define LSR_THRE 0x20 | 16 | #define LSR_THRE 0x20 |
17 | 17 | ||
@@ -27,16 +27,6 @@ static void flush(void) | |||
27 | { | 27 | { |
28 | } | 28 | } |
29 | 29 | ||
30 | static void orion_early_putstr(const char *ptr) | ||
31 | { | ||
32 | char c; | ||
33 | while ((c = *ptr++) != '\0') { | ||
34 | if (c == '\n') | ||
35 | putc('\r'); | ||
36 | putc(c); | ||
37 | } | ||
38 | } | ||
39 | |||
40 | /* | 30 | /* |
41 | * nothing to do | 31 | * nothing to do |
42 | */ | 32 | */ |
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion/vmalloc.h index 23e2a102fe0c..9d580278d2bc 100644 --- a/include/asm-arm/arch-orion/vmalloc.h +++ b/include/asm-arm/arch-orion/vmalloc.h | |||
@@ -2,4 +2,4 @@ | |||
2 | * include/asm-arm/arch-orion/vmalloc.h | 2 | * include/asm-arm/arch-orion/vmalloc.h |
3 | */ | 3 | */ |
4 | 4 | ||
5 | #define VMALLOC_END 0xf0000000 | 5 | #define VMALLOC_END 0xfd800000 |