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-rw-r--r--include/asm-arm/arch-omap/aic23.h116
-rw-r--r--include/asm-arm/arch-omap/blizzard.h12
-rw-r--r--include/asm-arm/arch-omap/board-2430sdp.h39
-rw-r--r--include/asm-arm/arch-omap/board-ams-delta.h76
-rw-r--r--include/asm-arm/arch-omap/board-apollon.h38
-rw-r--r--include/asm-arm/arch-omap/board-fsample.h51
-rw-r--r--include/asm-arm/arch-omap/board-h2.h41
-rw-r--r--include/asm-arm/arch-omap/board-h3.h36
-rw-r--r--include/asm-arm/arch-omap/board-h4.h35
-rw-r--r--include/asm-arm/arch-omap/board-innovator.h52
-rw-r--r--include/asm-arm/arch-omap/board-nokia.h54
-rw-r--r--include/asm-arm/arch-omap/board-osk.h47
-rw-r--r--include/asm-arm/arch-omap/board-palmte.h32
-rw-r--r--include/asm-arm/arch-omap/board-palmtt.h23
-rw-r--r--include/asm-arm/arch-omap/board-palmz71.h26
-rw-r--r--include/asm-arm/arch-omap/board-perseus2.h39
-rw-r--r--include/asm-arm/arch-omap/board-sx1.h52
-rw-r--r--include/asm-arm/arch-omap/board-voiceblue.h20
-rw-r--r--include/asm-arm/arch-omap/board.h186
-rw-r--r--include/asm-arm/arch-omap/clock.h162
-rw-r--r--include/asm-arm/arch-omap/common.h69
-rw-r--r--include/asm-arm/arch-omap/control.h189
-rw-r--r--include/asm-arm/arch-omap/cpu.h402
-rw-r--r--include/asm-arm/arch-omap/debug-macro.S58
-rw-r--r--include/asm-arm/arch-omap/dma.h570
-rw-r--r--include/asm-arm/arch-omap/dmtimer.h84
-rw-r--r--include/asm-arm/arch-omap/dsp_common.h40
-rw-r--r--include/asm-arm/arch-omap/eac.h100
-rw-r--r--include/asm-arm/arch-omap/entry-macro.S89
-rw-r--r--include/asm-arm/arch-omap/fpga.h197
-rw-r--r--include/asm-arm/arch-omap/gpio-switch.h54
-rw-r--r--include/asm-arm/arch-omap/gpio.h122
-rw-r--r--include/asm-arm/arch-omap/gpioexpander.h35
-rw-r--r--include/asm-arm/arch-omap/gpmc.h96
-rw-r--r--include/asm-arm/arch-omap/hardware.h355
-rw-r--r--include/asm-arm/arch-omap/hwa742.h12
-rw-r--r--include/asm-arm/arch-omap/io.h197
-rw-r--r--include/asm-arm/arch-omap/irda.h37
-rw-r--r--include/asm-arm/arch-omap/irqs.h332
-rw-r--r--include/asm-arm/arch-omap/keypad.h39
-rw-r--r--include/asm-arm/arch-omap/lcd_mipid.h24
-rw-r--r--include/asm-arm/arch-omap/led.h24
-rw-r--r--include/asm-arm/arch-omap/mailbox.h73
-rw-r--r--include/asm-arm/arch-omap/mcbsp.h380
-rw-r--r--include/asm-arm/arch-omap/mcspi.h15
-rw-r--r--include/asm-arm/arch-omap/memory.h103
-rw-r--r--include/asm-arm/arch-omap/menelaus.h49
-rw-r--r--include/asm-arm/arch-omap/mmc.h74
-rw-r--r--include/asm-arm/arch-omap/mtd-xip.h61
-rw-r--r--include/asm-arm/arch-omap/mux.h615
-rw-r--r--include/asm-arm/arch-omap/nand.h24
-rw-r--r--include/asm-arm/arch-omap/omap-alsa.h123
-rw-r--r--include/asm-arm/arch-omap/omap1510.h48
-rw-r--r--include/asm-arm/arch-omap/omap16xx.h197
-rw-r--r--include/asm-arm/arch-omap/omap24xx.h107
-rw-r--r--include/asm-arm/arch-omap/omap34xx.h72
-rw-r--r--include/asm-arm/arch-omap/omap730.h102
-rw-r--r--include/asm-arm/arch-omap/omapfb.h395
-rw-r--r--include/asm-arm/arch-omap/onenand.h21
-rw-r--r--include/asm-arm/arch-omap/param.h8
-rw-r--r--include/asm-arm/arch-omap/pm.h356
-rw-r--r--include/asm-arm/arch-omap/prcm.h33
-rw-r--r--include/asm-arm/arch-omap/sdrc.h75
-rw-r--r--include/asm-arm/arch-omap/serial.h37
-rw-r--r--include/asm-arm/arch-omap/sram.h56
-rw-r--r--include/asm-arm/arch-omap/system.h49
-rw-r--r--include/asm-arm/arch-omap/tc.h106
-rw-r--r--include/asm-arm/arch-omap/timex.h41
-rw-r--r--include/asm-arm/arch-omap/uncompress.h83
-rw-r--r--include/asm-arm/arch-omap/usb.h141
-rw-r--r--include/asm-arm/arch-omap/vmalloc.h21
71 files changed, 0 insertions, 7727 deletions
diff --git a/include/asm-arm/arch-omap/aic23.h b/include/asm-arm/arch-omap/aic23.h
deleted file mode 100644
index aec2d6563622..000000000000
--- a/include/asm-arm/arch-omap/aic23.h
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/aic23.h
3 *
4 * Hardware definitions for TI TLV320AIC23 audio codec
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifndef __ASM_ARCH_AIC23_H
31#define __ASM_ARCH_AIC23_H
32
33// Codec TLV320AIC23
34#define LEFT_LINE_VOLUME_ADDR 0x00
35#define RIGHT_LINE_VOLUME_ADDR 0x01
36#define LEFT_CHANNEL_VOLUME_ADDR 0x02
37#define RIGHT_CHANNEL_VOLUME_ADDR 0x03
38#define ANALOG_AUDIO_CONTROL_ADDR 0x04
39#define DIGITAL_AUDIO_CONTROL_ADDR 0x05
40#define POWER_DOWN_CONTROL_ADDR 0x06
41#define DIGITAL_AUDIO_FORMAT_ADDR 0x07
42#define SAMPLE_RATE_CONTROL_ADDR 0x08
43#define DIGITAL_INTERFACE_ACT_ADDR 0x09
44#define RESET_CONTROL_ADDR 0x0F
45
46// Left (right) line input volume control register
47#define LRS_ENABLED 0x0100
48#define LIM_MUTED 0x0080
49#define LIV_DEFAULT 0x0017
50#define LIV_MAX 0x001f
51#define LIV_MIN 0x0000
52
53// Left (right) channel headphone volume control register
54#define LZC_ON 0x0080
55#define LHV_DEFAULT 0x0079
56#define LHV_MAX 0x007f
57#define LHV_MIN 0x0000
58
59// Analog audio path control register
60#define STA_REG(x) ((x)<<6)
61#define STE_ENABLED 0x0020
62#define DAC_SELECTED 0x0010
63#define BYPASS_ON 0x0008
64#define INSEL_MIC 0x0004
65#define MICM_MUTED 0x0002
66#define MICB_20DB 0x0001
67
68// Digital audio path control register
69#define DACM_MUTE 0x0008
70#define DEEMP_32K 0x0002
71#define DEEMP_44K 0x0004
72#define DEEMP_48K 0x0006
73#define ADCHP_ON 0x0001
74
75// Power control down register
76#define DEVICE_POWER_OFF 0x0080
77#define CLK_OFF 0x0040
78#define OSC_OFF 0x0020
79#define OUT_OFF 0x0010
80#define DAC_OFF 0x0008
81#define ADC_OFF 0x0004
82#define MIC_OFF 0x0002
83#define LINE_OFF 0x0001
84
85// Digital audio interface register
86#define MS_MASTER 0x0040
87#define LRSWAP_ON 0x0020
88#define LRP_ON 0x0010
89#define IWL_16 0x0000
90#define IWL_20 0x0004
91#define IWL_24 0x0008
92#define IWL_32 0x000C
93#define FOR_I2S 0x0002
94#define FOR_DSP 0x0003
95
96// Sample rate control register
97#define CLKOUT_HALF 0x0080
98#define CLKIN_HALF 0x0040
99#define BOSR_384fs 0x0002 // BOSR_272fs when in USB mode
100#define USB_CLK_ON 0x0001
101#define SR_MASK 0xf
102#define CLKOUT_SHIFT 7
103#define CLKIN_SHIFT 6
104#define SR_SHIFT 2
105#define BOSR_SHIFT 1
106
107// Digital interface register
108#define ACT_ON 0x0001
109
110#define TLV320AIC23ID1 (0x1a) // cs low
111#define TLV320AIC23ID2 (0x1b) // cs high
112
113void aic23_power_up(void);
114void aic23_power_down(void);
115
116#endif /* __ASM_ARCH_AIC23_H */
diff --git a/include/asm-arm/arch-omap/blizzard.h b/include/asm-arm/arch-omap/blizzard.h
deleted file mode 100644
index 8d160f171372..000000000000
--- a/include/asm-arm/arch-omap/blizzard.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _BLIZZARD_H
2#define _BLIZZARD_H
3
4struct blizzard_platform_data {
5 void (*power_up)(struct device *dev);
6 void (*power_down)(struct device *dev);
7 unsigned long (*get_clock_rate)(struct device *dev);
8
9 unsigned te_connected : 1;
10};
11
12#endif
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h
deleted file mode 100644
index c7db9004ec31..000000000000
--- a/include/asm-arm/arch-omap/board-2430sdp.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-2430sdp.h
3 *
4 * Hardware definitions for TI OMAP2430 SDP board.
5 *
6 * Based on board-h4.h by Dirk Behme <dirk.behme@de.bosch.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_2430SDP_H
30#define __ASM_ARCH_OMAP_2430SDP_H
31
32/* Placeholder for 2430SDP specific defines */
33#define OMAP24XX_ETHR_START 0x08000300
34#define OMAP24XX_ETHR_GPIO_IRQ 149
35#define SDP2430_CS0_BASE 0x04000000
36
37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
38
39#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/include/asm-arm/arch-omap/board-ams-delta.h b/include/asm-arm/arch-omap/board-ams-delta.h
deleted file mode 100644
index 9aee15d97145..000000000000
--- a/include/asm-arm/arch-omap/board-ams-delta.h
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-ams-delta.h
3 *
4 * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
27#define __ASM_ARCH_OMAP_AMS_DELTA_H
28
29#if defined (CONFIG_MACH_AMS_DELTA)
30
31#define AMS_DELTA_LATCH1_PHYS 0x01000000
32#define AMS_DELTA_LATCH1_VIRT 0xEA000000
33#define AMS_DELTA_MODEM_PHYS 0x04000000
34#define AMS_DELTA_MODEM_VIRT 0xEB000000
35#define AMS_DELTA_LATCH2_PHYS 0x08000000
36#define AMS_DELTA_LATCH2_VIRT 0xEC000000
37
38#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
39#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
40#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
41#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
42#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
43#define AMS_DELTA_LATCH1_LED_VOICE 0x20
44
45#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
46#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
47#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
48#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
49#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
50#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
51#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
52#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
53#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
54#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
55#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
56#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
57#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
58#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
59
60#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
61#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
62#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
63#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
64#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
65#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
66#define AMS_DELTA_GPIO_PIN_CONFIG 11
67#define AMS_DELTA_GPIO_PIN_NAND_RB 12
68
69#ifndef __ASSEMBLY__
70void ams_delta_latch1_write(u8 mask, u8 value);
71void ams_delta_latch2_write(u16 mask, u16 value);
72#endif
73
74#endif /* CONFIG_MACH_AMS_DELTA */
75
76#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h
deleted file mode 100644
index 547125a4695e..000000000000
--- a/include/asm-arm/arch-omap/board-apollon.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-apollon.h
3 *
4 * Hardware definitions for Samsung OMAP24XX Apollon board.
5 *
6 * Initial creation by Kyungmin Park <kyungmin.park@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_APOLLON_H
30#define __ASM_ARCH_OMAP_APOLLON_H
31
32extern void apollon_mmc_init(void);
33
34/* Placeholder for APOLLON specific defines */
35#define APOLLON_ETHR_GPIO_IRQ 74
36
37#endif /* __ASM_ARCH_OMAP_APOLLON_H */
38
diff --git a/include/asm-arm/arch-omap/board-fsample.h b/include/asm-arm/arch-omap/board-fsample.h
deleted file mode 100644
index 89a1e529fb6f..000000000000
--- a/include/asm-arm/arch-omap/board-fsample.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-fsample.h
3 *
4 * Board-specific goodies for TI F-Sample.
5 *
6 * Copyright (C) 2006 Google, Inc.
7 * Author: Brian Swetland <swetland@google.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_OMAP_FSAMPLE_H
15#define __ASM_ARCH_OMAP_FSAMPLE_H
16
17/* fsample is pretty close to p2-sample */
18#include <asm/arch/board-perseus2.h>
19
20#define fsample_cpld_read(reg) __raw_readb(reg)
21#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
22
23#define FSAMPLE_CPLD_BASE 0xE8100000
24#define FSAMPLE_CPLD_SIZE SZ_4K
25#define FSAMPLE_CPLD_START 0x05080000
26
27#define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
28#define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
29#define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
30#define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
31#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
32#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
33
34#define FSAMPLE_CPLD_BIT_BT_RESET 0
35#define FSAMPLE_CPLD_BIT_LCD_RESET 1
36#define FSAMPLE_CPLD_BIT_CAM_PWDN 2
37#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
38#define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
39#define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
40#define FSAMPLE_CPLD_BIT_BACKLIGHT 6
41#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
42#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
43#define FSAMPLE_CPLD_BIT_OTG_RESET 9
44
45#define fsample_cpld_set(bit) \
46 fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
47
48#define fsample_cpld_clear(bit) \
49 fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
50
51#endif
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
deleted file mode 100644
index c322796d0d26..000000000000
--- a/include/asm-arm/arch-omap/board-h2.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-h2.h
3 *
4 * Hardware definitions for TI OMAP1610 H2 board.
5 *
6 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_H2_H
30#define __ASM_ARCH_OMAP_H2_H
31
32/* Placeholder for H2 specific defines */
33
34/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
35#define OMAP1610_ETHR_START 0x04000300
36
37extern void h2_mmc_init(void);
38extern void h2_mmc_slot_cover_handler(void *arg, int state);
39
40#endif /* __ASM_ARCH_OMAP_H2_H */
41
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
deleted file mode 100644
index c5d0f32a40ac..000000000000
--- a/include/asm-arm/arch-omap/board-h3.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-h3.h
3 *
4 * Copyright (C) 2001 RidgeRun, Inc.
5 * Copyright (C) 2004 Texas Instruments, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_ARCH_OMAP_H3_H
28#define __ASM_ARCH_OMAP_H3_H
29
30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
31#define OMAP1710_ETHR_START 0x04000300
32
33extern void h3_mmc_init(void);
34extern void h3_mmc_slot_cover_handler(void *arg, int state);
35
36#endif /* __ASM_ARCH_OMAP_H3_H */
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
deleted file mode 100644
index 7e0efef4bb65..000000000000
--- a/include/asm-arm/arch-omap/board-h4.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-h4.h
3 *
4 * Hardware definitions for TI OMAP1610 H4 board.
5 *
6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_H4_H
30#define __ASM_ARCH_OMAP_H4_H
31
32/* Placeholder for H4 specific defines */
33#define OMAP24XX_ETHR_GPIO_IRQ 92
34#endif /* __ASM_ARCH_OMAP_H4_H */
35
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
deleted file mode 100644
index 9ca03dec9d36..000000000000
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-innovator.h
3 *
4 * Copyright (C) 2001 RidgeRun, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
27#define __ASM_ARCH_OMAP_INNOVATOR_H
28
29#if defined (CONFIG_ARCH_OMAP15XX)
30
31#ifndef OMAP_SDRAM_DEVICE
32#define OMAP_SDRAM_DEVICE D256M_1X16_4B
33#endif
34
35#define OMAP1510P1_IMIF_PRI_VALUE 0x00
36#define OMAP1510P1_EMIFS_PRI_VALUE 0x00
37#define OMAP1510P1_EMIFF_PRI_VALUE 0x00
38
39#ifndef __ASSEMBLY__
40void fpga_write(unsigned char val, int reg);
41unsigned char fpga_read(int reg);
42#endif
43
44#endif /* CONFIG_ARCH_OMAP15XX */
45
46#if defined (CONFIG_ARCH_OMAP16XX)
47
48/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
49#define INNOVATOR1610_ETHR_START 0x04000300
50
51#endif /* CONFIG_ARCH_OMAP1610 */
52#endif /* __ASM_ARCH_OMAP_INNOVATOR_H */
diff --git a/include/asm-arm/arch-omap/board-nokia.h b/include/asm-arm/arch-omap/board-nokia.h
deleted file mode 100644
index 72deea203493..000000000000
--- a/include/asm-arm/arch-omap/board-nokia.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-nokia.h
3 *
4 * Information structures for Nokia-specific board config data
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 */
8
9#ifndef _OMAP_BOARD_NOKIA_H
10#define _OMAP_BOARD_NOKIA_H
11
12#include <linux/types.h>
13
14#define OMAP_TAG_NOKIA_BT 0x4e01
15#define OMAP_TAG_WLAN_CX3110X 0x4e02
16#define OMAP_TAG_CBUS 0x4e03
17#define OMAP_TAG_EM_ASIC_BB5 0x4e04
18
19
20#define BT_CHIP_CSR 1
21#define BT_CHIP_TI 2
22
23#define BT_SYSCLK_12 1
24#define BT_SYSCLK_38_4 2
25
26struct omap_bluetooth_config {
27 u8 chip_type;
28 u8 bt_wakeup_gpio;
29 u8 host_wakeup_gpio;
30 u8 reset_gpio;
31 u8 bt_uart;
32 u8 bd_addr[6];
33 u8 bt_sysclk;
34};
35
36struct omap_wlan_cx3110x_config {
37 u8 chip_type;
38 s16 power_gpio;
39 s16 irq_gpio;
40 s16 spi_cs_gpio;
41};
42
43struct omap_cbus_config {
44 s16 clk_gpio;
45 s16 dat_gpio;
46 s16 sel_gpio;
47};
48
49struct omap_em_asic_bb5_config {
50 s16 retu_irq_gpio;
51 s16 tahvo_irq_gpio;
52};
53
54#endif
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
deleted file mode 100644
index 94926090e475..000000000000
--- a/include/asm-arm/arch-omap/board-osk.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-osk.h
3 *
4 * Hardware definitions for TI OMAP5912 OSK board.
5 *
6 * Written by Dirk Behme <dirk.behme@de.bosch.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_OSK_H
30#define __ASM_ARCH_OMAP_OSK_H
31
32/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
33#define OMAP_OSK_ETHR_START 0x04800300
34
35/* TPS65010 has four GPIOs. nPG and LED2 can be treated like GPIOs with
36 * alternate pin configurations for hardware-controlled blinking.
37 */
38#define OSK_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
39# define OSK_TPS_GPIO_USB_PWR_EN (OSK_TPS_GPIO_BASE + 0)
40# define OSK_TPS_GPIO_LED_D3 (OSK_TPS_GPIO_BASE + 1)
41# define OSK_TPS_GPIO_LAN_RESET (OSK_TPS_GPIO_BASE + 2)
42# define OSK_TPS_GPIO_DSP_PWR_EN (OSK_TPS_GPIO_BASE + 3)
43# define OSK_TPS_GPIO_LED_D9 (OSK_TPS_GPIO_BASE + 4)
44# define OSK_TPS_GPIO_LED_D2 (OSK_TPS_GPIO_BASE + 5)
45
46#endif /* __ASM_ARCH_OMAP_OSK_H */
47
diff --git a/include/asm-arm/arch-omap/board-palmte.h b/include/asm-arm/arch-omap/board-palmte.h
deleted file mode 100644
index 6fac2c8935be..000000000000
--- a/include/asm-arm/arch-omap/board-palmte.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-palmte.h
3 *
4 * Hardware definitions for the Palm Tungsten E device.
5 *
6 * Maintainters : http://palmtelinux.sf.net
7 * palmtelinux-developpers@lists.sf.net
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __OMAP_BOARD_PALMTE_H
15#define __OMAP_BOARD_PALMTE_H
16
17#define PALMTE_USBDETECT_GPIO 0
18#define PALMTE_USB_OR_DC_GPIO 1
19#define PALMTE_TSC_GPIO 4
20#define PALMTE_PINTDAV_GPIO 6
21#define PALMTE_MMC_WP_GPIO 8
22#define PALMTE_MMC_POWER_GPIO 9
23#define PALMTE_HDQ_GPIO 11
24#define PALMTE_HEADPHONES_GPIO 14
25#define PALMTE_SPEAKER_GPIO 15
26#define PALMTE_DC_GPIO OMAP_MPUIO(2)
27#define PALMTE_MMC_SWITCH_GPIO OMAP_MPUIO(4)
28#define PALMTE_MMC1_GPIO OMAP_MPUIO(6)
29#define PALMTE_MMC2_GPIO OMAP_MPUIO(7)
30#define PALMTE_MMC3_GPIO OMAP_MPUIO(11)
31
32#endif /* __OMAP_BOARD_PALMTE_H */
diff --git a/include/asm-arm/arch-omap/board-palmtt.h b/include/asm-arm/arch-omap/board-palmtt.h
deleted file mode 100644
index d9590b0ec90e..000000000000
--- a/include/asm-arm/arch-omap/board-palmtt.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-palmte.h
3 *
4 * Hardware definitions for the Palm Tungsten|T device.
5 *
6 * Maintainters : Marek Vasut <marek.vasut@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __OMAP_BOARD_PALMTT_H
14#define __OMAP_BOARD_PALMTT_H
15
16#define PALMTT_USBDETECT_GPIO 0
17#define PALMTT_CABLE_GPIO 1
18#define PALMTT_LED_GPIO 3
19#define PALMTT_PENIRQ_GPIO 6
20#define PALMTT_MMC_WP_GPIO 8
21#define PALMTT_HDQ_GPIO 11
22
23#endif /* __OMAP_BOARD_PALMTT_H */
diff --git a/include/asm-arm/arch-omap/board-palmz71.h b/include/asm-arm/arch-omap/board-palmz71.h
deleted file mode 100644
index 1252a859787d..000000000000
--- a/include/asm-arm/arch-omap/board-palmz71.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-palmz71.h
3 *
4 * Hardware definitions for the Palm Zire71 device.
5 *
6 * Maintainters : Marek Vasut <marek.vasut@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __OMAP_BOARD_PALMZ71_H
14#define __OMAP_BOARD_PALMZ71_H
15
16#define PALMZ71_USBDETECT_GPIO 0
17#define PALMZ71_PENIRQ_GPIO 6
18#define PALMZ71_MMC_WP_GPIO 8
19#define PALMZ71_HDQ_GPIO 11
20
21#define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1)
22#define PALMZ71_CABLE_GPIO OMAP_MPUIO(2)
23#define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3)
24#define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4)
25
26#endif /* __OMAP_BOARD_PALMZ71_H */
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
deleted file mode 100644
index d7429cb0f726..000000000000
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-perseus2.h
3 *
4 * Copyright 2003 by Texas Instruments Incorporated
5 * OMAP730 / Perseus2 support by Jean Pihet
6 *
7 * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
8 * Author: RidgeRun, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#ifndef __ASM_ARCH_OMAP_PERSEUS2_H
31#define __ASM_ARCH_OMAP_PERSEUS2_H
32
33#include <asm/arch/fpga.h>
34
35#ifndef OMAP_SDRAM_DEVICE
36#define OMAP_SDRAM_DEVICE D256M_1X16_4B
37#endif
38
39#endif
diff --git a/include/asm-arm/arch-omap/board-sx1.h b/include/asm-arm/arch-omap/board-sx1.h
deleted file mode 100644
index 355adbdaae33..000000000000
--- a/include/asm-arm/arch-omap/board-sx1.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Siemens SX1 board definitions
3 *
4 * Copyright: Vovan888 at gmail com
5 *
6 * This package is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 */
14
15#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
16#define __ASM_ARCH_SX1_I2C_CHIPS_H
17
18#define SOFIA_MAX_LIGHT_VAL 0x2B
19
20#define SOFIA_I2C_ADDR 0x32
21/* Sofia reg 3 bits masks */
22#define SOFIA_POWER1_REG 0x03
23
24#define SOFIA_USB_POWER 0x01
25#define SOFIA_MMC_POWER 0x04
26#define SOFIA_BLUETOOTH_POWER 0x08
27#define SOFIA_MMILIGHT_POWER 0x20
28
29#define SOFIA_POWER2_REG 0x04
30#define SOFIA_BACKLIGHT_REG 0x06
31#define SOFIA_KEYLIGHT_REG 0x07
32#define SOFIA_DIMMING_REG 0x09
33
34
35/* Function Prototypes for SX1 devices control on I2C bus */
36
37int sx1_setbacklight(u8 backlight);
38int sx1_getbacklight(u8 *backlight);
39int sx1_setkeylight(u8 keylight);
40int sx1_getkeylight(u8 *keylight);
41
42int sx1_setmmipower(u8 onoff);
43int sx1_setusbpower(u8 onoff);
44int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
45int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
46
47/* MMC prototypes */
48
49extern void sx1_mmc_init(void);
50extern void sx1_mmc_slot_cover_handler(void *arg, int state);
51
52#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
diff --git a/include/asm-arm/arch-omap/board-voiceblue.h b/include/asm-arm/arch-omap/board-voiceblue.h
deleted file mode 100644
index ed6d346ee123..000000000000
--- a/include/asm-arm/arch-omap/board-voiceblue.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
3 *
4 * Hardware definitions for OMAP5910 based VoiceBlue board.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_VOICEBLUE_H
12#define __ASM_ARCH_VOICEBLUE_H
13
14extern void voiceblue_wdt_enable(void);
15extern void voiceblue_wdt_disable(void);
16extern void voiceblue_wdt_ping(void);
17extern void voiceblue_reset(void);
18
19#endif /* __ASM_ARCH_VOICEBLUE_H */
20
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
deleted file mode 100644
index 99564c70f128..000000000000
--- a/include/asm-arm/arch-omap/board.h
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/board.h
3 *
4 * Information structures for board-specific data
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 */
9
10#ifndef _OMAP_BOARD_H
11#define _OMAP_BOARD_H
12
13#include <linux/types.h>
14
15#include <asm/arch/gpio-switch.h>
16
17/* Different peripheral ids */
18#define OMAP_TAG_CLOCK 0x4f01
19#define OMAP_TAG_MMC 0x4f02
20#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
21#define OMAP_TAG_USB 0x4f04
22#define OMAP_TAG_LCD 0x4f05
23#define OMAP_TAG_GPIO_SWITCH 0x4f06
24#define OMAP_TAG_UART 0x4f07
25#define OMAP_TAG_FBMEM 0x4f08
26#define OMAP_TAG_STI_CONSOLE 0x4f09
27#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
28
29#define OMAP_TAG_BOOT_REASON 0x4f80
30#define OMAP_TAG_FLASH_PART 0x4f81
31#define OMAP_TAG_VERSION_STR 0x4f82
32
33struct omap_clock_config {
34 /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
35 u8 system_clock_type;
36};
37
38struct omap_mmc_conf {
39 unsigned enabled:1;
40 /* nomux means "standard" muxing is wrong on this board, and that
41 * board-specific code handled it before common init logic.
42 */
43 unsigned nomux:1;
44 /* switch pin can be for card detect (default) or card cover */
45 unsigned cover:1;
46 /* 4 wire signaling is optional, and is only used for SD/SDIO */
47 unsigned wire4:1;
48 s16 power_pin;
49 s16 switch_pin;
50 s16 wp_pin;
51};
52
53struct omap_mmc_config {
54 struct omap_mmc_conf mmc[2];
55};
56
57struct omap_serial_console_config {
58 u8 console_uart;
59 u32 console_speed;
60};
61
62struct omap_sti_console_config {
63 unsigned enable:1;
64 u8 channel;
65};
66
67struct omap_camera_sensor_config {
68 u16 reset_gpio;
69 int (*power_on)(void * data);
70 int (*power_off)(void * data);
71};
72
73struct omap_usb_config {
74 /* Configure drivers according to the connectors on your board:
75 * - "A" connector (rectagular)
76 * ... for host/OHCI use, set "register_host".
77 * - "B" connector (squarish) or "Mini-B"
78 * ... for device/gadget use, set "register_dev".
79 * - "Mini-AB" connector (very similar to Mini-B)
80 * ... for OTG use as device OR host, initialize "otg"
81 */
82 unsigned register_host:1;
83 unsigned register_dev:1;
84 u8 otg; /* port number, 1-based: usb1 == 2 */
85
86 u8 hmc_mode;
87
88 /* implicitly true if otg: host supports remote wakeup? */
89 u8 rwc;
90
91 /* signaling pins used to talk to transceiver on usbN:
92 * 0 == usbN unused
93 * 2 == usb0-only, using internal transceiver
94 * 3 == 3 wire bidirectional
95 * 4 == 4 wire bidirectional
96 * 6 == 6 wire unidirectional (or TLL)
97 */
98 u8 pins[3];
99};
100
101struct omap_lcd_config {
102 char panel_name[16];
103 char ctrl_name[16];
104 s16 nreset_gpio;
105 u8 data_lines;
106};
107
108struct device;
109struct fb_info;
110struct omap_backlight_config {
111 int default_intensity;
112 int (*set_power)(struct device *dev, int state);
113 int (*check_fb)(struct fb_info *fb);
114};
115
116struct omap_fbmem_config {
117 u32 start;
118 u32 size;
119};
120
121struct omap_pwm_led_platform_data {
122 const char *name;
123 int intensity_timer;
124 int blink_timer;
125 void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
126};
127
128/* See include/asm-arm/arch-omap/gpio-switch.h for definitions */
129struct omap_gpio_switch_config {
130 char name[12];
131 u16 gpio;
132 int flags:4;
133 int type:4;
134 int key_code:24; /* Linux key code */
135};
136
137struct omap_uart_config {
138 /* Bit field of UARTs present; bit 0 --> UART1 */
139 unsigned int enabled_uarts;
140};
141
142
143struct omap_flash_part_config {
144 char part_table[0];
145};
146
147struct omap_boot_reason_config {
148 char reason_str[12];
149};
150
151struct omap_version_config {
152 char component[12];
153 char version[12];
154};
155
156
157#include <asm/arch/board-nokia.h>
158
159struct omap_board_config_entry {
160 u16 tag;
161 u16 len;
162 u8 data[0];
163};
164
165struct omap_board_config_kernel {
166 u16 tag;
167 const void *data;
168};
169
170extern const void *__omap_get_config(u16 tag, size_t len, int nr);
171
172#define omap_get_config(tag, type) \
173 ((const type *) __omap_get_config((tag), sizeof(type), 0))
174#define omap_get_nr_config(tag, type, nr) \
175 ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
176
177extern const void *omap_get_var_config(u16 tag, size_t *len);
178
179extern struct omap_board_config_kernel *omap_board_config;
180extern int omap_board_config_size;
181
182
183/* for TI reference platforms sharing the same debug card */
184extern int debug_card_init(u32 addr, unsigned gpio);
185
186#endif
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
deleted file mode 100644
index 4c7b3514f71a..000000000000
--- a/include/asm-arm/arch-omap/clock.h
+++ /dev/null
@@ -1,162 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ARCH_ARM_OMAP_CLOCK_H
14#define __ARCH_ARM_OMAP_CLOCK_H
15
16struct module;
17struct clk;
18
19#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
20
21struct clksel_rate {
22 u8 div;
23 u32 val;
24 u8 flags;
25};
26
27struct clksel {
28 struct clk *parent;
29 const struct clksel_rate *rates;
30};
31
32struct dpll_data {
33 void __iomem *mult_div1_reg;
34 u32 mult_mask;
35 u32 div1_mask;
36 u16 last_rounded_m;
37 u8 last_rounded_n;
38 unsigned long last_rounded_rate;
39 unsigned int rate_tolerance;
40 u16 max_multiplier;
41 u8 max_divider;
42 u32 max_tolerance;
43# if defined(CONFIG_ARCH_OMAP3)
44 u8 modes;
45 void __iomem *control_reg;
46 u32 enable_mask;
47 u8 auto_recal_bit;
48 u8 recal_en_bit;
49 u8 recal_st_bit;
50 void __iomem *autoidle_reg;
51 u32 autoidle_mask;
52 void __iomem *idlest_reg;
53 u8 idlest_bit;
54# endif
55};
56
57#endif
58
59struct clk {
60 struct list_head node;
61 struct module *owner;
62 const char *name;
63 int id;
64 struct clk *parent;
65 unsigned long rate;
66 __u32 flags;
67 void __iomem *enable_reg;
68 __u8 enable_bit;
69 __s8 usecount;
70 void (*recalc)(struct clk *);
71 int (*set_rate)(struct clk *, unsigned long);
72 long (*round_rate)(struct clk *, unsigned long);
73 void (*init)(struct clk *);
74 int (*enable)(struct clk *);
75 void (*disable)(struct clk *);
76#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
77 u8 fixed_div;
78 void __iomem *clksel_reg;
79 u32 clksel_mask;
80 const struct clksel *clksel;
81 struct dpll_data *dpll_data;
82#else
83 __u8 rate_offset;
84 __u8 src_offset;
85#endif
86#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
87 struct dentry *dent; /* For visible tree hierarchy */
88#endif
89};
90
91struct cpufreq_frequency_table;
92
93struct clk_functions {
94 int (*clk_enable)(struct clk *clk);
95 void (*clk_disable)(struct clk *clk);
96 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
97 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
98 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
99 struct clk * (*clk_get_parent)(struct clk *clk);
100 void (*clk_allow_idle)(struct clk *clk);
101 void (*clk_deny_idle)(struct clk *clk);
102 void (*clk_disable_unused)(struct clk *clk);
103#ifdef CONFIG_CPU_FREQ
104 void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
105#endif
106};
107
108extern unsigned int mpurate;
109
110extern int clk_init(struct clk_functions * custom_clocks);
111extern int clk_register(struct clk *clk);
112extern void clk_unregister(struct clk *clk);
113extern void propagate_rate(struct clk *clk);
114extern void recalculate_root_clocks(void);
115extern void followparent_recalc(struct clk * clk);
116extern void clk_allow_idle(struct clk *clk);
117extern void clk_deny_idle(struct clk *clk);
118extern int clk_get_usecount(struct clk *clk);
119extern void clk_enable_init_clocks(void);
120
121/* Clock flags */
122#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
123#define RATE_FIXED (1 << 1) /* Fixed clock rate */
124#define RATE_PROPAGATES (1 << 2) /* Program children too */
125#define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */
126#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
127#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
128#define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
129#define CLOCK_IDLE_CONTROL (1 << 7)
130#define CLOCK_NO_IDLE_PARENT (1 << 8)
131#define DELAYED_APP (1 << 9) /* Delay application of clock */
132#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
133#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
134#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
135/* bits 13-20 are currently free */
136#define CLOCK_IN_OMAP310 (1 << 21)
137#define CLOCK_IN_OMAP730 (1 << 22)
138#define CLOCK_IN_OMAP1510 (1 << 23)
139#define CLOCK_IN_OMAP16XX (1 << 24)
140#define CLOCK_IN_OMAP242X (1 << 25)
141#define CLOCK_IN_OMAP243X (1 << 26)
142#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
143#define PARENT_CONTROLS_CLOCK (1 << 28)
144#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
145#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
146
147/* Clksel_rate flags */
148#define DEFAULT_RATE (1 << 0)
149#define RATE_IN_242X (1 << 1)
150#define RATE_IN_243X (1 << 2)
151#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
152#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
153
154#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
155
156
157/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
158#define CORE_CLK_SRC_32K 0
159#define CORE_CLK_SRC_DPLL 1
160#define CORE_CLK_SRC_DPLL_X2 2
161
162#endif
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
deleted file mode 100644
index 8ac03071f60c..000000000000
--- a/include/asm-arm/arch-omap/common.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/common.h
3 *
4 * Header for code common to all OMAP machines.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
28#define __ARCH_ARM_MACH_OMAP_COMMON_H
29
30#include <linux/i2c.h>
31
32struct sys_timer;
33
34extern void omap_map_common_io(void);
35extern struct sys_timer omap_timer;
36extern void omap_serial_init(void);
37#ifdef CONFIG_I2C_OMAP
38extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
39 struct i2c_board_info const *info,
40 unsigned len);
41#else
42static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
43 struct i2c_board_info const *info,
44 unsigned len)
45{
46 return 0;
47}
48#endif
49
50/* IO bases for various OMAP processors */
51struct omap_globals {
52 void __iomem *tap; /* Control module ID code */
53 void __iomem *sdrc; /* SDRAM Controller */
54 void __iomem *sms; /* SDRAM Memory Scheduler */
55 void __iomem *ctrl; /* System Control Module */
56 void __iomem *prm; /* Power and Reset Management */
57 void __iomem *cm; /* Clock Management */
58};
59
60void omap2_set_globals_242x(void);
61void omap2_set_globals_243x(void);
62void omap2_set_globals_343x(void);
63
64/* These get called from omap2_set_globals_xxxx(), do not call these */
65void omap2_set_globals_memory(struct omap_globals *);
66void omap2_set_globals_control(struct omap_globals *);
67void omap2_set_globals_prcm(struct omap_globals *);
68
69#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
deleted file mode 100644
index 987553e3eeb9..000000000000
--- a/include/asm-arm/arch-omap/control.h
+++ /dev/null
@@ -1,189 +0,0 @@
1#ifndef __ASM_ARCH_CONTROL_H
2#define __ASM_ARCH_CONTROL_H
3
4/*
5 * include/asm-arm/arch-omap/control.h
6 *
7 * OMAP2/3 System Control Module definitions
8 *
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Copyright (C) 2007 Nokia Corporation
11 *
12 * Written by Paul Walmsley
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation.
17 */
18
19#include <asm/arch/io.h>
20
21#define OMAP242X_CTRL_REGADDR(reg) \
22 (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
23#define OMAP243X_CTRL_REGADDR(reg) \
24 (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
25#define OMAP343X_CTRL_REGADDR(reg) \
26 (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
27
28/*
29 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
30 * OMAP24XX and OMAP34XX.
31 */
32
33/* Control submodule offsets */
34
35#define OMAP2_CONTROL_INTERFACE 0x000
36#define OMAP2_CONTROL_PADCONFS 0x030
37#define OMAP2_CONTROL_GENERAL 0x270
38#define OMAP343X_CONTROL_MEM_WKUP 0x600
39#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
40#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
41
42/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
43
44#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
45
46/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
47#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
48#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
49#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
50#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
51#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
52#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
53#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
54#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
55#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
56#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
57#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
58#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
59
60/* 242x-only CONTROL_GENERAL register offsets */
61#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
62#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
63
64/* 243x-only CONTROL_GENERAL register offsets */
65/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
66#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
67#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
68#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
69#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
70#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
71
72/* 24xx-only CONTROL_GENERAL register offsets */
73#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
74#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
75#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
76#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
77#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
78#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
79#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
80#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
81#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
82#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
83#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
84#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
85#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
86#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
87#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
88#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
89#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
90#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
91#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
92#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
93#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
94#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
95#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
96#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
97#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
98#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
99#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
100#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
101#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
102#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
103#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
104
105/* 34xx-only CONTROL_GENERAL register offsets */
106#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
107#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
108#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
109#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
110#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
111#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
112#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
113#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
114#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
115#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
116#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
117#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
118#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
119#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
120#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
121#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
122#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
123#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
124#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
125#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
126#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
127#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
128#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
129#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
130#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
131#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
132#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
133#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
134#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
135#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
136#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
137
138/*
139 * REVISIT: This list of registers is not comprehensive - there are more
140 * that should be added.
141 */
142
143/*
144 * Control module register bit defines - these should eventually go into
145 * their own regbits file. Some of these will be complicated, depending
146 * on the device type (general-purpose, emulator, test, secure, bad, other)
147 * and the security mode (secure, non-secure, don't care)
148 */
149/* CONTROL_DEVCONF0 bits */
150#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
151#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
152#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
153
154/* CONTROL_DEVCONF1 bits */
155#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
156#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
157#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
158
159/* CONTROL_STATUS bits */
160#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
161#define OMAP2_SYSBOOT_5_MASK (1 << 5)
162#define OMAP2_SYSBOOT_4_MASK (1 << 4)
163#define OMAP2_SYSBOOT_3_MASK (1 << 3)
164#define OMAP2_SYSBOOT_2_MASK (1 << 2)
165#define OMAP2_SYSBOOT_1_MASK (1 << 1)
166#define OMAP2_SYSBOOT_0_MASK (1 << 0)
167
168#ifndef __ASSEMBLY__
169#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
170extern void __iomem *omap_ctrl_base_get(void);
171extern u8 omap_ctrl_readb(u16 offset);
172extern u16 omap_ctrl_readw(u16 offset);
173extern u32 omap_ctrl_readl(u16 offset);
174extern void omap_ctrl_writeb(u8 val, u16 offset);
175extern void omap_ctrl_writew(u16 val, u16 offset);
176extern void omap_ctrl_writel(u32 val, u16 offset);
177#else
178#define omap_ctrl_base_get() 0
179#define omap_ctrl_readb(x) 0
180#define omap_ctrl_readw(x) 0
181#define omap_ctrl_readl(x) 0
182#define omap_ctrl_writeb(x, y) WARN_ON(1)
183#define omap_ctrl_writew(x, y) WARN_ON(1)
184#define omap_ctrl_writel(x, y) WARN_ON(1)
185#endif
186#endif /* __ASSEMBLY__ */
187
188#endif /* __ASM_ARCH_CONTROL_H */
189
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
deleted file mode 100644
index 52db09f83281..000000000000
--- a/include/asm-arm/arch-omap/cpu.h
+++ /dev/null
@@ -1,402 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/cpu.h
3 *
4 * OMAP cpu type detection
5 *
6 * Copyright (C) 2004, 2008 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP_CPU_H
27#define __ASM_ARCH_OMAP_CPU_H
28
29struct omap_chip_id {
30 u8 oc;
31};
32
33#define OMAP_CHIP_INIT(x) { .oc = x }
34
35extern unsigned int system_rev;
36
37#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f)
38
39/*
40 * Test if multicore OMAP support is needed
41 */
42#undef MULTI_OMAP1
43#undef MULTI_OMAP2
44#undef OMAP_NAME
45
46#ifdef CONFIG_ARCH_OMAP730
47# ifdef OMAP_NAME
48# undef MULTI_OMAP1
49# define MULTI_OMAP1
50# else
51# define OMAP_NAME omap730
52# endif
53#endif
54#ifdef CONFIG_ARCH_OMAP15XX
55# ifdef OMAP_NAME
56# undef MULTI_OMAP1
57# define MULTI_OMAP1
58# else
59# define OMAP_NAME omap1510
60# endif
61#endif
62#ifdef CONFIG_ARCH_OMAP16XX
63# ifdef OMAP_NAME
64# undef MULTI_OMAP1
65# define MULTI_OMAP1
66# else
67# define OMAP_NAME omap16xx
68# endif
69#endif
70#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
71# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
72# error "OMAP1 and OMAP2 can't be selected at the same time"
73# endif
74#endif
75#ifdef CONFIG_ARCH_OMAP2420
76# ifdef OMAP_NAME
77# undef MULTI_OMAP2
78# define MULTI_OMAP2
79# else
80# define OMAP_NAME omap2420
81# endif
82#endif
83#ifdef CONFIG_ARCH_OMAP2430
84# ifdef OMAP_NAME
85# undef MULTI_OMAP2
86# define MULTI_OMAP2
87# else
88# define OMAP_NAME omap2430
89# endif
90#endif
91#ifdef CONFIG_ARCH_OMAP3430
92# ifdef OMAP_NAME
93# undef MULTI_OMAP2
94# define MULTI_OMAP2
95# else
96# define OMAP_NAME omap3430
97# endif
98#endif
99
100/*
101 * Macros to group OMAP into cpu classes.
102 * These can be used in most places.
103 * cpu_is_omap7xx(): True for OMAP730
104 * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
105 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
106 * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
107 * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
108 * cpu_is_omap243x(): True for OMAP2430
109 * cpu_is_omap343x(): True for OMAP3430
110 */
111#define GET_OMAP_CLASS ((system_rev >> 24) & 0xff)
112
113#define IS_OMAP_CLASS(class, id) \
114static inline int is_omap ##class (void) \
115{ \
116 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
117}
118
119#define GET_OMAP_SUBCLASS ((system_rev >> 20) & 0x0fff)
120
121#define IS_OMAP_SUBCLASS(subclass, id) \
122static inline int is_omap ##subclass (void) \
123{ \
124 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
125}
126
127IS_OMAP_CLASS(7xx, 0x07)
128IS_OMAP_CLASS(15xx, 0x15)
129IS_OMAP_CLASS(16xx, 0x16)
130IS_OMAP_CLASS(24xx, 0x24)
131IS_OMAP_CLASS(34xx, 0x34)
132
133IS_OMAP_SUBCLASS(242x, 0x242)
134IS_OMAP_SUBCLASS(243x, 0x243)
135IS_OMAP_SUBCLASS(343x, 0x343)
136
137#define cpu_is_omap7xx() 0
138#define cpu_is_omap15xx() 0
139#define cpu_is_omap16xx() 0
140#define cpu_is_omap24xx() 0
141#define cpu_is_omap242x() 0
142#define cpu_is_omap243x() 0
143#define cpu_is_omap34xx() 0
144#define cpu_is_omap343x() 0
145
146#if defined(MULTI_OMAP1)
147# if defined(CONFIG_ARCH_OMAP730)
148# undef cpu_is_omap7xx
149# define cpu_is_omap7xx() is_omap7xx()
150# endif
151# if defined(CONFIG_ARCH_OMAP15XX)
152# undef cpu_is_omap15xx
153# define cpu_is_omap15xx() is_omap15xx()
154# endif
155# if defined(CONFIG_ARCH_OMAP16XX)
156# undef cpu_is_omap16xx
157# define cpu_is_omap16xx() is_omap16xx()
158# endif
159#else
160# if defined(CONFIG_ARCH_OMAP730)
161# undef cpu_is_omap7xx
162# define cpu_is_omap7xx() 1
163# endif
164# if defined(CONFIG_ARCH_OMAP15XX)
165# undef cpu_is_omap15xx
166# define cpu_is_omap15xx() 1
167# endif
168# if defined(CONFIG_ARCH_OMAP16XX)
169# undef cpu_is_omap16xx
170# define cpu_is_omap16xx() 1
171# endif
172#endif
173
174#if defined(MULTI_OMAP2)
175# if defined(CONFIG_ARCH_OMAP24XX)
176# undef cpu_is_omap24xx
177# undef cpu_is_omap242x
178# undef cpu_is_omap243x
179# define cpu_is_omap24xx() is_omap24xx()
180# define cpu_is_omap242x() is_omap242x()
181# define cpu_is_omap243x() is_omap243x()
182# endif
183# if defined(CONFIG_ARCH_OMAP34XX)
184# undef cpu_is_omap34xx
185# undef cpu_is_omap343x
186# define cpu_is_omap34xx() is_omap34xx()
187# define cpu_is_omap343x() is_omap343x()
188# endif
189#else
190# if defined(CONFIG_ARCH_OMAP24XX)
191# undef cpu_is_omap24xx
192# define cpu_is_omap24xx() 1
193# endif
194# if defined(CONFIG_ARCH_OMAP2420)
195# undef cpu_is_omap242x
196# define cpu_is_omap242x() 1
197# endif
198# if defined(CONFIG_ARCH_OMAP2430)
199# undef cpu_is_omap243x
200# define cpu_is_omap243x() 1
201# endif
202# if defined(CONFIG_ARCH_OMAP34XX)
203# undef cpu_is_omap34xx
204# define cpu_is_omap34xx() 1
205# endif
206# if defined(CONFIG_ARCH_OMAP3430)
207# undef cpu_is_omap343x
208# define cpu_is_omap343x() 1
209# endif
210#endif
211
212/*
213 * Macros to detect individual cpu types.
214 * These are only rarely needed.
215 * cpu_is_omap330(): True for OMAP330
216 * cpu_is_omap730(): True for OMAP730
217 * cpu_is_omap1510(): True for OMAP1510
218 * cpu_is_omap1610(): True for OMAP1610
219 * cpu_is_omap1611(): True for OMAP1611
220 * cpu_is_omap5912(): True for OMAP5912
221 * cpu_is_omap1621(): True for OMAP1621
222 * cpu_is_omap1710(): True for OMAP1710
223 * cpu_is_omap2420(): True for OMAP2420
224 * cpu_is_omap2422(): True for OMAP2422
225 * cpu_is_omap2423(): True for OMAP2423
226 * cpu_is_omap2430(): True for OMAP2430
227 * cpu_is_omap3430(): True for OMAP3430
228 */
229#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff)
230
231#define IS_OMAP_TYPE(type, id) \
232static inline int is_omap ##type (void) \
233{ \
234 return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
235}
236
237IS_OMAP_TYPE(310, 0x0310)
238IS_OMAP_TYPE(730, 0x0730)
239IS_OMAP_TYPE(1510, 0x1510)
240IS_OMAP_TYPE(1610, 0x1610)
241IS_OMAP_TYPE(1611, 0x1611)
242IS_OMAP_TYPE(5912, 0x1611)
243IS_OMAP_TYPE(1621, 0x1621)
244IS_OMAP_TYPE(1710, 0x1710)
245IS_OMAP_TYPE(2420, 0x2420)
246IS_OMAP_TYPE(2422, 0x2422)
247IS_OMAP_TYPE(2423, 0x2423)
248IS_OMAP_TYPE(2430, 0x2430)
249IS_OMAP_TYPE(3430, 0x3430)
250
251#define cpu_is_omap310() 0
252#define cpu_is_omap730() 0
253#define cpu_is_omap1510() 0
254#define cpu_is_omap1610() 0
255#define cpu_is_omap5912() 0
256#define cpu_is_omap1611() 0
257#define cpu_is_omap1621() 0
258#define cpu_is_omap1710() 0
259#define cpu_is_omap2420() 0
260#define cpu_is_omap2422() 0
261#define cpu_is_omap2423() 0
262#define cpu_is_omap2430() 0
263#define cpu_is_omap3430() 0
264
265#if defined(MULTI_OMAP1)
266# if defined(CONFIG_ARCH_OMAP730)
267# undef cpu_is_omap730
268# define cpu_is_omap730() is_omap730()
269# endif
270#else
271# if defined(CONFIG_ARCH_OMAP730)
272# undef cpu_is_omap730
273# define cpu_is_omap730() 1
274# endif
275#endif
276
277/*
278 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
279 * between 330 vs. 1510 and 1611B/5912 vs. 1710.
280 */
281#if defined(CONFIG_ARCH_OMAP15XX)
282# undef cpu_is_omap310
283# undef cpu_is_omap1510
284# define cpu_is_omap310() is_omap310()
285# define cpu_is_omap1510() is_omap1510()
286#endif
287
288#if defined(CONFIG_ARCH_OMAP16XX)
289# undef cpu_is_omap1610
290# undef cpu_is_omap1611
291# undef cpu_is_omap5912
292# undef cpu_is_omap1621
293# undef cpu_is_omap1710
294# define cpu_is_omap1610() is_omap1610()
295# define cpu_is_omap1611() is_omap1611()
296# define cpu_is_omap5912() is_omap5912()
297# define cpu_is_omap1621() is_omap1621()
298# define cpu_is_omap1710() is_omap1710()
299#endif
300
301#if defined(CONFIG_ARCH_OMAP24XX)
302# undef cpu_is_omap2420
303# undef cpu_is_omap2422
304# undef cpu_is_omap2423
305# undef cpu_is_omap2430
306# define cpu_is_omap2420() is_omap2420()
307# define cpu_is_omap2422() is_omap2422()
308# define cpu_is_omap2423() is_omap2423()
309# define cpu_is_omap2430() is_omap2430()
310#endif
311
312#if defined(CONFIG_ARCH_OMAP34XX)
313# undef cpu_is_omap3430
314# define cpu_is_omap3430() is_omap3430()
315#endif
316
317/* Macros to detect if we have OMAP1 or OMAP2 */
318#define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \
319 cpu_is_omap16xx())
320#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx())
321
322#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
323/*
324 * Macros to detect silicon revision of OMAP2/3 processors.
325 * is_sil_rev_greater_than: true if passed cpu type & its rev is greater.
326 * is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser.
327 * is_sil_rev_equal_to: true if passed cpu type & its rev is equal.
328 * get_sil_rev: return the silicon rev value.
329 */
330#define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16)
331#define get_sil_revision(rev) ((rev & 0x0000f000) >> 12)
332
333#define is_sil_rev_greater_than(rev) \
334 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
335 (get_sil_revision(system_rev) > get_sil_revision(rev)))
336
337#define is_sil_rev_less_than(rev) \
338 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
339 (get_sil_revision(system_rev) < get_sil_revision(rev)))
340
341#define is_sil_rev_equal_to(rev) \
342 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
343 (get_sil_revision(system_rev) == get_sil_revision(rev)))
344
345#define get_sil_rev() \
346 get_sil_revision(system_rev)
347
348/* Various silicon macros defined here */
349#define OMAP2420_REV_ES1_0 0x24200000
350#define OMAP2420_REV_ES2_0 0x24201000
351#define OMAP2430_REV_ES1_0 0x24300000
352#define OMAP3430_REV_ES1_0 0x34300000
353#define OMAP3430_REV_ES2_0 0x34301000
354#define OMAP3430_REV_ES2_1 0x34302000
355#define OMAP3430_REV_ES2_2 0x34303000
356
357/*
358 * omap_chip bits
359 *
360 * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
361 * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
362 * something that is only valid on that particular ES revision.
363 *
364 * These bits may be ORed together to indicate structures that are
365 * available on multiple chip types.
366 *
367 * To test whether a particular structure matches the current OMAP chip type,
368 * use omap_chip_is().
369 *
370 */
371#define CHIP_IS_OMAP2420 (1 << 0)
372#define CHIP_IS_OMAP2430 (1 << 1)
373#define CHIP_IS_OMAP3430 (1 << 2)
374#define CHIP_IS_OMAP3430ES1 (1 << 3)
375#define CHIP_IS_OMAP3430ES2 (1 << 4)
376
377#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
378
379int omap_chip_is(struct omap_chip_id oci);
380
381
382/*
383 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
384 */
385#define DEVICE_TYPE_TEST 0
386#define DEVICE_TYPE_EMU 1
387#define DEVICE_TYPE_SEC 2
388#define DEVICE_TYPE_GP 3
389#define DEVICE_TYPE_BAD 4
390
391#define get_device_type() ((system_rev & 0x700) >> 8)
392#define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST)
393#define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU)
394#define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC)
395#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
396#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
397
398void omap2_check_revision(void);
399
400#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
401
402#endif
diff --git a/include/asm-arm/arch-omap/debug-macro.S b/include/asm-arm/arch-omap/debug-macro.S
deleted file mode 100644
index ca4f577f9675..000000000000
--- a/include/asm-arm/arch-omap/debug-macro.S
+++ /dev/null
@@ -1,58 +0,0 @@
1/* linux/include/asm-arm/arch-omap/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17#ifdef CONFIG_ARCH_OMAP1
18 moveq \rx, #0xff000000 @ physical base address
19 movne \rx, #0xfe000000 @ virtual base
20 orr \rx, \rx, #0x00fb0000
21#ifdef CONFIG_OMAP_LL_DEBUG_UART3
22 orr \rx, \rx, #0x00009000 @ UART 3
23#endif
24#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
25 orr \rx, \rx, #0x00000800 @ UART 2 & 3
26#endif
27
28#elif CONFIG_ARCH_OMAP2
29 moveq \rx, #0x48000000 @ physical base address
30 movne \rx, #0xd8000000 @ virtual base
31 orr \rx, \rx, #0x0006a000
32#ifdef CONFIG_OMAP_LL_DEBUG_UART2
33 add \rx, \rx, #0x00002000 @ UART 2
34#endif
35#ifdef CONFIG_OMAP_LL_DEBUG_UART3
36 add \rx, \rx, #0x00004000 @ UART 3
37#endif
38#endif
39 .endm
40
41 .macro senduart,rd,rx
42 strb \rd, [\rx]
43 .endm
44
45 .macro busyuart,rd,rx
461001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
47 and \rd, \rd, #0x60
48 teq \rd, #0x60
49 beq 1002f
50 ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
51 and \rd, \rd, #0x60
52 teq \rd, #0x60
53 bne 1001b
541002:
55 .endm
56
57 .macro waituart,rd,rx
58 .endm
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
deleted file mode 100644
index f4dcb9587869..000000000000
--- a/include/asm-arm/arch-omap/dma.h
+++ /dev/null
@@ -1,570 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/dma.h
3 *
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24/* Hardware registers for omap1 */
25#define OMAP1_DMA_BASE (0xfffed800)
26
27#define OMAP1_DMA_GCR 0x400
28#define OMAP1_DMA_GSCR 0x404
29#define OMAP1_DMA_GRST 0x408
30#define OMAP1_DMA_HW_ID 0x442
31#define OMAP1_DMA_PCH2_ID 0x444
32#define OMAP1_DMA_PCH0_ID 0x446
33#define OMAP1_DMA_PCH1_ID 0x448
34#define OMAP1_DMA_PCHG_ID 0x44a
35#define OMAP1_DMA_PCHD_ID 0x44c
36#define OMAP1_DMA_CAPS_0_U 0x44e
37#define OMAP1_DMA_CAPS_0_L 0x450
38#define OMAP1_DMA_CAPS_1_U 0x452
39#define OMAP1_DMA_CAPS_1_L 0x454
40#define OMAP1_DMA_CAPS_2 0x456
41#define OMAP1_DMA_CAPS_3 0x458
42#define OMAP1_DMA_CAPS_4 0x45a
43#define OMAP1_DMA_PCH2_SR 0x460
44#define OMAP1_DMA_PCH0_SR 0x480
45#define OMAP1_DMA_PCH1_SR 0x482
46#define OMAP1_DMA_PCHD_SR 0x4c0
47
48/* Hardware registers for omap2 and omap3 */
49#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
50#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
51
52#define OMAP_DMA4_REVISION 0x00
53#define OMAP_DMA4_GCR 0x78
54#define OMAP_DMA4_IRQSTATUS_L0 0x08
55#define OMAP_DMA4_IRQSTATUS_L1 0x0c
56#define OMAP_DMA4_IRQSTATUS_L2 0x10
57#define OMAP_DMA4_IRQSTATUS_L3 0x14
58#define OMAP_DMA4_IRQENABLE_L0 0x18
59#define OMAP_DMA4_IRQENABLE_L1 0x1c
60#define OMAP_DMA4_IRQENABLE_L2 0x20
61#define OMAP_DMA4_IRQENABLE_L3 0x24
62#define OMAP_DMA4_SYSSTATUS 0x28
63#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
64#define OMAP_DMA4_CAPS_0 0x64
65#define OMAP_DMA4_CAPS_2 0x6c
66#define OMAP_DMA4_CAPS_3 0x70
67#define OMAP_DMA4_CAPS_4 0x74
68
69#define OMAP1_LOGICAL_DMA_CH_COUNT 17
70#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
71
72/* Common channel specific registers for omap1 */
73#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
74#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
75#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
76#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
77#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
78#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
79#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
80#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
81#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
82#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
83#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
84#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
85#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
86#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
87#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
88
89/* Common channel specific registers for omap2 */
90#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
91#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
92#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
93#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
94#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
95#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
96#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
97#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
98#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
99#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
100#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
101#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
102#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
103#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
104
105/* Channel specific registers only on omap1 */
106#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
107#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
108#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
109#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
110#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
111#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
112#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
113#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
114#define OMAP1_DMA_CCEN(n) 0
115#define OMAP1_DMA_CCFN(n) 0
116
117/* Channel specific registers only on omap2 */
118#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
119#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
120#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
121#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
122#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
123
124/* Dummy defines to keep multi-omap compiles happy */
125#define OMAP1_DMA_REVISION 0
126#define OMAP1_DMA_IRQSTATUS_L0 0
127#define OMAP1_DMA_IRQENABLE_L0 0
128#define OMAP1_DMA_OCP_SYSCONFIG 0
129#define OMAP_DMA4_HW_ID 0
130#define OMAP_DMA4_CAPS_0_L 0
131#define OMAP_DMA4_CAPS_0_U 0
132#define OMAP_DMA4_CAPS_1_L 0
133#define OMAP_DMA4_CAPS_1_U 0
134#define OMAP_DMA4_GSCR 0
135#define OMAP_DMA4_CPC(n) 0
136
137#define OMAP_DMA4_LCH_CTRL(n) 0
138#define OMAP_DMA4_COLOR_L(n) 0
139#define OMAP_DMA4_COLOR_U(n) 0
140#define OMAP_DMA4_CCR2(n) 0
141#define OMAP1_DMA_CSSA(n) 0
142#define OMAP1_DMA_CDSA(n) 0
143#define OMAP_DMA4_CSSA_L(n) 0
144#define OMAP_DMA4_CSSA_U(n) 0
145#define OMAP_DMA4_CDSA_L(n) 0
146#define OMAP_DMA4_CDSA_U(n) 0
147
148/*----------------------------------------------------------------------------*/
149
150/* DMA channels for omap1 */
151#define OMAP_DMA_NO_DEVICE 0
152#define OMAP_DMA_MCSI1_TX 1
153#define OMAP_DMA_MCSI1_RX 2
154#define OMAP_DMA_I2C_RX 3
155#define OMAP_DMA_I2C_TX 4
156#define OMAP_DMA_EXT_NDMA_REQ 5
157#define OMAP_DMA_EXT_NDMA_REQ2 6
158#define OMAP_DMA_UWIRE_TX 7
159#define OMAP_DMA_MCBSP1_TX 8
160#define OMAP_DMA_MCBSP1_RX 9
161#define OMAP_DMA_MCBSP3_TX 10
162#define OMAP_DMA_MCBSP3_RX 11
163#define OMAP_DMA_UART1_TX 12
164#define OMAP_DMA_UART1_RX 13
165#define OMAP_DMA_UART2_TX 14
166#define OMAP_DMA_UART2_RX 15
167#define OMAP_DMA_MCBSP2_TX 16
168#define OMAP_DMA_MCBSP2_RX 17
169#define OMAP_DMA_UART3_TX 18
170#define OMAP_DMA_UART3_RX 19
171#define OMAP_DMA_CAMERA_IF_RX 20
172#define OMAP_DMA_MMC_TX 21
173#define OMAP_DMA_MMC_RX 22
174#define OMAP_DMA_NAND 23
175#define OMAP_DMA_IRQ_LCD_LINE 24
176#define OMAP_DMA_MEMORY_STICK 25
177#define OMAP_DMA_USB_W2FC_RX0 26
178#define OMAP_DMA_USB_W2FC_RX1 27
179#define OMAP_DMA_USB_W2FC_RX2 28
180#define OMAP_DMA_USB_W2FC_TX0 29
181#define OMAP_DMA_USB_W2FC_TX1 30
182#define OMAP_DMA_USB_W2FC_TX2 31
183
184/* These are only for 1610 */
185#define OMAP_DMA_CRYPTO_DES_IN 32
186#define OMAP_DMA_SPI_TX 33
187#define OMAP_DMA_SPI_RX 34
188#define OMAP_DMA_CRYPTO_HASH 35
189#define OMAP_DMA_CCP_ATTN 36
190#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
191#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
192#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
193#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
194#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
195#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
196#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
197#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
198#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
199#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
200#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
201#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
202#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
203#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
204#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
205#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
206#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
207#define OMAP_DMA_MMC2_TX 54
208#define OMAP_DMA_MMC2_RX 55
209#define OMAP_DMA_CRYPTO_DES_OUT 56
210
211/* DMA channels for 24xx */
212#define OMAP24XX_DMA_NO_DEVICE 0
213#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
214#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
215#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
216#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
217#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
218#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
219#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
220#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
221#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
222#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
223#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
224#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
225#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
226#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
227#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
228#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
229#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
230#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
231#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
232#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
233#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
234#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
235#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
236#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
237#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
238#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
239#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
240#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
241#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
242#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
243#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
244#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
245#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
246#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
247#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
248#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
249#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
250#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
251#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
252#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
253#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
254#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
255#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
256#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
257#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
258#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
259#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
260#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
261#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
262#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
263#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
264#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
265#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
266#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
267#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
268#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
269#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
270#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
271#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
272#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
273#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
274#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
275#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
276#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
277#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
278#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
279#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
280#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
281#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
282#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
283#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
284#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
285#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
286#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
287#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
288#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
289#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
290#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
291#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
292#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
293#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
294#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
295#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
296#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
297#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
298#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
299#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
300#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
301#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
302#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
303#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
304#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
305#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
306#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
307#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
308#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
309#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
310#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
311
312/*----------------------------------------------------------------------------*/
313
314/* Hardware registers for LCD DMA */
315#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
316#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
317#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
318#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
319#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
320#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
321
322#define OMAP1610_DMA_LCD_BASE (0xfffee300)
323#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
324#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
325#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
326#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
327#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
328#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
329#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
330#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
331#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
332#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
333#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
334#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
335#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
336#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
337#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
338#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
339#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
340
341#define OMAP1_DMA_TOUT_IRQ (1 << 0)
342#define OMAP_DMA_DROP_IRQ (1 << 1)
343#define OMAP_DMA_HALF_IRQ (1 << 2)
344#define OMAP_DMA_FRAME_IRQ (1 << 3)
345#define OMAP_DMA_LAST_IRQ (1 << 4)
346#define OMAP_DMA_BLOCK_IRQ (1 << 5)
347#define OMAP1_DMA_SYNC_IRQ (1 << 6)
348#define OMAP2_DMA_PKT_IRQ (1 << 7)
349#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
350#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
351#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
352#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
353
354#define OMAP_DMA_DATA_TYPE_S8 0x00
355#define OMAP_DMA_DATA_TYPE_S16 0x01
356#define OMAP_DMA_DATA_TYPE_S32 0x02
357
358#define OMAP_DMA_SYNC_ELEMENT 0x00
359#define OMAP_DMA_SYNC_FRAME 0x01
360#define OMAP_DMA_SYNC_BLOCK 0x02
361#define OMAP_DMA_SYNC_PACKET 0x03
362
363#define OMAP_DMA_SRC_SYNC 0x01
364#define OMAP_DMA_DST_SYNC 0x00
365
366#define OMAP_DMA_PORT_EMIFF 0x00
367#define OMAP_DMA_PORT_EMIFS 0x01
368#define OMAP_DMA_PORT_OCP_T1 0x02
369#define OMAP_DMA_PORT_TIPB 0x03
370#define OMAP_DMA_PORT_OCP_T2 0x04
371#define OMAP_DMA_PORT_MPUI 0x05
372
373#define OMAP_DMA_AMODE_CONSTANT 0x00
374#define OMAP_DMA_AMODE_POST_INC 0x01
375#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
376#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
377
378#define DMA_DEFAULT_FIFO_DEPTH 0x10
379#define DMA_DEFAULT_ARB_RATE 0x01
380/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
381#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
382#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
383#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
384#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
385#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
386#define DMA_THREAD_FIFO_75 (0x01 << 14)
387#define DMA_THREAD_FIFO_25 (0x02 << 14)
388#define DMA_THREAD_FIFO_50 (0x03 << 14)
389
390/* Chaining modes*/
391#ifndef CONFIG_ARCH_OMAP1
392#define OMAP_DMA_STATIC_CHAIN 0x1
393#define OMAP_DMA_DYNAMIC_CHAIN 0x2
394#define OMAP_DMA_CHAIN_ACTIVE 0x1
395#define OMAP_DMA_CHAIN_INACTIVE 0x0
396#endif
397
398#define DMA_CH_PRIO_HIGH 0x1
399#define DMA_CH_PRIO_LOW 0x0 /* Def */
400
401/* LCD DMA block numbers */
402enum {
403 OMAP_LCD_DMA_B1_TOP,
404 OMAP_LCD_DMA_B1_BOTTOM,
405 OMAP_LCD_DMA_B2_TOP,
406 OMAP_LCD_DMA_B2_BOTTOM
407};
408
409enum omap_dma_burst_mode {
410 OMAP_DMA_DATA_BURST_DIS = 0,
411 OMAP_DMA_DATA_BURST_4,
412 OMAP_DMA_DATA_BURST_8,
413 OMAP_DMA_DATA_BURST_16,
414};
415
416enum end_type {
417 OMAP_DMA_LITTLE_ENDIAN = 0,
418 OMAP_DMA_BIG_ENDIAN
419};
420
421enum omap_dma_color_mode {
422 OMAP_DMA_COLOR_DIS = 0,
423 OMAP_DMA_CONSTANT_FILL,
424 OMAP_DMA_TRANSPARENT_COPY
425};
426
427enum omap_dma_write_mode {
428 OMAP_DMA_WRITE_NON_POSTED = 0,
429 OMAP_DMA_WRITE_POSTED,
430 OMAP_DMA_WRITE_LAST_NON_POSTED
431};
432
433enum omap_dma_channel_mode {
434 OMAP_DMA_LCH_2D = 0,
435 OMAP_DMA_LCH_G,
436 OMAP_DMA_LCH_P,
437 OMAP_DMA_LCH_PD
438};
439
440struct omap_dma_channel_params {
441 int data_type; /* data type 8,16,32 */
442 int elem_count; /* number of elements in a frame */
443 int frame_count; /* number of frames in a element */
444
445 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
446 int src_amode; /* constant, post increment, indexed,
447 double indexed */
448 unsigned long src_start; /* source address : physical */
449 int src_ei; /* source element index */
450 int src_fi; /* source frame index */
451
452 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
453 int dst_amode; /* constant, post increment, indexed,
454 double indexed */
455 unsigned long dst_start; /* source address : physical */
456 int dst_ei; /* source element index */
457 int dst_fi; /* source frame index */
458
459 int trigger; /* trigger attached if the channel is
460 synchronized */
461 int sync_mode; /* sycn on element, frame , block or packet */
462 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
463
464 int ie; /* interrupt enabled */
465
466 unsigned char read_prio;/* read priority */
467 unsigned char write_prio;/* write priority */
468
469#ifndef CONFIG_ARCH_OMAP1
470 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
471#endif
472};
473
474
475extern void omap_set_dma_priority(int lch, int dst_port, int priority);
476extern int omap_request_dma(int dev_id, const char *dev_name,
477 void (*callback)(int lch, u16 ch_status, void *data),
478 void *data, int *dma_ch);
479extern void omap_enable_dma_irq(int ch, u16 irq_bits);
480extern void omap_disable_dma_irq(int ch, u16 irq_bits);
481extern void omap_free_dma(int ch);
482extern void omap_start_dma(int lch);
483extern void omap_stop_dma(int lch);
484extern void omap_set_dma_transfer_params(int lch, int data_type,
485 int elem_count, int frame_count,
486 int sync_mode,
487 int dma_trigger, int src_or_dst_synch);
488extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
489 u32 color);
490extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
491extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
492
493extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
494 unsigned long src_start,
495 int src_ei, int src_fi);
496extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
497extern void omap_set_dma_src_data_pack(int lch, int enable);
498extern void omap_set_dma_src_burst_mode(int lch,
499 enum omap_dma_burst_mode burst_mode);
500
501extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
502 unsigned long dest_start,
503 int dst_ei, int dst_fi);
504extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
505extern void omap_set_dma_dest_data_pack(int lch, int enable);
506extern void omap_set_dma_dest_burst_mode(int lch,
507 enum omap_dma_burst_mode burst_mode);
508
509extern void omap_set_dma_params(int lch,
510 struct omap_dma_channel_params *params);
511
512extern void omap_dma_link_lch(int lch_head, int lch_queue);
513extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
514
515extern int omap_set_dma_callback(int lch,
516 void (*callback)(int lch, u16 ch_status, void *data),
517 void *data);
518extern dma_addr_t omap_get_dma_src_pos(int lch);
519extern dma_addr_t omap_get_dma_dst_pos(int lch);
520extern void omap_clear_dma(int lch);
521extern int omap_get_dma_active_status(int lch);
522extern int omap_dma_running(void);
523extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
524 int tparams);
525extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
526 unsigned char write_prio);
527extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
528extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
529extern int omap_get_dma_index(int lch, int *ei, int *fi);
530
531/* Chaining APIs */
532#ifndef CONFIG_ARCH_OMAP1
533extern int omap_request_dma_chain(int dev_id, const char *dev_name,
534 void (*callback) (int chain_id, u16 ch_status,
535 void *data),
536 int *chain_id, int no_of_chans,
537 int chain_mode,
538 struct omap_dma_channel_params params);
539extern int omap_free_dma_chain(int chain_id);
540extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
541 int dest_start, int elem_count,
542 int frame_count, void *callbk_data);
543extern int omap_start_dma_chain_transfers(int chain_id);
544extern int omap_stop_dma_chain_transfers(int chain_id);
545extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
546extern int omap_get_dma_chain_dst_pos(int chain_id);
547extern int omap_get_dma_chain_src_pos(int chain_id);
548
549extern int omap_modify_dma_chain_params(int chain_id,
550 struct omap_dma_channel_params params);
551extern int omap_dma_chain_status(int chain_id);
552#endif
553
554/* LCD DMA functions */
555extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
556 void *data);
557extern void omap_free_lcd_dma(void);
558extern void omap_setup_lcd_dma(void);
559extern void omap_enable_lcd_dma(void);
560extern void omap_stop_lcd_dma(void);
561extern void omap_set_lcd_dma_ext_controller(int external);
562extern void omap_set_lcd_dma_single_transfer(int single);
563extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
564 int data_type);
565extern void omap_set_lcd_dma_b1_rotation(int rotate);
566extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
567extern void omap_set_lcd_dma_b1_mirror(int mirror);
568extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
569
570#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
deleted file mode 100644
index 02b29e8437ae..000000000000
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/dmtimer.h
3 *
4 * OMAP Dual-Mode Timers
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
8 * PWM and clock framwork support by Timo Teras.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_DMTIMER_H
30#define __ASM_ARCH_DMTIMER_H
31
32/* clock sources */
33#define OMAP_TIMER_SRC_SYS_CLK 0x00
34#define OMAP_TIMER_SRC_32_KHZ 0x01
35#define OMAP_TIMER_SRC_EXT_CLK 0x02
36
37/* timer interrupt enable bits */
38#define OMAP_TIMER_INT_CAPTURE (1 << 2)
39#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
40#define OMAP_TIMER_INT_MATCH (1 << 0)
41
42/* trigger types */
43#define OMAP_TIMER_TRIGGER_NONE 0x00
44#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
45#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
46
47struct omap_dm_timer;
48struct clk;
49
50int omap_dm_timer_init(void);
51
52struct omap_dm_timer *omap_dm_timer_request(void);
53struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
54void omap_dm_timer_free(struct omap_dm_timer *timer);
55void omap_dm_timer_enable(struct omap_dm_timer *timer);
56void omap_dm_timer_disable(struct omap_dm_timer *timer);
57
58int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
59
60u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
61struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
62
63void omap_dm_timer_trigger(struct omap_dm_timer *timer);
64void omap_dm_timer_start(struct omap_dm_timer *timer);
65void omap_dm_timer_stop(struct omap_dm_timer *timer);
66
67void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
69void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
70void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
71void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
72void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
73
74void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
75
76unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
77void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
78unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
79void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
80
81int omap_dm_timers_active(void);
82
83
84#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/include/asm-arm/arch-omap/dsp_common.h b/include/asm-arm/arch-omap/dsp_common.h
deleted file mode 100644
index da97736f3efa..000000000000
--- a/include/asm-arm/arch-omap/dsp_common.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
3 *
4 * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
5 *
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#ifndef ASM_ARCH_DSP_COMMON_H
25#define ASM_ARCH_DSP_COMMON_H
26
27#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
28extern void omap_dsp_request_mpui(void);
29extern void omap_dsp_release_mpui(void);
30extern int omap_dsp_request_mem(void);
31extern int omap_dsp_release_mem(void);
32#else
33static inline int omap_dsp_request_mem(void)
34{
35 return 0;
36}
37#define omap_dsp_release_mem() do {} while (0)
38#endif
39
40#endif /* ASM_ARCH_DSP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/eac.h b/include/asm-arm/arch-omap/eac.h
deleted file mode 100644
index ccee3b0700b3..000000000000
--- a/include/asm-arm/arch-omap/eac.h
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap2/eac.h
3 *
4 * Defines for Enhanced Audio Controller
5 *
6 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
7 *
8 * Copyright (C) 2006 Nokia Corporation
9 * Copyright (C) 2004 Texas Instruments, Inc.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 */
26
27#ifndef __ASM_ARM_ARCH_OMAP2_EAC_H
28#define __ASM_ARM_ARCH_OMAP2_EAC_H
29
30#include <asm/arch/io.h>
31#include <asm/arch/hardware.h>
32#include <asm/irq.h>
33
34#include <sound/core.h>
35
36/* master codec clock source */
37#define EAC_MCLK_EXT_MASK 0x100
38enum eac_mclk_src {
39 EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */
40 EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK,
41 EAC_MCLK_EXT_12288000,
42 EAC_MCLK_EXT_2x11289600,
43 EAC_MCLK_EXT_2x12288000,
44};
45
46/* codec port interface mode */
47enum eac_codec_mode {
48 EAC_CODEC_PCM,
49 EAC_CODEC_AC97,
50 EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */
51 EAC_CODEC_I2S_SLAVE,
52};
53
54/* configuration structure for I2S mode */
55struct eac_i2s_conf {
56 /* if enabled, then first data slot (left channel) is signaled as
57 * positive level of frame sync EAC.AC_FS */
58 unsigned polarity_changed_mode:1;
59 /* if enabled, then serial data starts one clock cycle after the
60 * of EAC.AC_FS for first audio slot */
61 unsigned sync_delay_enable:1;
62};
63
64/* configuration structure for EAC codec port */
65struct eac_codec {
66 enum eac_mclk_src mclk_src;
67
68 enum eac_codec_mode codec_mode;
69 union {
70 struct eac_i2s_conf i2s;
71 } codec_conf;
72
73 int default_rate; /* audio sampling rate */
74
75 int (* set_power)(void *private_data, int dac, int adc);
76 int (* register_controls)(void *private_data,
77 struct snd_card *card);
78 const char *short_name;
79
80 void *private_data;
81};
82
83/* structure for passing platform dependent data to the EAC driver */
84struct eac_platform_data {
85 int (* init)(struct device *eac_dev);
86 void (* cleanup)(struct device *eac_dev);
87 /* these callbacks are used to configure & control external MCLK
88 * source. NULL if not used */
89 int (* enable_ext_clocks)(struct device *eac_dev);
90 void (* disable_ext_clocks)(struct device *eac_dev);
91};
92
93extern void omap_init_eac(struct eac_platform_data *pdata);
94
95extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec);
96extern void eac_unregister_codec(struct device *eac_dev);
97
98extern int eac_set_mode(struct device *eac_dev, int play, int rec);
99
100#endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
deleted file mode 100644
index 67ed7839e782..000000000000
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * include/asm-arm/arch-omap/entry-macro.S
3 *
4 * Low-level IRQ helper macros for OMAP-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <asm/arch/hardware.h>
11#include <asm/arch/io.h>
12#include <asm/arch/irqs.h>
13
14#if defined(CONFIG_ARCH_OMAP1)
15
16#if defined(CONFIG_ARCH_OMAP730) && \
17 (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
18#error "FIXME: OMAP730 doesn't support multiple-OMAP"
19#elif defined(CONFIG_ARCH_OMAP730)
20#define INT_IH2_IRQ INT_730_IH2_IRQ
21#elif defined(CONFIG_ARCH_OMAP15XX)
22#define INT_IH2_IRQ INT_1510_IH2_IRQ
23#elif defined(CONFIG_ARCH_OMAP16XX)
24#define INT_IH2_IRQ INT_1610_IH2_IRQ
25#else
26#warning "IH2 IRQ defaulted"
27#define INT_IH2_IRQ INT_1510_IH2_IRQ
28#endif
29
30 .macro disable_fiq
31 .endm
32
33 .macro get_irqnr_preamble, base, tmp
34 .endm
35
36 .macro arch_ret_to_user, tmp1, tmp2
37 .endm
38
39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
40 ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
41 ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
42 ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
43 mov \irqstat, #0xffffffff
44 bic \tmp, \irqstat, \tmp
45 tst \irqnr, \tmp
46 beq 1510f
47
48 ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
49 cmp \irqnr, #0
50 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
51 cmpeq \irqnr, #INT_IH2_IRQ
52 ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE)
53 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
54 addeqs \irqnr, \irqnr, #32
551510:
56 .endm
57
58#elif defined(CONFIG_ARCH_OMAP24XX)
59
60#include <asm/arch/omap24xx.h>
61
62 .macro disable_fiq
63 .endm
64
65 .macro get_irqnr_preamble, base, tmp
66 .endm
67
68 .macro arch_ret_to_user, tmp1, tmp2
69 .endm
70
71 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
72 ldr \base, =OMAP2_VA_IC_BASE
73 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
74 cmp \irqnr, #0x0
75 bne 2222f
76 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
77 cmp \irqnr, #0x0
78 bne 2222f
79 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
80 cmp \irqnr, #0x0
812222:
82 ldrne \irqnr, [\base, #IRQ_SIR_IRQ]
83
84 .endm
85
86 .macro irq_prio_table
87 .endm
88
89#endif
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
deleted file mode 100644
index f420881d2a3b..000000000000
--- a/include/asm-arm/arch-omap/fpga.h
+++ /dev/null
@@ -1,197 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/fpga.h
3 *
4 * Interrupt handler for OMAP-1510 FPGA
5 *
6 * Copyright (C) 2001 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * Copyright (C) 2002 MontaVista Software, Inc.
10 *
11 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
12 * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ASM_ARCH_OMAP_FPGA_H
20#define __ASM_ARCH_OMAP_FPGA_H
21
22#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
23extern void omap1510_fpga_init_irq(void);
24#else
25#define omap1510_fpga_init_irq() (0)
26#endif
27
28#define fpga_read(reg) __raw_readb(reg)
29#define fpga_write(val, reg) __raw_writeb(val, reg)
30
31/*
32 * ---------------------------------------------------------------------------
33 * H2/P2 Debug board FPGA
34 * ---------------------------------------------------------------------------
35 */
36/* maps in the FPGA registers and the ETHR registers */
37#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
40
41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
43#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
44#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
45#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
46#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
47#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
48#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
49
50/* NOTE: most boards don't have a static mapping for the FPGA ... */
51struct h2p2_dbg_fpga {
52 /* offset 0x00 */
53 u16 smc91x[8];
54 /* offset 0x10 */
55 u16 fpga_rev;
56 u16 board_rev;
57 u16 gpio_outputs;
58 u16 leds;
59 /* offset 0x18 */
60 u16 misc_inputs;
61 u16 lan_status;
62 u16 lan_reset;
63 u16 reserved0;
64 /* offset 0x20 */
65 u16 ps2_data;
66 u16 ps2_ctrl;
67 /* plus also 4 rs232 ports ... */
68};
69
70/* LEDs definition on debug board (16 LEDs, all physically green) */
71#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
72#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
73#define H2P2_DBG_FPGA_LED_RED (1 << 13)
74#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
75/* cpu0 load-meter LEDs */
76#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
77#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
78#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
79
80#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
81#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
82
83/*
84 * ---------------------------------------------------------------------------
85 * OMAP-1510 FPGA
86 * ---------------------------------------------------------------------------
87 */
88#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */
89#define OMAP1510_FPGA_SIZE SZ_4K
90#define OMAP1510_FPGA_START 0x08000000 /* Physical */
91
92/* Revision */
93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
94#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
95
96#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
97#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
98#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
99#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
100
101/* Interrupt status */
102#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
103#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
104
105/* Interrupt mask */
106#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
107#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
108
109/* Reset registers */
110#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
111#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
112
113#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
114#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
115#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
116#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
117#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
118#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
119#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
120#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
121#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
122#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
123
124#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
125
126#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
127#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
128#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
129#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
130#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
131#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
132#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
133#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
134#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
135#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
136#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
137
138#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
139
140/*
141 * Power up Giga UART driver, turn on HID clock.
142 * Turn off BT power, since we're not using it and it
143 * draws power.
144 */
145#define OMAP1510_FPGA_RESET_VALUE 0x42
146
147#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
148#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
149#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
150#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
151#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
152#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
153#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
154#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
155
156/*
157 * Innovator/OMAP1510 FPGA HID register bit definitions
158 */
159#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
160#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
161#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
162#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
163#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
164#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
165#define OMAP1510_FPGA_HID_rsrvd (1<<6)
166#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
167
168/* The FPGA IRQ is cascaded through GPIO_13 */
169#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
170
171/* IRQ Numbers for interrupts muxed through the FPGA */
172#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
173#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
174#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
175#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
176#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
177#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
178#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
179#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
180#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
181#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
182#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
183#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
184#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
185#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
186#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
187#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
188#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
189#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
190#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
191#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
192#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
193#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
194#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
195#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
196
197#endif
diff --git a/include/asm-arm/arch-omap/gpio-switch.h b/include/asm-arm/arch-omap/gpio-switch.h
deleted file mode 100644
index 10da0e07c0cf..000000000000
--- a/include/asm-arm/arch-omap/gpio-switch.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * GPIO switch definitions
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
12#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
13
14#include <linux/types.h>
15
16/* Cover:
17 * high -> closed
18 * low -> open
19 * Connection:
20 * high -> connected
21 * low -> disconnected
22 * Activity:
23 * high -> active
24 * low -> inactive
25 *
26 */
27#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
28#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
29#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
30#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
31#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
32
33struct omap_gpio_switch {
34 const char *name;
35 s16 gpio;
36 unsigned flags:4;
37 unsigned type:4;
38
39 /* Time in ms to debounce when transitioning from
40 * inactive state to active state. */
41 u16 debounce_rising;
42 /* Same for transition from active to inactive state. */
43 u16 debounce_falling;
44
45 /* notify board-specific code about state changes */
46 void (* notify)(void *data, int state);
47 void *notify_data;
48};
49
50/* Call at init time only */
51extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
52 int count);
53
54#endif
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
deleted file mode 100644
index 5ee6a49864c3..000000000000
--- a/include/asm-arm/arch-omap/gpio.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/gpio.h
3 *
4 * OMAP GPIO handling defines and functions
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 *
8 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP_GPIO_H
27#define __ASM_ARCH_OMAP_GPIO_H
28
29#include <asm/arch/irqs.h>
30#include <asm/io.h>
31
32#define OMAP_MPUIO_BASE (void __iomem *)0xfffb5000
33
34#ifdef CONFIG_ARCH_OMAP730
35#define OMAP_MPUIO_INPUT_LATCH 0x00
36#define OMAP_MPUIO_OUTPUT 0x02
37#define OMAP_MPUIO_IO_CNTL 0x04
38#define OMAP_MPUIO_KBR_LATCH 0x08
39#define OMAP_MPUIO_KBC 0x0a
40#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
41#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
42#define OMAP_MPUIO_KBD_INT 0x10
43#define OMAP_MPUIO_GPIO_INT 0x12
44#define OMAP_MPUIO_KBD_MASKIT 0x14
45#define OMAP_MPUIO_GPIO_MASKIT 0x16
46#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
47#define OMAP_MPUIO_LATCH 0x1a
48#else
49#define OMAP_MPUIO_INPUT_LATCH 0x00
50#define OMAP_MPUIO_OUTPUT 0x04
51#define OMAP_MPUIO_IO_CNTL 0x08
52#define OMAP_MPUIO_KBR_LATCH 0x10
53#define OMAP_MPUIO_KBC 0x14
54#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
55#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
56#define OMAP_MPUIO_KBD_INT 0x20
57#define OMAP_MPUIO_GPIO_INT 0x24
58#define OMAP_MPUIO_KBD_MASKIT 0x28
59#define OMAP_MPUIO_GPIO_MASKIT 0x2c
60#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
61#define OMAP_MPUIO_LATCH 0x34
62#endif
63
64#define OMAP34XX_NR_GPIOS 6
65
66#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
67#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
68
69#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
70 IH_MPUIO_BASE + ((nr) & 0x0f) : \
71 IH_GPIO_BASE + (nr))
72
73extern int omap_gpio_init(void); /* Call from board init only */
74extern int omap_request_gpio(int gpio);
75extern void omap_free_gpio(int gpio);
76extern void omap_set_gpio_direction(int gpio, int is_input);
77extern void omap_set_gpio_dataout(int gpio, int enable);
78extern int omap_get_gpio_datain(int gpio);
79extern void omap_set_gpio_debounce(int gpio, int enable);
80extern void omap_set_gpio_debounce_time(int gpio, int enable);
81
82/*-------------------------------------------------------------------------*/
83
84/* Wrappers for "new style" GPIO calls, using the new infrastructure
85 * which lets us plug in FPGA, I2C, and other implementations.
86 * *
87 * The original OMAP-specfic calls should eventually be removed.
88 */
89
90#include <linux/errno.h>
91#include <asm-generic/gpio.h>
92
93static inline int gpio_get_value(unsigned gpio)
94{
95 return __gpio_get_value(gpio);
96}
97
98static inline void gpio_set_value(unsigned gpio, int value)
99{
100 __gpio_set_value(gpio, value);
101}
102
103static inline int gpio_cansleep(unsigned gpio)
104{
105 return __gpio_cansleep(gpio);
106}
107
108static inline int gpio_to_irq(unsigned gpio)
109{
110 if (gpio < (OMAP_MAX_GPIO_LINES + 16))
111 return OMAP_GPIO_IRQ(gpio);
112 return -EINVAL;
113}
114
115static inline int irq_to_gpio(unsigned irq)
116{
117 if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
118 return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
119 return irq - IH_GPIO_BASE;
120}
121
122#endif
diff --git a/include/asm-arm/arch-omap/gpioexpander.h b/include/asm-arm/arch-omap/gpioexpander.h
deleted file mode 100644
index 4eed1f80e2fb..000000000000
--- a/include/asm-arm/arch-omap/gpioexpander.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/gpioexpander.h
3 *
4 *
5 * Copyright (C) 2004 Texas Instruments, Inc.
6 *
7 * This package is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
12 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
13 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 */
15
16#ifndef __ASM_ARCH_OMAP_GPIOEXPANDER_H
17#define __ASM_ARCH_OMAP_GPIOEXPANDER_H
18
19/* Function Prototypes for GPIO Expander functions */
20
21#ifdef CONFIG_GPIOEXPANDER_OMAP
22int read_gpio_expa(u8 *, int);
23int write_gpio_expa(u8 , int);
24#else
25static inline int read_gpio_expa(u8 *val, int addr)
26{
27 return 0;
28}
29static inline int write_gpio_expa(u8 val, int addr)
30{
31 return 0;
32}
33#endif
34
35#endif /* __ASM_ARCH_OMAP_GPIOEXPANDER_H */
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
deleted file mode 100644
index 6a8e07ffc2d0..000000000000
--- a/include/asm-arm/arch-omap/gpmc.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14#define GPMC_CS_CONFIG1 0x00
15#define GPMC_CS_CONFIG2 0x04
16#define GPMC_CS_CONFIG3 0x08
17#define GPMC_CS_CONFIG4 0x0c
18#define GPMC_CS_CONFIG5 0x10
19#define GPMC_CS_CONFIG6 0x14
20#define GPMC_CS_CONFIG7 0x18
21#define GPMC_CS_NAND_COMMAND 0x1c
22#define GPMC_CS_NAND_ADDRESS 0x20
23#define GPMC_CS_NAND_DATA 0x24
24
25#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
26#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
27#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
28#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
29#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
30#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
31#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
32#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
33#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
34#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
35#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
36#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
37#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
38#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
39#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
40#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
41#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
42#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1)
43#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
44#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
45#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
46#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
47#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
48#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
49
50/*
51 * Note that all values in this struct are in nanoseconds, while
52 * the register values are in gpmc_fck cycles.
53 */
54struct gpmc_timings {
55 /* Minimum clock period for synchronous mode */
56 u16 sync_clk;
57
58 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u16 cs_on; /* Assertion time */
60 u16 cs_rd_off; /* Read deassertion time */
61 u16 cs_wr_off; /* Write deassertion time */
62
63 /* ADV signal timings corresponding to GPMC_CONFIG3 */
64 u16 adv_on; /* Assertion time */
65 u16 adv_rd_off; /* Read deassertion time */
66 u16 adv_wr_off; /* Write deassertion time */
67
68 /* WE signals timings corresponding to GPMC_CONFIG4 */
69 u16 we_on; /* WE assertion time */
70 u16 we_off; /* WE deassertion time */
71
72 /* OE signals timings corresponding to GPMC_CONFIG4 */
73 u16 oe_on; /* OE assertion time */
74 u16 oe_off; /* OE deassertion time */
75
76 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
77 u16 page_burst_access; /* Multiple access word delay */
78 u16 access; /* Start-cycle to first data valid delay */
79 u16 rd_cycle; /* Total read cycle time */
80 u16 wr_cycle; /* Total write cycle time */
81};
82
83extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
84extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
85extern unsigned long gpmc_get_fclk_period(void);
86
87extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
88extern u32 gpmc_cs_read_reg(int cs, int idx);
89extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
90extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
91extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
92extern void gpmc_cs_free(int cs);
93extern int gpmc_cs_set_reserved(int cs, int reserved);
94extern int gpmc_cs_reserved(int cs);
95
96#endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
deleted file mode 100644
index 45fdfccbd5d4..000000000000
--- a/include/asm-arm/arch-omap/hardware.h
+++ /dev/null
@@ -1,355 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/hardware.h
3 *
4 * Hardware definitions for TI OMAP processors and boards
5 *
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
8 *
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
11 *
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35
36#ifndef __ASM_ARCH_OMAP_HARDWARE_H
37#define __ASM_ARCH_OMAP_HARDWARE_H
38
39#include <asm/sizes.h>
40#ifndef __ASSEMBLER__
41#include <asm/types.h>
42#include <asm/arch/cpu.h>
43#endif
44#include <asm/arch/serial.h>
45
46/*
47 * ---------------------------------------------------------------------------
48 * Common definitions for all OMAP processors
49 * NOTE: Put all processor or board specific parts to the special header
50 * files.
51 * ---------------------------------------------------------------------------
52 */
53
54/*
55 * ----------------------------------------------------------------------------
56 * Timers
57 * ----------------------------------------------------------------------------
58 */
59#define OMAP_MPU_TIMER1_BASE (0xfffec500)
60#define OMAP_MPU_TIMER2_BASE (0xfffec600)
61#define OMAP_MPU_TIMER3_BASE (0xfffec700)
62#define MPU_TIMER_FREE (1 << 6)
63#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
64#define MPU_TIMER_AR (1 << 1)
65#define MPU_TIMER_ST (1 << 0)
66
67/*
68 * ----------------------------------------------------------------------------
69 * Clocks
70 * ----------------------------------------------------------------------------
71 */
72#define CLKGEN_REG_BASE (0xfffece00)
73#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
74#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
75#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
76#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
77#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
78#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
79#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
80#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
81
82#define CK_RATEF 1
83#define CK_IDLEF 2
84#define CK_ENABLEF 4
85#define CK_SELECTF 8
86#define SETARM_IDLE_SHIFT
87
88/* DPLL control registers */
89#define DPLL_CTL (0xfffecf00)
90
91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
92#define DSP_CONFIG_REG_BASE (0xe1008000)
93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
96#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
97
98/*
99 * ---------------------------------------------------------------------------
100 * UPLD
101 * ---------------------------------------------------------------------------
102 */
103#define ULPD_REG_BASE (0xfffe0800)
104#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
105#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
106#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
107# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
108# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
109#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
110# define SOFT_UDC_REQ (1 << 4)
111# define SOFT_USB_CLK_REQ (1 << 3)
112# define SOFT_DPLL_REQ (1 << 0)
113#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
114#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
115#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
116#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
117#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
118# define DIS_MMC2_DPLL_REQ (1 << 11)
119# define DIS_MMC1_DPLL_REQ (1 << 10)
120# define DIS_UART3_DPLL_REQ (1 << 9)
121# define DIS_UART2_DPLL_REQ (1 << 8)
122# define DIS_UART1_DPLL_REQ (1 << 7)
123# define DIS_USB_HOST_DPLL_REQ (1 << 6)
124#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
125#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
126
127/*
128 * ---------------------------------------------------------------------------
129 * Watchdog timer
130 * ---------------------------------------------------------------------------
131 */
132
133/* Watchdog timer within the OMAP3.2 gigacell */
134#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
135#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
136#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
137#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
138#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
139
140/*
141 * ---------------------------------------------------------------------------
142 * Interrupts
143 * ---------------------------------------------------------------------------
144 */
145#ifdef CONFIG_ARCH_OMAP1
146
147/*
148 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
149 * or something similar.. -- PFM.
150 */
151
152#define OMAP_IH1_BASE 0xfffecb00
153#define OMAP_IH2_BASE 0xfffe0000
154
155#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
156#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
157#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
158#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
159#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
160#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
161#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
162
163#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
164#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
165#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
166#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
167#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
168#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
169#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
170
171#define IRQ_ITR_REG_OFFSET 0x00
172#define IRQ_MIR_REG_OFFSET 0x04
173#define IRQ_SIR_IRQ_REG_OFFSET 0x10
174#define IRQ_SIR_FIQ_REG_OFFSET 0x14
175#define IRQ_CONTROL_REG_OFFSET 0x18
176#define IRQ_ISR_REG_OFFSET 0x9c
177#define IRQ_ILR0_REG_OFFSET 0x1c
178#define IRQ_GMR_REG_OFFSET 0xa0
179
180#endif
181
182/*
183 * ----------------------------------------------------------------------------
184 * System control registers
185 * ----------------------------------------------------------------------------
186 */
187#define MOD_CONF_CTRL_0 0xfffe1080
188#define MOD_CONF_CTRL_1 0xfffe1110
189
190/*
191 * ----------------------------------------------------------------------------
192 * Pin multiplexing registers
193 * ----------------------------------------------------------------------------
194 */
195#define FUNC_MUX_CTRL_0 0xfffe1000
196#define FUNC_MUX_CTRL_1 0xfffe1004
197#define FUNC_MUX_CTRL_2 0xfffe1008
198#define COMP_MODE_CTRL_0 0xfffe100c
199#define FUNC_MUX_CTRL_3 0xfffe1010
200#define FUNC_MUX_CTRL_4 0xfffe1014
201#define FUNC_MUX_CTRL_5 0xfffe1018
202#define FUNC_MUX_CTRL_6 0xfffe101C
203#define FUNC_MUX_CTRL_7 0xfffe1020
204#define FUNC_MUX_CTRL_8 0xfffe1024
205#define FUNC_MUX_CTRL_9 0xfffe1028
206#define FUNC_MUX_CTRL_A 0xfffe102C
207#define FUNC_MUX_CTRL_B 0xfffe1030
208#define FUNC_MUX_CTRL_C 0xfffe1034
209#define FUNC_MUX_CTRL_D 0xfffe1038
210#define PULL_DWN_CTRL_0 0xfffe1040
211#define PULL_DWN_CTRL_1 0xfffe1044
212#define PULL_DWN_CTRL_2 0xfffe1048
213#define PULL_DWN_CTRL_3 0xfffe104c
214#define PULL_DWN_CTRL_4 0xfffe10ac
215
216/* OMAP-1610 specific multiplexing registers */
217#define FUNC_MUX_CTRL_E 0xfffe1090
218#define FUNC_MUX_CTRL_F 0xfffe1094
219#define FUNC_MUX_CTRL_10 0xfffe1098
220#define FUNC_MUX_CTRL_11 0xfffe109c
221#define FUNC_MUX_CTRL_12 0xfffe10a0
222#define PU_PD_SEL_0 0xfffe10b4
223#define PU_PD_SEL_1 0xfffe10b8
224#define PU_PD_SEL_2 0xfffe10bc
225#define PU_PD_SEL_3 0xfffe10c0
226#define PU_PD_SEL_4 0xfffe10c4
227
228/* Timer32K for 1610 and 1710*/
229#define OMAP_TIMER32K_BASE 0xFFFBC400
230
231/*
232 * ---------------------------------------------------------------------------
233 * TIPB bus interface
234 * ---------------------------------------------------------------------------
235 */
236#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
237#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
238#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
239#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
240
241/*
242 * ----------------------------------------------------------------------------
243 * MPUI interface
244 * ----------------------------------------------------------------------------
245 */
246#define MPUI_BASE (0xfffec900)
247#define MPUI_CTRL (MPUI_BASE + 0x0)
248#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
249#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
250#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
251#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
252#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
253#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
254#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
255
256/*
257 * ----------------------------------------------------------------------------
258 * LED Pulse Generator
259 * ----------------------------------------------------------------------------
260 */
261#define OMAP_LPG1_BASE 0xfffbd000
262#define OMAP_LPG2_BASE 0xfffbd800
263#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
264#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
265#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
266#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
267
268/*
269 * ----------------------------------------------------------------------------
270 * Pulse-Width Light
271 * ----------------------------------------------------------------------------
272 */
273#define OMAP_PWL_BASE 0xfffb5800
274#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
275#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
276
277/*
278 * ---------------------------------------------------------------------------
279 * Processor specific defines
280 * ---------------------------------------------------------------------------
281 */
282
283#include "omap730.h"
284#include "omap1510.h"
285#include "omap24xx.h"
286#include "omap16xx.h"
287#include "omap34xx.h"
288
289#ifndef __ASSEMBLER__
290
291/*
292 * ---------------------------------------------------------------------------
293 * Board specific defines
294 * ---------------------------------------------------------------------------
295 */
296
297#ifdef CONFIG_MACH_OMAP_INNOVATOR
298#include "board-innovator.h"
299#endif
300
301#ifdef CONFIG_MACH_OMAP_H2
302#include "board-h2.h"
303#endif
304
305#ifdef CONFIG_MACH_OMAP_PERSEUS2
306#include "board-perseus2.h"
307#endif
308
309#ifdef CONFIG_MACH_OMAP_FSAMPLE
310#include "board-fsample.h"
311#endif
312
313#ifdef CONFIG_MACH_OMAP_H3
314#include "board-h3.h"
315#endif
316
317#ifdef CONFIG_MACH_OMAP_H4
318#include "board-h4.h"
319#endif
320
321#ifdef CONFIG_MACH_OMAP_2430SDP
322#include "board-2430sdp.h"
323#endif
324
325#ifdef CONFIG_MACH_OMAP_APOLLON
326#include "board-apollon.h"
327#endif
328
329#ifdef CONFIG_MACH_OMAP_OSK
330#include "board-osk.h"
331#endif
332
333#ifdef CONFIG_MACH_VOICEBLUE
334#include "board-voiceblue.h"
335#endif
336
337#ifdef CONFIG_MACH_OMAP_PALMTE
338#include "board-palmte.h"
339#endif
340
341#ifdef CONFIG_MACH_OMAP_PALMZ71
342#include "board-palmz71.h"
343#endif
344
345#ifdef CONFIG_MACH_OMAP_PALMTT
346#include "board-palmtt.h"
347#endif
348
349#ifdef CONFIG_MACH_SX1
350#include "board-sx1.h"
351#endif
352
353#endif /* !__ASSEMBLER__ */
354
355#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/include/asm-arm/arch-omap/hwa742.h b/include/asm-arm/arch-omap/hwa742.h
deleted file mode 100644
index 577f492f2d3c..000000000000
--- a/include/asm-arm/arch-omap/hwa742.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _HWA742_H
2#define _HWA742_H
3
4struct hwa742_platform_data {
5 void (*power_up)(struct device *dev);
6 void (*power_down)(struct device *dev);
7 unsigned long (*get_clock_rate)(struct device *dev);
8
9 unsigned te_connected:1;
10};
11
12#endif
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
deleted file mode 100644
index 449e3568baa6..000000000000
--- a/include/asm-arm/arch-omap/io.h
+++ /dev/null
@@ -1,197 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/io.h
3 *
4 * IO definitions for TI OMAP processors and boards
5 *
6 * Copied from linux/include/asm-arm/arch-sa1100/io.h
7 * Copyright (C) 1997-1999 Russell King
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Modifications:
30 * 06-12-1997 RMK Created.
31 * 07-04-1999 RMK Major cleanup
32 */
33
34#ifndef __ASM_ARM_ARCH_IO_H
35#define __ASM_ARM_ARCH_IO_H
36
37#include <asm/arch/hardware.h>
38
39#define IO_SPACE_LIMIT 0xffffffff
40
41/*
42 * We don't actually have real ISA nor PCI buses, but there is so many
43 * drivers out there that might just work if we fake them...
44 */
45#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
46#define __mem_pci(a) (a)
47
48/*
49 * ----------------------------------------------------------------------------
50 * I/O mapping
51 * ----------------------------------------------------------------------------
52 */
53
54#define PCIO_BASE 0
55
56#if defined(CONFIG_ARCH_OMAP1)
57
58#define IO_PHYS 0xFFFB0000
59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
60#define IO_SIZE 0x40000
61#define IO_VIRT (IO_PHYS - IO_OFFSET)
62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
64#define io_p2v(pa) ((pa) - IO_OFFSET)
65#define io_v2p(va) ((va) + IO_OFFSET)
66
67#elif defined(CONFIG_ARCH_OMAP2)
68
69/* We map both L3 and L4 on OMAP2 */
70#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */
71#define L3_24XX_VIRT 0xf8000000
72#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
73#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */
74#define L4_24XX_VIRT 0xd8000000
75#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
76
77#ifdef CONFIG_ARCH_OMAP2430
78#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
79#define L4_WK_243X_VIRT 0xd9000000
80#define L4_WK_243X_SIZE SZ_1M
81#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
82#define OMAP243X_GPMC_VIRT 0xFE000000
83#define OMAP243X_GPMC_SIZE SZ_1M
84#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
85#define OMAP243X_SDRC_VIRT 0xFD000000
86#define OMAP243X_SDRC_SIZE SZ_1M
87#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
88#define OMAP243X_SMS_VIRT 0xFC000000
89#define OMAP243X_SMS_SIZE SZ_1M
90
91#endif
92
93#define IO_OFFSET 0x90000000
94#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
95#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
96#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
97#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
98
99/* DSP */
100#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
101#define DSP_MEM_24XX_VIRT 0xe0000000
102#define DSP_MEM_24XX_SIZE 0x28000
103#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
104#define DSP_IPI_24XX_VIRT 0xe1000000
105#define DSP_IPI_24XX_SIZE SZ_4K
106#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
107#define DSP_MMU_24XX_VIRT 0xe2000000
108#define DSP_MMU_24XX_SIZE SZ_4K
109
110#elif defined(CONFIG_ARCH_OMAP3)
111
112/* We map both L3 and L4 on OMAP3 */
113#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
114#define L3_34XX_VIRT 0xf8000000
115#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
116
117#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */
118#define L4_34XX_VIRT 0xd8000000
119#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
120
121/*
122 * Need to look at the Size 4M for L4.
123 * VPOM3430 was not working for Int controller
124 */
125
126#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */
127#define L4_WK_34XX_VIRT 0xd8300000
128#define L4_WK_34XX_SIZE SZ_1M
129
130#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */
131#define L4_PER_34XX_VIRT 0xd9000000
132#define L4_PER_34XX_SIZE SZ_1M
133
134#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */
135#define L4_EMU_34XX_VIRT 0xe4000000
136#define L4_EMU_34XX_SIZE SZ_64M
137
138#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */
139#define OMAP34XX_GPMC_VIRT 0xFE000000
140#define OMAP34XX_GPMC_SIZE SZ_1M
141
142#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
143#define OMAP343X_SMS_VIRT 0xFC000000
144#define OMAP343X_SMS_SIZE SZ_1M
145
146#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
147#define OMAP343X_SDRC_VIRT 0xFD000000
148#define OMAP343X_SDRC_SIZE SZ_1M
149
150
151#define IO_OFFSET 0x90000000
152#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
153#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
154#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
155#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
156
157/* DSP */
158#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
159#define DSP_MEM_34XX_VIRT 0xe0000000
160#define DSP_MEM_34XX_SIZE 0x28000
161#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
162#define DSP_IPI_34XX_VIRT 0xe1000000
163#define DSP_IPI_34XX_SIZE SZ_4K
164#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
165#define DSP_MMU_34XX_VIRT 0xe2000000
166#define DSP_MMU_34XX_SIZE SZ_4K
167
168#endif
169
170#ifndef __ASSEMBLER__
171
172/*
173 * Functions to access the OMAP IO region
174 *
175 * NOTE: - Use omap_read/write[bwl] for physical register addresses
176 * - Use __raw_read/write[bwl]() for virtual register addresses
177 * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
178 * - DO NOT use hardcoded virtual addresses to allow changing the
179 * IO address space again if needed
180 */
181#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a))
182#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a))
183#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a))
184
185#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v))
186#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
187#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
188
189extern void omap1_map_common_io(void);
190extern void omap1_init_common_hw(void);
191
192extern void omap2_map_common_io(void);
193extern void omap2_init_common_hw(void);
194
195#endif
196
197#endif
diff --git a/include/asm-arm/arch-omap/irda.h b/include/asm-arm/arch-omap/irda.h
deleted file mode 100644
index 96bb12fab438..000000000000
--- a/include/asm-arm/arch-omap/irda.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/irda.h
3 *
4 * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef ASMARM_ARCH_IRDA_H
11#define ASMARM_ARCH_IRDA_H
12
13/* board specific transceiver capabilities */
14
15#define IR_SEL 1 /* Selects IrDA */
16#define IR_SIRMODE 2
17#define IR_FIRMODE 4
18#define IR_MIRMODE 8
19
20struct omap_irda_config {
21 int transceiver_cap;
22 int (*transceiver_mode)(struct device *dev, int mode);
23 int (*select_irda)(struct device *dev, int state);
24 /* Very specific to the needs of some platforms (h3,h4)
25 * having calls which can sleep in irda_set_speed.
26 */
27 struct delayed_work gpio_expa;
28 int rx_channel;
29 int tx_channel;
30 unsigned long dest_start;
31 unsigned long src_start;
32 int tx_trigger;
33 int rx_trigger;
34 int mode;
35};
36
37#endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
deleted file mode 100644
index afbf1e846468..000000000000
--- a/include/asm-arm/arch-omap/irqs.h
+++ /dev/null
@@ -1,332 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/irqs.h
3 *
4 * Copyright (C) Greg Lonnon 2001
5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
22 * are different.
23 */
24
25#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
26#define __ASM_ARCH_OMAP15XX_IRQS_H
27
28/*
29 * IRQ numbers for interrupt handler 1
30 *
31 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
32 *
33 */
34#define INT_CAMERA 1
35#define INT_FIQ 3
36#define INT_RTDX 6
37#define INT_DSP_MMU_ABORT 7
38#define INT_HOST 8
39#define INT_ABORT 9
40#define INT_BRIDGE_PRIV 13
41#define INT_GPIO_BANK1 14
42#define INT_UART3 15
43#define INT_TIMER3 16
44#define INT_DMA_CH0_6 19
45#define INT_DMA_CH1_7 20
46#define INT_DMA_CH2_8 21
47#define INT_DMA_CH3 22
48#define INT_DMA_CH4 23
49#define INT_DMA_CH5 24
50#define INT_DMA_LCD 25
51#define INT_TIMER1 26
52#define INT_WD_TIMER 27
53#define INT_BRIDGE_PUB 28
54#define INT_TIMER2 30
55#define INT_LCD_CTRL 31
56
57/*
58 * OMAP-1510 specific IRQ numbers for interrupt handler 1
59 */
60#define INT_1510_IH2_IRQ 0
61#define INT_1510_RES2 2
62#define INT_1510_SPI_TX 4
63#define INT_1510_SPI_RX 5
64#define INT_1510_DSP_MAILBOX1 10
65#define INT_1510_DSP_MAILBOX2 11
66#define INT_1510_RES12 12
67#define INT_1510_LB_MMU 17
68#define INT_1510_RES18 18
69#define INT_1510_LOCAL_BUS 29
70
71/*
72 * OMAP-1610 specific IRQ numbers for interrupt handler 1
73 */
74#define INT_1610_IH2_IRQ 0
75#define INT_1610_IH2_FIQ 2
76#define INT_1610_McBSP2_TX 4
77#define INT_1610_McBSP2_RX 5
78#define INT_1610_DSP_MAILBOX1 10
79#define INT_1610_DSP_MAILBOX2 11
80#define INT_1610_LCD_LINE 12
81#define INT_1610_GPTIMER1 17
82#define INT_1610_GPTIMER2 18
83#define INT_1610_SSR_FIFO_0 29
84
85/*
86 * OMAP-730 specific IRQ numbers for interrupt handler 1
87 */
88#define INT_730_IH2_FIQ 0
89#define INT_730_IH2_IRQ 1
90#define INT_730_USB_NON_ISO 2
91#define INT_730_USB_ISO 3
92#define INT_730_ICR 4
93#define INT_730_EAC 5
94#define INT_730_GPIO_BANK1 6
95#define INT_730_GPIO_BANK2 7
96#define INT_730_GPIO_BANK3 8
97#define INT_730_McBSP2TX 10
98#define INT_730_McBSP2RX 11
99#define INT_730_McBSP2RX_OVF 12
100#define INT_730_LCD_LINE 14
101#define INT_730_GSM_PROTECT 15
102#define INT_730_TIMER3 16
103#define INT_730_GPIO_BANK5 17
104#define INT_730_GPIO_BANK6 18
105#define INT_730_SPGIO_WR 29
106
107/*
108 * IRQ numbers for interrupt handler 2
109 *
110 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
111 */
112#define IH2_BASE 32
113
114#define INT_KEYBOARD (1 + IH2_BASE)
115#define INT_uWireTX (2 + IH2_BASE)
116#define INT_uWireRX (3 + IH2_BASE)
117#define INT_I2C (4 + IH2_BASE)
118#define INT_MPUIO (5 + IH2_BASE)
119#define INT_USB_HHC_1 (6 + IH2_BASE)
120#define INT_McBSP3TX (10 + IH2_BASE)
121#define INT_McBSP3RX (11 + IH2_BASE)
122#define INT_McBSP1TX (12 + IH2_BASE)
123#define INT_McBSP1RX (13 + IH2_BASE)
124#define INT_UART1 (14 + IH2_BASE)
125#define INT_UART2 (15 + IH2_BASE)
126#define INT_BT_MCSI1TX (16 + IH2_BASE)
127#define INT_BT_MCSI1RX (17 + IH2_BASE)
128#define INT_USB_W2FC (20 + IH2_BASE)
129#define INT_1WIRE (21 + IH2_BASE)
130#define INT_OS_TIMER (22 + IH2_BASE)
131#define INT_MMC (23 + IH2_BASE)
132#define INT_GAUGE_32K (24 + IH2_BASE)
133#define INT_RTC_TIMER (25 + IH2_BASE)
134#define INT_RTC_ALARM (26 + IH2_BASE)
135#define INT_MEM_STICK (27 + IH2_BASE)
136
137/*
138 * OMAP-1510 specific IRQ numbers for interrupt handler 2
139 */
140#define INT_1510_DSP_MMU (28 + IH2_BASE)
141#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
142
143/*
144 * OMAP-1610 specific IRQ numbers for interrupt handler 2
145 */
146#define INT_1610_FAC (0 + IH2_BASE)
147#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
148#define INT_1610_USB_OTG (8 + IH2_BASE)
149#define INT_1610_SoSSI (9 + IH2_BASE)
150#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
151#define INT_1610_DSP_MMU (28 + IH2_BASE)
152#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
153#define INT_1610_STI (32 + IH2_BASE)
154#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
155#define INT_1610_GPTIMER3 (34 + IH2_BASE)
156#define INT_1610_GPTIMER4 (35 + IH2_BASE)
157#define INT_1610_GPTIMER5 (36 + IH2_BASE)
158#define INT_1610_GPTIMER6 (37 + IH2_BASE)
159#define INT_1610_GPTIMER7 (38 + IH2_BASE)
160#define INT_1610_GPTIMER8 (39 + IH2_BASE)
161#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
162#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
163#define INT_1610_MMC2 (42 + IH2_BASE)
164#define INT_1610_CF (43 + IH2_BASE)
165#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
166#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
167#define INT_1610_SPI (49 + IH2_BASE)
168#define INT_1610_DMA_CH6 (53 + IH2_BASE)
169#define INT_1610_DMA_CH7 (54 + IH2_BASE)
170#define INT_1610_DMA_CH8 (55 + IH2_BASE)
171#define INT_1610_DMA_CH9 (56 + IH2_BASE)
172#define INT_1610_DMA_CH10 (57 + IH2_BASE)
173#define INT_1610_DMA_CH11 (58 + IH2_BASE)
174#define INT_1610_DMA_CH12 (59 + IH2_BASE)
175#define INT_1610_DMA_CH13 (60 + IH2_BASE)
176#define INT_1610_DMA_CH14 (61 + IH2_BASE)
177#define INT_1610_DMA_CH15 (62 + IH2_BASE)
178#define INT_1610_NAND (63 + IH2_BASE)
179
180/*
181 * OMAP-730 specific IRQ numbers for interrupt handler 2
182 */
183#define INT_730_HW_ERRORS (0 + IH2_BASE)
184#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE)
185#define INT_730_CFCD (2 + IH2_BASE)
186#define INT_730_CFIREQ (3 + IH2_BASE)
187#define INT_730_I2C (4 + IH2_BASE)
188#define INT_730_PCC (5 + IH2_BASE)
189#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE)
190#define INT_730_SPI_100K_1 (7 + IH2_BASE)
191#define INT_730_SYREN_SPI (8 + IH2_BASE)
192#define INT_730_VLYNQ (9 + IH2_BASE)
193#define INT_730_GPIO_BANK4 (10 + IH2_BASE)
194#define INT_730_McBSP1TX (11 + IH2_BASE)
195#define INT_730_McBSP1RX (12 + IH2_BASE)
196#define INT_730_McBSP1RX_OF (13 + IH2_BASE)
197#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
198#define INT_730_UART_MODEM_1 (15 + IH2_BASE)
199#define INT_730_MCSI (16 + IH2_BASE)
200#define INT_730_uWireTX (17 + IH2_BASE)
201#define INT_730_uWireRX (18 + IH2_BASE)
202#define INT_730_SMC_CD (19 + IH2_BASE)
203#define INT_730_SMC_IREQ (20 + IH2_BASE)
204#define INT_730_HDQ_1WIRE (21 + IH2_BASE)
205#define INT_730_TIMER32K (22 + IH2_BASE)
206#define INT_730_MMC_SDIO (23 + IH2_BASE)
207#define INT_730_UPLD (24 + IH2_BASE)
208#define INT_730_USB_HHC_1 (27 + IH2_BASE)
209#define INT_730_USB_HHC_2 (28 + IH2_BASE)
210#define INT_730_USB_GENI (29 + IH2_BASE)
211#define INT_730_USB_OTG (30 + IH2_BASE)
212#define INT_730_CAMERA_IF (31 + IH2_BASE)
213#define INT_730_RNG (32 + IH2_BASE)
214#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
215#define INT_730_DBB_RF_EN (34 + IH2_BASE)
216#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE)
217#define INT_730_SHA1_MD5 (36 + IH2_BASE)
218#define INT_730_SPI_100K_2 (37 + IH2_BASE)
219#define INT_730_RNG_IDLE (38 + IH2_BASE)
220#define INT_730_MPUIO (39 + IH2_BASE)
221#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
222#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
223#define INT_730_LLPC_OE_RISING (42 + IH2_BASE)
224#define INT_730_LLPC_VSYNC (43 + IH2_BASE)
225#define INT_730_WAKE_UP_REQ (46 + IH2_BASE)
226#define INT_730_DMA_CH6 (53 + IH2_BASE)
227#define INT_730_DMA_CH7 (54 + IH2_BASE)
228#define INT_730_DMA_CH8 (55 + IH2_BASE)
229#define INT_730_DMA_CH9 (56 + IH2_BASE)
230#define INT_730_DMA_CH10 (57 + IH2_BASE)
231#define INT_730_DMA_CH11 (58 + IH2_BASE)
232#define INT_730_DMA_CH12 (59 + IH2_BASE)
233#define INT_730_DMA_CH13 (60 + IH2_BASE)
234#define INT_730_DMA_CH14 (61 + IH2_BASE)
235#define INT_730_DMA_CH15 (62 + IH2_BASE)
236#define INT_730_NAND (63 + IH2_BASE)
237
238#define INT_24XX_SYS_NIRQ 7
239#define INT_24XX_SDMA_IRQ0 12
240#define INT_24XX_SDMA_IRQ1 13
241#define INT_24XX_SDMA_IRQ2 14
242#define INT_24XX_SDMA_IRQ3 15
243#define INT_24XX_CAM_IRQ 24
244#define INT_24XX_DSS_IRQ 25
245#define INT_24XX_MAIL_U0_MPU 26
246#define INT_24XX_DSP_UMA 27
247#define INT_24XX_DSP_MMU 28
248#define INT_24XX_GPIO_BANK1 29
249#define INT_24XX_GPIO_BANK2 30
250#define INT_24XX_GPIO_BANK3 31
251#define INT_24XX_GPIO_BANK4 32
252#define INT_24XX_GPIO_BANK5 33
253#define INT_24XX_MAIL_U3_MPU 34
254#define INT_24XX_GPTIMER1 37
255#define INT_24XX_GPTIMER2 38
256#define INT_24XX_GPTIMER3 39
257#define INT_24XX_GPTIMER4 40
258#define INT_24XX_GPTIMER5 41
259#define INT_24XX_GPTIMER6 42
260#define INT_24XX_GPTIMER7 43
261#define INT_24XX_GPTIMER8 44
262#define INT_24XX_GPTIMER9 45
263#define INT_24XX_GPTIMER10 46
264#define INT_24XX_GPTIMER11 47
265#define INT_24XX_GPTIMER12 48
266#define INT_24XX_I2C1_IRQ 56
267#define INT_24XX_I2C2_IRQ 57
268#define INT_24XX_MCBSP1_IRQ_TX 59
269#define INT_24XX_MCBSP1_IRQ_RX 60
270#define INT_24XX_MCBSP2_IRQ_TX 62
271#define INT_24XX_MCBSP2_IRQ_RX 63
272#define INT_24XX_UART1_IRQ 72
273#define INT_24XX_UART2_IRQ 73
274#define INT_24XX_UART3_IRQ 74
275#define INT_24XX_USB_IRQ_GEN 75
276#define INT_24XX_USB_IRQ_NISO 76
277#define INT_24XX_USB_IRQ_ISO 77
278#define INT_24XX_USB_IRQ_HGEN 78
279#define INT_24XX_USB_IRQ_HSOF 79
280#define INT_24XX_USB_IRQ_OTG 80
281#define INT_24XX_MMC_IRQ 83
282
283/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
284 * 16 MPUIO lines */
285#define OMAP_MAX_GPIO_LINES 192
286#define IH_GPIO_BASE (128 + IH2_BASE)
287#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
288#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
289
290/* External FPGA handles interrupts on Innovator boards */
291#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
292#ifdef CONFIG_MACH_OMAP_INNOVATOR
293#define OMAP_FPGA_NR_IRQS 24
294#else
295#define OMAP_FPGA_NR_IRQS 0
296#endif
297#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
298
299/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
300#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
301#ifdef CONFIG_TWL4030_CORE
302#define TWL4030_BASE_NR_IRQS 8
303#define TWL4030_PWR_NR_IRQS 8
304#else
305#define TWL4030_BASE_NR_IRQS 0
306#define TWL4030_PWR_NR_IRQS 0
307#endif
308#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
309#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
310#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
311
312/* External TWL4030 gpio interrupts are optional */
313#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
314#ifdef CONFIG_TWL4030_GPIO
315#define TWL4030_GPIO_NR_IRQS 18
316#else
317#define TWL4030_GPIO_NR_IRQS 0
318#endif
319#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
320
321/* Total number of interrupts depends on the enabled blocks above */
322#define NR_IRQS TWL4030_GPIO_IRQ_END
323
324#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
325
326#ifndef __ASSEMBLY__
327extern void omap_init_irq(void);
328#endif
329
330#include <asm/arch/hardware.h>
331
332#endif
diff --git a/include/asm-arm/arch-omap/keypad.h b/include/asm-arm/arch-omap/keypad.h
deleted file mode 100644
index b7f83075436e..000000000000
--- a/include/asm-arm/arch-omap/keypad.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/keypad.h
3 *
4 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef ASMARM_ARCH_KEYPAD_H
11#define ASMARM_ARCH_KEYPAD_H
12
13struct omap_kp_platform_data {
14 int rows;
15 int cols;
16 int *keymap;
17 unsigned int keymapsize;
18 unsigned int rep:1;
19 unsigned long delay;
20 unsigned int dbounce:1;
21 /* specific to OMAP242x*/
22 unsigned int *row_gpios;
23 unsigned int *col_gpios;
24};
25
26/* Group (0..3) -- when multiple keys are pressed, only the
27 * keys pressed in the same group are considered as pressed. This is
28 * in order to workaround certain crappy HW designs that produce ghost
29 * keypresses. */
30#define GROUP_0 (0 << 16)
31#define GROUP_1 (1 << 16)
32#define GROUP_2 (2 << 16)
33#define GROUP_3 (3 << 16)
34#define GROUP_MASK GROUP_3
35
36#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
37
38#endif
39
diff --git a/include/asm-arm/arch-omap/lcd_mipid.h b/include/asm-arm/arch-omap/lcd_mipid.h
deleted file mode 100644
index f8fbc4801e52..000000000000
--- a/include/asm-arm/arch-omap/lcd_mipid.h
+++ /dev/null
@@ -1,24 +0,0 @@
1#ifndef __LCD_MIPID_H
2#define __LCD_MIPID_H
3
4enum mipid_test_num {
5 MIPID_TEST_RGB_LINES,
6};
7
8enum mipid_test_result {
9 MIPID_TEST_SUCCESS,
10 MIPID_TEST_INVALID,
11 MIPID_TEST_FAILED,
12};
13
14#ifdef __KERNEL__
15
16struct mipid_platform_data {
17 int nreset_gpio;
18 int data_lines;
19 void (*shutdown)(struct mipid_platform_data *pdata);
20};
21
22#endif
23
24#endif
diff --git a/include/asm-arm/arch-omap/led.h b/include/asm-arm/arch-omap/led.h
deleted file mode 100644
index f3acae28e2da..000000000000
--- a/include/asm-arm/arch-omap/led.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/led.h
3 *
4 * Copyright (C) 2006 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef ASMARM_ARCH_LED_H
12#define ASMARM_ARCH_LED_H
13
14struct omap_led_config {
15 struct led_classdev cdev;
16 s16 gpio;
17};
18
19struct omap_led_platform_data {
20 s16 nr_leds;
21 struct omap_led_config *leds;
22};
23
24#endif
diff --git a/include/asm-arm/arch-omap/mailbox.h b/include/asm-arm/arch-omap/mailbox.h
deleted file mode 100644
index 7cbed9332e16..000000000000
--- a/include/asm-arm/arch-omap/mailbox.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/* mailbox.h */
2
3#ifndef MAILBOX_H
4#define MAILBOX_H
5
6#include <linux/wait.h>
7#include <linux/workqueue.h>
8#include <linux/blkdev.h>
9
10typedef u32 mbox_msg_t;
11typedef void (mbox_receiver_t)(mbox_msg_t msg);
12struct omap_mbox;
13
14typedef int __bitwise omap_mbox_irq_t;
15#define IRQ_TX ((__force omap_mbox_irq_t) 1)
16#define IRQ_RX ((__force omap_mbox_irq_t) 2)
17
18typedef int __bitwise omap_mbox_type_t;
19#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
20#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
21
22struct omap_mbox_ops {
23 omap_mbox_type_t type;
24 int (*startup)(struct omap_mbox *mbox);
25 void (*shutdown)(struct omap_mbox *mbox);
26 /* fifo */
27 mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
28 void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
29 int (*fifo_empty)(struct omap_mbox *mbox);
30 int (*fifo_full)(struct omap_mbox *mbox);
31 /* irq */
32 void (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
33 void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
34 void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
35 int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
36};
37
38struct omap_mbox_queue {
39 spinlock_t lock;
40 struct request_queue *queue;
41 struct work_struct work;
42 int (*callback)(void *);
43 struct omap_mbox *mbox;
44};
45
46struct omap_mbox {
47 char *name;
48 unsigned int irq;
49
50 struct omap_mbox_queue *txq, *rxq;
51
52 struct omap_mbox_ops *ops;
53
54 mbox_msg_t seq_snd, seq_rcv;
55
56 struct device dev;
57
58 struct omap_mbox *next;
59 void *priv;
60
61 void (*err_notify)(void);
62};
63
64int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *);
65void omap_mbox_init_seq(struct omap_mbox *);
66
67struct omap_mbox *omap_mbox_get(const char *);
68void omap_mbox_put(struct omap_mbox *);
69
70int omap_mbox_register(struct omap_mbox *);
71int omap_mbox_unregister(struct omap_mbox *);
72
73#endif /* MAILBOX_H */
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
deleted file mode 100644
index 3da459a282b9..000000000000
--- a/include/asm-arm/arch-omap/mcbsp.h
+++ /dev/null
@@ -1,380 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/mcbsp.h
3 *
4 * Defines for Multi-Channel Buffered Serial Port
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H
26
27#include <linux/completion.h>
28#include <linux/spinlock.h>
29
30#include <asm/arch/hardware.h>
31#include <asm/arch/clock.h>
32
33#define OMAP730_MCBSP1_BASE 0xfffb1000
34#define OMAP730_MCBSP2_BASE 0xfffb1800
35
36#define OMAP1510_MCBSP1_BASE 0xe1011800
37#define OMAP1510_MCBSP2_BASE 0xfffb1000
38#define OMAP1510_MCBSP3_BASE 0xe1017000
39
40#define OMAP1610_MCBSP1_BASE 0xe1011800
41#define OMAP1610_MCBSP2_BASE 0xfffb1000
42#define OMAP1610_MCBSP3_BASE 0xe1017000
43
44#define OMAP24XX_MCBSP1_BASE 0x48074000
45#define OMAP24XX_MCBSP2_BASE 0x48076000
46
47#define OMAP34XX_MCBSP1_BASE 0x48074000
48#define OMAP34XX_MCBSP2_BASE 0x49022000
49
50#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
51
52#define OMAP_MCBSP_REG_DRR2 0x00
53#define OMAP_MCBSP_REG_DRR1 0x02
54#define OMAP_MCBSP_REG_DXR2 0x04
55#define OMAP_MCBSP_REG_DXR1 0x06
56#define OMAP_MCBSP_REG_SPCR2 0x08
57#define OMAP_MCBSP_REG_SPCR1 0x0a
58#define OMAP_MCBSP_REG_RCR2 0x0c
59#define OMAP_MCBSP_REG_RCR1 0x0e
60#define OMAP_MCBSP_REG_XCR2 0x10
61#define OMAP_MCBSP_REG_XCR1 0x12
62#define OMAP_MCBSP_REG_SRGR2 0x14
63#define OMAP_MCBSP_REG_SRGR1 0x16
64#define OMAP_MCBSP_REG_MCR2 0x18
65#define OMAP_MCBSP_REG_MCR1 0x1a
66#define OMAP_MCBSP_REG_RCERA 0x1c
67#define OMAP_MCBSP_REG_RCERB 0x1e
68#define OMAP_MCBSP_REG_XCERA 0x20
69#define OMAP_MCBSP_REG_XCERB 0x22
70#define OMAP_MCBSP_REG_PCR0 0x24
71#define OMAP_MCBSP_REG_RCERC 0x26
72#define OMAP_MCBSP_REG_RCERD 0x28
73#define OMAP_MCBSP_REG_XCERC 0x2A
74#define OMAP_MCBSP_REG_XCERD 0x2C
75#define OMAP_MCBSP_REG_RCERE 0x2E
76#define OMAP_MCBSP_REG_RCERF 0x30
77#define OMAP_MCBSP_REG_XCERE 0x32
78#define OMAP_MCBSP_REG_XCERF 0x34
79#define OMAP_MCBSP_REG_RCERG 0x36
80#define OMAP_MCBSP_REG_RCERH 0x38
81#define OMAP_MCBSP_REG_XCERG 0x3A
82#define OMAP_MCBSP_REG_XCERH 0x3C
83
84#define OMAP_MAX_MCBSP_COUNT 3
85#define MAX_MCBSP_CLOCKS 3
86
87#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
88#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
89
90#define AUDIO_MCBSP OMAP_MCBSP1
91#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
92#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
93
94#elif defined(CONFIG_ARCH_OMAP24XX)
95
96#define OMAP_MCBSP_REG_DRR2 0x00
97#define OMAP_MCBSP_REG_DRR1 0x04
98#define OMAP_MCBSP_REG_DXR2 0x08
99#define OMAP_MCBSP_REG_DXR1 0x0C
100#define OMAP_MCBSP_REG_SPCR2 0x10
101#define OMAP_MCBSP_REG_SPCR1 0x14
102#define OMAP_MCBSP_REG_RCR2 0x18
103#define OMAP_MCBSP_REG_RCR1 0x1C
104#define OMAP_MCBSP_REG_XCR2 0x20
105#define OMAP_MCBSP_REG_XCR1 0x24
106#define OMAP_MCBSP_REG_SRGR2 0x28
107#define OMAP_MCBSP_REG_SRGR1 0x2C
108#define OMAP_MCBSP_REG_MCR2 0x30
109#define OMAP_MCBSP_REG_MCR1 0x34
110#define OMAP_MCBSP_REG_RCERA 0x38
111#define OMAP_MCBSP_REG_RCERB 0x3C
112#define OMAP_MCBSP_REG_XCERA 0x40
113#define OMAP_MCBSP_REG_XCERB 0x44
114#define OMAP_MCBSP_REG_PCR0 0x48
115#define OMAP_MCBSP_REG_RCERC 0x4C
116#define OMAP_MCBSP_REG_RCERD 0x50
117#define OMAP_MCBSP_REG_XCERC 0x54
118#define OMAP_MCBSP_REG_XCERD 0x58
119#define OMAP_MCBSP_REG_RCERE 0x5C
120#define OMAP_MCBSP_REG_RCERF 0x60
121#define OMAP_MCBSP_REG_XCERE 0x64
122#define OMAP_MCBSP_REG_XCERF 0x68
123#define OMAP_MCBSP_REG_RCERG 0x6C
124#define OMAP_MCBSP_REG_RCERH 0x70
125#define OMAP_MCBSP_REG_XCERG 0x74
126#define OMAP_MCBSP_REG_XCERH 0x78
127
128#define OMAP_MAX_MCBSP_COUNT 2
129#define MAX_MCBSP_CLOCKS 2
130
131#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
132#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
133
134#define AUDIO_MCBSP OMAP_MCBSP2
135#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
136#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
137
138#endif
139
140#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
141#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
142
143
144/************************** McBSP SPCR1 bit definitions ***********************/
145#define RRST 0x0001
146#define RRDY 0x0002
147#define RFULL 0x0004
148#define RSYNC_ERR 0x0008
149#define RINTM(value) ((value)<<4) /* bits 4:5 */
150#define ABIS 0x0040
151#define DXENA 0x0080
152#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
153#define RJUST(value) ((value)<<13) /* bits 13:14 */
154#define DLB 0x8000
155
156/************************** McBSP SPCR2 bit definitions ***********************/
157#define XRST 0x0001
158#define XRDY 0x0002
159#define XEMPTY 0x0004
160#define XSYNC_ERR 0x0008
161#define XINTM(value) ((value)<<4) /* bits 4:5 */
162#define GRST 0x0040
163#define FRST 0x0080
164#define SOFT 0x0100
165#define FREE 0x0200
166
167/************************** McBSP PCR bit definitions *************************/
168#define CLKRP 0x0001
169#define CLKXP 0x0002
170#define FSRP 0x0004
171#define FSXP 0x0008
172#define DR_STAT 0x0010
173#define DX_STAT 0x0020
174#define CLKS_STAT 0x0040
175#define SCLKME 0x0080
176#define CLKRM 0x0100
177#define CLKXM 0x0200
178#define FSRM 0x0400
179#define FSXM 0x0800
180#define RIOEN 0x1000
181#define XIOEN 0x2000
182#define IDLE_EN 0x4000
183
184/************************** McBSP RCR1 bit definitions ************************/
185#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
186#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
187
188/************************** McBSP XCR1 bit definitions ************************/
189#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
190#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
191
192/*************************** McBSP RCR2 bit definitions ***********************/
193#define RDATDLY(value) (value) /* Bits 0:1 */
194#define RFIG 0x0004
195#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
196#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
197#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
198#define RPHASE 0x8000
199
200/*************************** McBSP XCR2 bit definitions ***********************/
201#define XDATDLY(value) (value) /* Bits 0:1 */
202#define XFIG 0x0004
203#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
204#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
205#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
206#define XPHASE 0x8000
207
208/************************* McBSP SRGR1 bit definitions ************************/
209#define CLKGDV(value) (value) /* Bits 0:7 */
210#define FWID(value) ((value)<<8) /* Bits 8:15 */
211
212/************************* McBSP SRGR2 bit definitions ************************/
213#define FPER(value) (value) /* Bits 0:11 */
214#define FSGM 0x1000
215#define CLKSM 0x2000
216#define CLKSP 0x4000
217#define GSYNC 0x8000
218
219/************************* McBSP MCR1 bit definitions *************************/
220#define RMCM 0x0001
221#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
222#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
223#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
224
225/************************* McBSP MCR2 bit definitions *************************/
226#define XMCM(value) (value) /* Bits 0:1 */
227#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
228#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
229#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
230
231
232/* we don't do multichannel for now */
233struct omap_mcbsp_reg_cfg {
234 u16 spcr2;
235 u16 spcr1;
236 u16 rcr2;
237 u16 rcr1;
238 u16 xcr2;
239 u16 xcr1;
240 u16 srgr2;
241 u16 srgr1;
242 u16 mcr2;
243 u16 mcr1;
244 u16 pcr0;
245 u16 rcerc;
246 u16 rcerd;
247 u16 xcerc;
248 u16 xcerd;
249 u16 rcere;
250 u16 rcerf;
251 u16 xcere;
252 u16 xcerf;
253 u16 rcerg;
254 u16 rcerh;
255 u16 xcerg;
256 u16 xcerh;
257};
258
259typedef enum {
260 OMAP_MCBSP1 = 0,
261 OMAP_MCBSP2,
262 OMAP_MCBSP3,
263} omap_mcbsp_id;
264
265typedef int __bitwise omap_mcbsp_io_type_t;
266#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
267#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
268
269typedef enum {
270 OMAP_MCBSP_WORD_8 = 0,
271 OMAP_MCBSP_WORD_12,
272 OMAP_MCBSP_WORD_16,
273 OMAP_MCBSP_WORD_20,
274 OMAP_MCBSP_WORD_24,
275 OMAP_MCBSP_WORD_32,
276} omap_mcbsp_word_length;
277
278typedef enum {
279 OMAP_MCBSP_CLK_RISING = 0,
280 OMAP_MCBSP_CLK_FALLING,
281} omap_mcbsp_clk_polarity;
282
283typedef enum {
284 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
285 OMAP_MCBSP_FS_ACTIVE_LOW,
286} omap_mcbsp_fs_polarity;
287
288typedef enum {
289 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
290 OMAP_MCBSP_CLK_STP_MODE_DELAY,
291} omap_mcbsp_clk_stp_mode;
292
293
294/******* SPI specific mode **********/
295typedef enum {
296 OMAP_MCBSP_SPI_MASTER = 0,
297 OMAP_MCBSP_SPI_SLAVE,
298} omap_mcbsp_spi_mode;
299
300struct omap_mcbsp_spi_cfg {
301 omap_mcbsp_spi_mode spi_mode;
302 omap_mcbsp_clk_polarity rx_clock_polarity;
303 omap_mcbsp_clk_polarity tx_clock_polarity;
304 omap_mcbsp_fs_polarity fsx_polarity;
305 u8 clk_div;
306 omap_mcbsp_clk_stp_mode clk_stp_mode;
307 omap_mcbsp_word_length word_length;
308};
309
310/* Platform specific configuration */
311struct omap_mcbsp_ops {
312 void (*request)(unsigned int);
313 void (*free)(unsigned int);
314 int (*check)(unsigned int);
315};
316
317struct omap_mcbsp_platform_data {
318 u32 virt_base;
319 u8 dma_rx_sync, dma_tx_sync;
320 u16 rx_irq, tx_irq;
321 struct omap_mcbsp_ops *ops;
322 char const *clk_name;
323};
324
325struct omap_mcbsp {
326 struct device *dev;
327 u32 io_base;
328 u8 id;
329 u8 free;
330 omap_mcbsp_word_length rx_word_length;
331 omap_mcbsp_word_length tx_word_length;
332
333 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
334 /* IRQ based TX/RX */
335 int rx_irq;
336 int tx_irq;
337
338 /* DMA stuff */
339 u8 dma_rx_sync;
340 short dma_rx_lch;
341 u8 dma_tx_sync;
342 short dma_tx_lch;
343
344 /* Completion queues */
345 struct completion tx_irq_completion;
346 struct completion rx_irq_completion;
347 struct completion tx_dma_completion;
348 struct completion rx_dma_completion;
349
350 /* Protect the field .free, while checking if the mcbsp is in use */
351 spinlock_t lock;
352 struct omap_mcbsp_platform_data *pdata;
353 struct clk *clk;
354};
355
356int omap_mcbsp_init(void);
357void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
358 int size);
359void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
360int omap_mcbsp_request(unsigned int id);
361void omap_mcbsp_free(unsigned int id);
362void omap_mcbsp_start(unsigned int id);
363void omap_mcbsp_stop(unsigned int id);
364void omap_mcbsp_xmit_word(unsigned int id, u32 word);
365u32 omap_mcbsp_recv_word(unsigned int id);
366
367int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
368int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
369int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
370int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
371
372
373/* SPI specific API */
374void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
375
376/* Polled read/write functions */
377int omap_mcbsp_pollread(unsigned int id, u16 * buf);
378int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
379
380#endif
diff --git a/include/asm-arm/arch-omap/mcspi.h b/include/asm-arm/arch-omap/mcspi.h
deleted file mode 100644
index 1254e4945b6f..000000000000
--- a/include/asm-arm/arch-omap/mcspi.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef _OMAP2_MCSPI_H
2#define _OMAP2_MCSPI_H
3
4struct omap2_mcspi_platform_config {
5 unsigned short num_cs;
6};
7
8struct omap2_mcspi_device_config {
9 unsigned turbo_mode:1;
10
11 /* Do we want one channel enabled at the same time? */
12 unsigned single_channel:1;
13};
14
15#endif
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
deleted file mode 100644
index 14cba97c18ad..000000000000
--- a/include/asm-arm/arch-omap/memory.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/memory.h
3 *
4 * Memory map for OMAP-1510 and 1610
5 *
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * This file was derived from linux/include/asm-arm/arch-intergrator/memory.h
10 * Copyright (C) 1999 ARM Limited
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#ifndef __ASM_ARCH_MEMORY_H
34#define __ASM_ARCH_MEMORY_H
35
36/*
37 * Physical DRAM offset.
38 */
39#if defined(CONFIG_ARCH_OMAP1)
40#define PHYS_OFFSET UL(0x10000000)
41#elif defined(CONFIG_ARCH_OMAP2)
42#define PHYS_OFFSET UL(0x80000000)
43#endif
44
45/*
46 * Conversion between SDRAM and fake PCI bus, used by USB
47 * NOTE: Physical address must be converted to Local Bus address
48 * on OMAP-1510 only
49 */
50
51/*
52 * Bus address is physical address, except for OMAP-1510 Local Bus.
53 */
54#define __virt_to_bus(x) __virt_to_phys(x)
55#define __bus_to_virt(x) __phys_to_virt(x)
56
57/*
58 * OMAP-1510 bus address is translated into a Local Bus address if the
59 * OMAP bus type is lbus. We do the address translation based on the
60 * device overriding the defaults used in the dma-mapping API.
61 * Note that the is_lbus_device() test is not very efficient on 1510
62 * because of the strncmp().
63 */
64#ifdef CONFIG_ARCH_OMAP15XX
65
66/*
67 * OMAP-1510 Local Bus address offset
68 */
69#define OMAP1510_LB_OFFSET UL(0x30000000)
70
71#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
72#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
73#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev->bus_id, "ohci", 4) == 0))
74
75#define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \
76 (dma_addr_t)virt_to_lbus(page_address(page)) : \
77 (dma_addr_t)__virt_to_bus(page_address(page));})
78
79#define __arch_dma_to_virt(dev, addr) ({is_lbus_device(dev) ? \
80 lbus_to_virt(addr) : \
81 __bus_to_virt(addr);})
82
83#define __arch_virt_to_dma(dev, addr) ({is_lbus_device(dev) ? \
84 virt_to_lbus(addr) : \
85 __virt_to_bus(addr);})
86
87#endif /* CONFIG_ARCH_OMAP15XX */
88
89/* Override the ARM default */
90#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
91
92#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
93#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
94#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
95#endif
96
97#define CONSISTENT_DMA_SIZE \
98 (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
99
100#endif
101
102#endif
103
diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h
deleted file mode 100644
index 69ed7ee40179..000000000000
--- a/include/asm-arm/arch-omap/menelaus.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/menelaus.h
3 *
4 * Functions to access Menelaus power management chip
5 */
6
7#ifndef __ASM_ARCH_MENELAUS_H
8#define __ASM_ARCH_MENELAUS_H
9
10struct device;
11
12struct menelaus_platform_data {
13 int (* late_init)(struct device *dev);
14};
15
16extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
17 void *data);
18extern void menelaus_unregister_mmc_callback(void);
19extern int menelaus_set_mmc_opendrain(int slot, int enable);
20extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
21
22extern int menelaus_set_vmem(unsigned int mV);
23extern int menelaus_set_vio(unsigned int mV);
24extern int menelaus_set_vmmc(unsigned int mV);
25extern int menelaus_set_vaux(unsigned int mV);
26extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
27extern int menelaus_set_slot_sel(int enable);
28extern int menelaus_get_slot_pin_states(void);
29extern int menelaus_set_vcore_sw(unsigned int mV);
30extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
31
32#define EN_VPLL_SLEEP (1 << 7)
33#define EN_VMMC_SLEEP (1 << 6)
34#define EN_VAUX_SLEEP (1 << 5)
35#define EN_VIO_SLEEP (1 << 4)
36#define EN_VMEM_SLEEP (1 << 3)
37#define EN_DC3_SLEEP (1 << 2)
38#define EN_DC2_SLEEP (1 << 1)
39#define EN_VC_SLEEP (1 << 0)
40
41extern int menelaus_set_regulator_sleep(int enable, u32 val);
42
43#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
44#define omap_has_menelaus() 1
45#else
46#define omap_has_menelaus() 0
47#endif
48
49#endif
diff --git a/include/asm-arm/arch-omap/mmc.h b/include/asm-arm/arch-omap/mmc.h
deleted file mode 100644
index 7cfc5f258560..000000000000
--- a/include/asm-arm/arch-omap/mmc.h
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * MMC definitions for OMAP2
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_MMC_H
12#define __OMAP2_MMC_H
13
14#include <linux/types.h>
15#include <linux/device.h>
16#include <linux/mmc/host.h>
17
18#include <asm/arch/board.h>
19
20#define OMAP_MMC_MAX_SLOTS 2
21
22struct omap_mmc_platform_data {
23 struct omap_mmc_conf conf;
24
25 /* number of slots on board */
26 unsigned nr_slots:2;
27
28 /* set if your board has components or wiring that limits the
29 * maximum frequency on the MMC bus */
30 unsigned int max_freq;
31
32 /* switch the bus to a new slot */
33 int (* switch_slot)(struct device *dev, int slot);
34 /* initialize board-specific MMC functionality, can be NULL if
35 * not supported */
36 int (* init)(struct device *dev);
37 void (* cleanup)(struct device *dev);
38 void (* shutdown)(struct device *dev);
39
40 /* To handle board related suspend/resume functionality for MMC */
41 int (*suspend)(struct device *dev, int slot);
42 int (*resume)(struct device *dev, int slot);
43
44 struct omap_mmc_slot_data {
45 int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
46 int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
47 int (* get_ro)(struct device *dev, int slot);
48
49 /* return MMC cover switch state, can be NULL if not supported.
50 *
51 * possible return values:
52 * 0 - open
53 * 1 - closed
54 */
55 int (* get_cover_state)(struct device *dev, int slot);
56
57 const char *name;
58 u32 ocr_mask;
59
60 /* Card detection IRQs */
61 int card_detect_irq;
62 int (* card_detect)(int irq);
63
64 unsigned int ban_openended:1;
65
66 } slots[OMAP_MMC_MAX_SLOTS];
67};
68
69extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info);
70
71/* called from board-specific card detection service routine */
72extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
73
74#endif
diff --git a/include/asm-arm/arch-omap/mtd-xip.h b/include/asm-arm/arch-omap/mtd-xip.h
deleted file mode 100644
index f4714b5270d0..000000000000
--- a/include/asm-arm/arch-omap/mtd-xip.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions.
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Author: Vladimir Barinov <vbarinov@ru.mvista.com>
7 *
8 * (c) 2005 MontaVista Software, Inc. This file is licensed under the
9 * terms of the GNU General Public License version 2. This program is
10 * licensed "as is" without any warranty of any kind, whether express or
11 * implied.
12 */
13
14#ifndef __ARCH_OMAP_MTD_XIP_H__
15#define __ARCH_OMAP_MTD_XIP_H__
16
17#include <asm/arch/hardware.h>
18#define OMAP_MPU_TIMER_BASE (0xfffec500)
19#define OMAP_MPU_TIMER_OFFSET 0x100
20
21typedef struct {
22 u32 cntl; /* CNTL_TIMER, R/W */
23 u32 load_tim; /* LOAD_TIM, W */
24 u32 read_tim; /* READ_TIM, R */
25} xip_omap_mpu_timer_regs_t;
26
27#define xip_omap_mpu_timer_base(n) \
28((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
29 (n)*OMAP_MPU_TIMER_OFFSET))
30
31static inline unsigned long xip_omap_mpu_timer_read(int nr)
32{
33 volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr);
34 return timer->read_tim;
35}
36
37#define xip_irqpending() \
38 (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
39#define xip_currtime() (~xip_omap_mpu_timer_read(0))
40
41/*
42 * It's permitted to do approxmation for xip_elapsed_since macro
43 * (see linux/mtd/xip.h)
44 */
45
46#ifdef CONFIG_MACH_OMAP_PERSEUS2
47#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
48#else
49#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
50#endif
51
52/*
53 * xip_cpu_idle() is used when waiting for a delay equal or larger than
54 * the system timer tick period. This should put the CPU into idle mode
55 * to save power and to be woken up only when some interrupts are pending.
56 * As above, this should not rely upon standard kernel code.
57 */
58
59#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
60
61#endif /* __ARCH_OMAP_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
deleted file mode 100644
index ff9a5b5575fd..000000000000
--- a/include/asm-arm/arch-omap/mux.h
+++ /dev/null
@@ -1,615 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/mux.h
3 *
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
6 *
7 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
8 * Copyright (C) 2003 - 2008 Nokia Corporation
9 *
10 * Written by Tony Lindgren
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * NOTE: Please use the following naming style for new pin entries.
27 * For example, W8_1610_MMC2_DAT0, where:
28 * - W8 = ball
29 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
30 * - MMC2_DAT0 = function
31 */
32
33#ifndef __ASM_ARCH_MUX_H
34#define __ASM_ARCH_MUX_H
35
36#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
37#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
38
39#ifdef CONFIG_OMAP_MUX_DEBUG
40#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
41 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mask_offset = mode_offset, \
43 .mask = mode,
44
45#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
46 .pull_reg = PULL_DWN_CTRL_##reg, \
47 .pull_bit = bit, \
48 .pull_val = status,
49
50#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
51 .pu_pd_reg = PU_PD_SEL_##reg, \
52 .pu_pd_val = status,
53
54#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
55 .mux_reg = OMAP730_IO_CONF_##reg, \
56 .mask_offset = mode_offset, \
57 .mask = mode,
58
59#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
60 .pull_reg = OMAP730_IO_CONF_##reg, \
61 .pull_bit = bit, \
62 .pull_val = status,
63
64#else
65
66#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
67 .mask_offset = mode_offset, \
68 .mask = mode,
69
70#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
71 .pull_bit = bit, \
72 .pull_val = status,
73
74#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
75 .pu_pd_val = status,
76
77#define MUX_REG_730(reg, mode_offset, mode) \
78 .mux_reg = OMAP730_IO_CONF_##reg, \
79 .mask_offset = mode_offset, \
80 .mask = mode,
81
82#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
83 .pull_bit = bit, \
84 .pull_val = status,
85
86#endif /* CONFIG_OMAP_MUX_DEBUG */
87
88#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
89 pull_reg, pull_bit, pull_status, \
90 pu_pd_reg, pu_pd_status, debug_status) \
91{ \
92 .name = desc, \
93 .debug = debug_status, \
94 MUX_REG(mux_reg, mode_offset, mode) \
95 PULL_REG(pull_reg, pull_bit, pull_status) \
96 PU_PD_REG(pu_pd_reg, pu_pd_status) \
97},
98
99
100/*
101 * OMAP730 has a slightly different config for the pin mux.
102 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
103 * not the FUNC_MUX_CTRL_x regs from hardware.h
104 * - for pull-up/down, only has one enable bit which is is in the same register
105 * as mux config
106 */
107#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
108 pull_bit, pull_status, debug_status)\
109{ \
110 .name = desc, \
111 .debug = debug_status, \
112 MUX_REG_730(mux_reg, mode_offset, mode) \
113 PULL_REG_730(mux_reg, pull_bit, pull_status) \
114 PU_PD_REG(NA, 0) \
115},
116
117#define MUX_CFG_24XX(desc, reg_offset, mode, \
118 pull_en, pull_mode, dbg) \
119{ \
120 .name = desc, \
121 .debug = dbg, \
122 .mux_reg = reg_offset, \
123 .mask = mode, \
124 .pull_val = pull_en, \
125 .pu_pd_val = pull_mode, \
126},
127
128
129#define PULL_DISABLED 0
130#define PULL_ENABLED 1
131
132#define PULL_DOWN 0
133#define PULL_UP 1
134
135struct pin_config {
136 char *name;
137 unsigned char busy;
138 unsigned char debug;
139
140 const char *mux_reg_name;
141 const unsigned int mux_reg;
142 const unsigned char mask_offset;
143 const unsigned char mask;
144
145 const char *pull_name;
146 const unsigned int pull_reg;
147 const unsigned char pull_val;
148 const unsigned char pull_bit;
149
150 const char *pu_pd_name;
151 const unsigned int pu_pd_reg;
152 const unsigned char pu_pd_val;
153};
154
155enum omap730_index {
156 /* OMAP 730 keyboard */
157 E2_730_KBR0,
158 J7_730_KBR1,
159 E1_730_KBR2,
160 F3_730_KBR3,
161 D2_730_KBR4,
162 C2_730_KBC0,
163 D3_730_KBC1,
164 E4_730_KBC2,
165 F4_730_KBC3,
166 E3_730_KBC4,
167
168 /* USB */
169 AA17_730_USB_DM,
170 W16_730_USB_PU_EN,
171 W17_730_USB_VBUSI,
172};
173
174enum omap1xxx_index {
175 /* UART1 (BT_UART_GATING)*/
176 UART1_TX = 0,
177 UART1_RTS,
178
179 /* UART2 (COM_UART_GATING)*/
180 UART2_TX,
181 UART2_RX,
182 UART2_CTS,
183 UART2_RTS,
184
185 /* UART3 (GIGA_UART_GATING) */
186 UART3_TX,
187 UART3_RX,
188 UART3_CTS,
189 UART3_RTS,
190 UART3_CLKREQ,
191 UART3_BCLK, /* 12MHz clock out */
192 Y15_1610_UART3_RTS,
193
194 /* PWT & PWL */
195 PWT,
196 PWL,
197
198 /* USB master generic */
199 R18_USB_VBUS,
200 R18_1510_USB_GPIO0,
201 W4_USB_PUEN,
202 W4_USB_CLKO,
203 W4_USB_HIGHZ,
204 W4_GPIO58,
205
206 /* USB1 master */
207 USB1_SUSP,
208 USB1_SEO,
209 W13_1610_USB1_SE0,
210 USB1_TXEN,
211 USB1_TXD,
212 USB1_VP,
213 USB1_VM,
214 USB1_RCV,
215 USB1_SPEED,
216 R13_1610_USB1_SPEED,
217 R13_1710_USB1_SE0,
218
219 /* USB2 master */
220 USB2_SUSP,
221 USB2_VP,
222 USB2_TXEN,
223 USB2_VM,
224 USB2_RCV,
225 USB2_SEO,
226 USB2_TXD,
227
228 /* OMAP-1510 GPIO */
229 R18_1510_GPIO0,
230 R19_1510_GPIO1,
231 M14_1510_GPIO2,
232
233 /* OMAP1610 GPIO */
234 P18_1610_GPIO3,
235 Y15_1610_GPIO17,
236
237 /* OMAP-1710 GPIO */
238 R18_1710_GPIO0,
239 V2_1710_GPIO10,
240 N21_1710_GPIO14,
241 W15_1710_GPIO40,
242
243 /* MPUIO */
244 MPUIO2,
245 N15_1610_MPUIO2,
246 MPUIO4,
247 MPUIO5,
248 T20_1610_MPUIO5,
249 W11_1610_MPUIO6,
250 V10_1610_MPUIO7,
251 W11_1610_MPUIO9,
252 V10_1610_MPUIO10,
253 W10_1610_MPUIO11,
254 E20_1610_MPUIO13,
255 U20_1610_MPUIO14,
256 E19_1610_MPUIO15,
257
258 /* MCBSP2 */
259 MCBSP2_CLKR,
260 MCBSP2_CLKX,
261 MCBSP2_DR,
262 MCBSP2_DX,
263 MCBSP2_FSR,
264 MCBSP2_FSX,
265
266 /* MCBSP3 */
267 MCBSP3_CLKX,
268
269 /* Misc ballouts */
270 BALLOUT_V8_ARMIO3,
271 N20_HDQ,
272
273 /* OMAP-1610 MMC2 */
274 W8_1610_MMC2_DAT0,
275 V8_1610_MMC2_DAT1,
276 W15_1610_MMC2_DAT2,
277 R10_1610_MMC2_DAT3,
278 Y10_1610_MMC2_CLK,
279 Y8_1610_MMC2_CMD,
280 V9_1610_MMC2_CMDDIR,
281 V5_1610_MMC2_DATDIR0,
282 W19_1610_MMC2_DATDIR1,
283 R18_1610_MMC2_CLKIN,
284
285 /* OMAP-1610 External Trace Interface */
286 M19_1610_ETM_PSTAT0,
287 L15_1610_ETM_PSTAT1,
288 L18_1610_ETM_PSTAT2,
289 L19_1610_ETM_D0,
290 J19_1610_ETM_D6,
291 J18_1610_ETM_D7,
292
293 /* OMAP16XX GPIO */
294 P20_1610_GPIO4,
295 V9_1610_GPIO7,
296 W8_1610_GPIO9,
297 N20_1610_GPIO11,
298 N19_1610_GPIO13,
299 P10_1610_GPIO22,
300 V5_1610_GPIO24,
301 AA20_1610_GPIO_41,
302 W19_1610_GPIO48,
303 M7_1610_GPIO62,
304 V14_16XX_GPIO37,
305 R9_16XX_GPIO18,
306 L14_16XX_GPIO49,
307
308 /* OMAP-1610 uWire */
309 V19_1610_UWIRE_SCLK,
310 U18_1610_UWIRE_SDI,
311 W21_1610_UWIRE_SDO,
312 N14_1610_UWIRE_CS0,
313 P15_1610_UWIRE_CS3,
314 N15_1610_UWIRE_CS1,
315
316 /* OMAP-1610 SPI */
317 U19_1610_SPIF_SCK,
318 U18_1610_SPIF_DIN,
319 P20_1610_SPIF_DIN,
320 W21_1610_SPIF_DOUT,
321 R18_1610_SPIF_DOUT,
322 N14_1610_SPIF_CS0,
323 N15_1610_SPIF_CS1,
324 T19_1610_SPIF_CS2,
325 P15_1610_SPIF_CS3,
326
327 /* OMAP-1610 Flash */
328 L3_1610_FLASH_CS2B_OE,
329 M8_1610_FLASH_CS2B_WE,
330
331 /* First MMC */
332 MMC_CMD,
333 MMC_DAT1,
334 MMC_DAT2,
335 MMC_DAT0,
336 MMC_CLK,
337 MMC_DAT3,
338
339 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
340 M15_1710_MMC_CLKI,
341 P19_1710_MMC_CMDDIR,
342 P20_1710_MMC_DATDIR0,
343
344 /* OMAP-1610 USB0 alternate pin configuration */
345 W9_USB0_TXEN,
346 AA9_USB0_VP,
347 Y5_USB0_RCV,
348 R9_USB0_VM,
349 V6_USB0_TXD,
350 W5_USB0_SE0,
351 V9_USB0_SPEED,
352 V9_USB0_SUSP,
353
354 /* USB2 */
355 W9_USB2_TXEN,
356 AA9_USB2_VP,
357 Y5_USB2_RCV,
358 R9_USB2_VM,
359 V6_USB2_TXD,
360 W5_USB2_SE0,
361
362 /* 16XX UART */
363 R13_1610_UART1_TX,
364 V14_16XX_UART1_RX,
365 R14_1610_UART1_CTS,
366 AA15_1610_UART1_RTS,
367 R9_16XX_UART2_RX,
368 L14_16XX_UART3_RX,
369
370 /* I2C OMAP-1610 */
371 I2C_SCL,
372 I2C_SDA,
373
374 /* Keypad */
375 F18_1610_KBC0,
376 D20_1610_KBC1,
377 D19_1610_KBC2,
378 E18_1610_KBC3,
379 C21_1610_KBC4,
380 G18_1610_KBR0,
381 F19_1610_KBR1,
382 H14_1610_KBR2,
383 E20_1610_KBR3,
384 E19_1610_KBR4,
385 N19_1610_KBR5,
386
387 /* Power management */
388 T20_1610_LOW_PWR,
389
390 /* MCLK Settings */
391 V5_1710_MCLK_ON,
392 V5_1710_MCLK_OFF,
393 R10_1610_MCLK_ON,
394 R10_1610_MCLK_OFF,
395
396 /* CompactFlash controller */
397 P11_1610_CF_CD2,
398 R11_1610_CF_IOIS16,
399 V10_1610_CF_IREQ,
400 W10_1610_CF_RESET,
401 W11_1610_CF_CD1,
402
403 /* parallel camera */
404 J15_1610_CAM_LCLK,
405 J18_1610_CAM_D7,
406 J19_1610_CAM_D6,
407 J14_1610_CAM_D5,
408 K18_1610_CAM_D4,
409 K19_1610_CAM_D3,
410 K15_1610_CAM_D2,
411 K14_1610_CAM_D1,
412 L19_1610_CAM_D0,
413 L18_1610_CAM_VS,
414 L15_1610_CAM_HS,
415 M19_1610_CAM_RSTZ,
416 Y15_1610_CAM_OUTCLK,
417
418 /* serial camera */
419 H19_1610_CAM_EXCLK,
420 Y12_1610_CCP_CLKP,
421 W13_1610_CCP_CLKM,
422 W14_1610_CCP_DATAP,
423 Y14_1610_CCP_DATAM,
424
425};
426
427enum omap24xx_index {
428 /* 24xx I2C */
429 M19_24XX_I2C1_SCL,
430 L15_24XX_I2C1_SDA,
431 J15_24XX_I2C2_SCL,
432 H19_24XX_I2C2_SDA,
433
434 /* 24xx Menelaus interrupt */
435 W19_24XX_SYS_NIRQ,
436
437 /* 24xx clock */
438 W14_24XX_SYS_CLKOUT,
439
440 /* 24xx GPMC chipselects, wait pin monitoring */
441 E2_GPMC_NCS2,
442 L2_GPMC_NCS7,
443 L3_GPMC_WAIT0,
444 N7_GPMC_WAIT1,
445 M1_GPMC_WAIT2,
446 P1_GPMC_WAIT3,
447
448 /* 242X McBSP */
449 Y15_24XX_MCBSP2_CLKX,
450 R14_24XX_MCBSP2_FSX,
451 W15_24XX_MCBSP2_DR,
452 V15_24XX_MCBSP2_DX,
453
454 /* 24xx GPIO */
455 M21_242X_GPIO11,
456 P21_242X_GPIO12,
457 AA10_242X_GPIO13,
458 AA6_242X_GPIO14,
459 AA4_242X_GPIO15,
460 Y11_242X_GPIO16,
461 AA12_242X_GPIO17,
462 AA8_242X_GPIO58,
463 Y20_24XX_GPIO60,
464 W4__24XX_GPIO74,
465 N15_24XX_GPIO85,
466 M15_24XX_GPIO92,
467 P20_24XX_GPIO93,
468 P18_24XX_GPIO95,
469 M18_24XX_GPIO96,
470 L14_24XX_GPIO97,
471 J15_24XX_GPIO99,
472 V14_24XX_GPIO117,
473 P14_24XX_GPIO125,
474
475 /* 242x DBG GPIO */
476 V4_242X_GPIO49,
477 W2_242X_GPIO50,
478 U4_242X_GPIO51,
479 V3_242X_GPIO52,
480 V2_242X_GPIO53,
481 V6_242X_GPIO53,
482 T4_242X_GPIO54,
483 Y4_242X_GPIO54,
484 T3_242X_GPIO55,
485 U2_242X_GPIO56,
486
487 /* 24xx external DMA requests */
488 AA10_242X_DMAREQ0,
489 AA6_242X_DMAREQ1,
490 E4_242X_DMAREQ2,
491 G4_242X_DMAREQ3,
492 D3_242X_DMAREQ4,
493 E3_242X_DMAREQ5,
494
495 /* UART3 */
496 K15_24XX_UART3_TX,
497 K14_24XX_UART3_RX,
498
499 /* MMC/SDIO */
500 G19_24XX_MMC_CLKO,
501 H18_24XX_MMC_CMD,
502 F20_24XX_MMC_DAT0,
503 H14_24XX_MMC_DAT1,
504 E19_24XX_MMC_DAT2,
505 D19_24XX_MMC_DAT3,
506 F19_24XX_MMC_DAT_DIR0,
507 E20_24XX_MMC_DAT_DIR1,
508 F18_24XX_MMC_DAT_DIR2,
509 E18_24XX_MMC_DAT_DIR3,
510 G18_24XX_MMC_CMD_DIR,
511 H15_24XX_MMC_CLKI,
512
513 /* Full speed USB */
514 J20_24XX_USB0_PUEN,
515 J19_24XX_USB0_VP,
516 K20_24XX_USB0_VM,
517 J18_24XX_USB0_RCV,
518 K19_24XX_USB0_TXEN,
519 J14_24XX_USB0_SE0,
520 K18_24XX_USB0_DAT,
521
522 N14_24XX_USB1_SE0,
523 W12_24XX_USB1_SE0,
524 P15_24XX_USB1_DAT,
525 R13_24XX_USB1_DAT,
526 W20_24XX_USB1_TXEN,
527 P13_24XX_USB1_TXEN,
528 V19_24XX_USB1_RCV,
529 V12_24XX_USB1_RCV,
530
531 AA10_24XX_USB2_SE0,
532 Y11_24XX_USB2_DAT,
533 AA12_24XX_USB2_TXEN,
534 AA6_24XX_USB2_RCV,
535 AA4_24XX_USB2_TLLSE0,
536
537 /* Keypad GPIO*/
538 T19_24XX_KBR0,
539 R19_24XX_KBR1,
540 V18_24XX_KBR2,
541 M21_24XX_KBR3,
542 E5__24XX_KBR4,
543 M18_24XX_KBR5,
544 R20_24XX_KBC0,
545 M14_24XX_KBC1,
546 H19_24XX_KBC2,
547 V17_24XX_KBC3,
548 P21_24XX_KBC4,
549 L14_24XX_KBC5,
550 N19_24XX_KBC6,
551
552 /* 24xx Menelaus Keypad GPIO */
553 B3__24XX_KBR5,
554 AA4_24XX_KBC2,
555 B13_24XX_KBC6,
556
557 /* 2430 USB */
558 AD9_2430_USB0_PUEN,
559 Y11_2430_USB0_VP,
560 AD7_2430_USB0_VM,
561 AE7_2430_USB0_RCV,
562 AD4_2430_USB0_TXEN,
563 AF9_2430_USB0_SE0,
564 AE6_2430_USB0_DAT,
565 AD24_2430_USB1_SE0,
566 AB24_2430_USB1_RCV,
567 Y25_2430_USB1_TXEN,
568 AA26_2430_USB1_DAT,
569
570 /* 2430 HS-USB */
571 AD9_2430_USB0HS_DATA3,
572 Y11_2430_USB0HS_DATA4,
573 AD7_2430_USB0HS_DATA5,
574 AE7_2430_USB0HS_DATA6,
575 AD4_2430_USB0HS_DATA2,
576 AF9_2430_USB0HS_DATA0,
577 AE6_2430_USB0HS_DATA1,
578 AE8_2430_USB0HS_CLK,
579 AD8_2430_USB0HS_DIR,
580 AE5_2430_USB0HS_STP,
581 AE9_2430_USB0HS_NXT,
582 AC7_2430_USB0HS_DATA7,
583
584 /* 2430 McBSP */
585 AC10_2430_MCBSP2_FSX,
586 AD16_2430_MCBSP2_CLX,
587 AE13_2430_MCBSP2_DX,
588 AD13_2430_MCBSP2_DR,
589 AC10_2430_MCBSP2_FSX_OFF,
590 AD16_2430_MCBSP2_CLX_OFF,
591 AE13_2430_MCBSP2_DX_OFF,
592 AD13_2430_MCBSP2_DR_OFF,
593
594};
595
596struct omap_mux_cfg {
597 struct pin_config *pins;
598 unsigned long size;
599 int (*cfg_reg)(const struct pin_config *cfg);
600};
601
602#ifdef CONFIG_OMAP_MUX
603/* setup pin muxing in Linux */
604extern int omap1_mux_init(void);
605extern int omap2_mux_init(void);
606extern int omap_mux_register(struct omap_mux_cfg *);
607extern int omap_cfg_reg(unsigned long reg_cfg);
608#else
609/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
610static inline int omap1_mux_init(void) { return 0; }
611static inline int omap2_mux_init(void) { return 0; }
612static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
613#endif
614
615#endif
diff --git a/include/asm-arm/arch-omap/nand.h b/include/asm-arm/arch-omap/nand.h
deleted file mode 100644
index 17ae26e35353..000000000000
--- a/include/asm-arm/arch-omap/nand.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * include/asm-arm/arch-omap/nand.h
3 *
4 * Copyright (C) 2006 Micron Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/mtd/partitions.h>
12
13struct omap_nand_platform_data {
14 unsigned int options;
15 int cs;
16 int gpio_irq;
17 struct mtd_partition *parts;
18 int nr_parts;
19 int (*nand_setup)(void __iomem *);
20 int (*dev_ready)(struct omap_nand_platform_data *);
21 int dma_channel;
22 void __iomem *gpmc_cs_baseaddr;
23 void __iomem *gpmc_baseaddr;
24};
diff --git a/include/asm-arm/arch-omap/omap-alsa.h b/include/asm-arm/arch-omap/omap-alsa.h
deleted file mode 100644
index faa0ed23d4ba..000000000000
--- a/include/asm-arm/arch-omap/omap-alsa.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/omap-alsa.h
3 *
4 * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
5 *
6 * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
7 *
8 * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
9 * Written by Daniel Petrini, David Cohen, Anderson Briglia
10 * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 * History
33 * -------
34 *
35 * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk,
36 * original version based in sa1100 driver
37 * and omap oss driver.
38 */
39
40#ifndef __OMAP_ALSA_H
41#define __OMAP_ALSA_H
42
43#include <asm/arch/dma.h>
44#include <sound/core.h>
45#include <sound/pcm.h>
46#include <asm/arch/mcbsp.h>
47#include <linux/platform_device.h>
48
49#define DMA_BUF_SIZE (1024 * 8)
50
51/*
52 * Buffer management for alsa and dma
53 */
54struct audio_stream {
55 char *id; /* identification string */
56 int stream_id; /* numeric identification */
57 int dma_dev; /* dma number of that device */
58 int *lch; /* Chain of channels this stream is linked to */
59 char started; /* to store if the chain was started or not */
60 int dma_q_head; /* DMA Channel Q Head */
61 int dma_q_tail; /* DMA Channel Q Tail */
62 char dma_q_count; /* DMA Channel Q Count */
63 int active:1; /* we are using this stream for transfer now */
64 int period; /* current transfer period */
65 int periods; /* current count of periods registerd in the DMA engine */
66 spinlock_t dma_lock; /* for locking in DMA operations */
67 struct snd_pcm_substream *stream; /* the pcm stream */
68 unsigned linked:1; /* dma channels linked */
69 int offset; /* store start position of the last period in the alsa buffer */
70 int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */
71 int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */
72};
73
74/*
75 * Alsa card structure for aic23
76 */
77struct snd_card_omap_codec {
78 struct snd_card *card;
79 struct snd_pcm *pcm;
80 long samplerate;
81 struct audio_stream s[2]; /* playback & capture */
82};
83
84/* Codec specific information and function pointers.
85 * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
86 * are responsible for defining the function pointers.
87 */
88struct omap_alsa_codec_config {
89 char *name;
90 struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
91 struct snd_pcm_hw_constraint_list *hw_constraints_rates;
92 struct snd_pcm_hardware *snd_omap_alsa_playback;
93 struct snd_pcm_hardware *snd_omap_alsa_capture;
94 void (*codec_configure_dev)(void);
95 void (*codec_set_samplerate)(long);
96 void (*codec_clock_setup)(void);
97 int (*codec_clock_on)(void);
98 int (*codec_clock_off)(void);
99 int (*get_default_samplerate)(void);
100};
101
102/*********** Mixer function prototypes *************************/
103int snd_omap_mixer(struct snd_card_omap_codec *);
104void snd_omap_init_mixer(void);
105
106#ifdef CONFIG_PM
107void snd_omap_suspend_mixer(void);
108void snd_omap_resume_mixer(void);
109#endif
110
111int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
112int snd_omap_alsa_remove(struct platform_device *pdev);
113#ifdef CONFIG_PM
114int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
115int snd_omap_alsa_resume(struct platform_device *pdev);
116#else
117#define snd_omap_alsa_suspend NULL
118#define snd_omap_alsa_resume NULL
119#endif
120
121void callback_omap_alsa_sound_dma(void *);
122
123#endif
diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h
deleted file mode 100644
index c575d354850f..000000000000
--- a/include/asm-arm/arch-omap/omap1510.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/* linux/include/asm-arm/arch-omap/omap1510.h
2 *
3 * Hardware definitions for TI OMAP1510 processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP15XX_H
29#define __ASM_ARCH_OMAP15XX_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP1510_DSP_BASE 0xE0000000
40#define OMAP1510_DSP_SIZE 0x28000
41#define OMAP1510_DSP_START 0xE0000000
42
43#define OMAP1510_DSPREG_BASE 0xE1000000
44#define OMAP1510_DSPREG_SIZE SZ_128K
45#define OMAP1510_DSPREG_START 0xE1000000
46
47#endif /* __ASM_ARCH_OMAP15XX_H */
48
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
deleted file mode 100644
index f7f5cdfdccce..000000000000
--- a/include/asm-arm/arch-omap/omap16xx.h
+++ /dev/null
@@ -1,197 +0,0 @@
1/* linux/include/asm-arm/arch-omap/omap16xx.h
2 *
3 * Hardware definitions for TI OMAP1610/5912/1710 processors.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP16XX_H
29#define __ASM_ARCH_OMAP16XX_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP16XX_DSP_BASE 0xE0000000
40#define OMAP16XX_DSP_SIZE 0x28000
41#define OMAP16XX_DSP_START 0xE0000000
42
43#define OMAP16XX_DSPREG_BASE 0xE1000000
44#define OMAP16XX_DSPREG_SIZE SZ_128K
45#define OMAP16XX_DSPREG_START 0xE1000000
46
47/*
48 * ---------------------------------------------------------------------------
49 * Interrupts
50 * ---------------------------------------------------------------------------
51 */
52#define OMAP_IH2_0_BASE (0xfffe0000)
53#define OMAP_IH2_1_BASE (0xfffe0100)
54#define OMAP_IH2_2_BASE (0xfffe0200)
55#define OMAP_IH2_3_BASE (0xfffe0300)
56
57#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
58#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
59#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
60#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
61#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
62#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
63#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
64
65#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
66#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
67#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
68#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
69#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
70#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
71#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
72
73#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
74#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
75#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
76#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
77#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
78#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
79#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
80
81#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
82#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
83#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
84#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
85#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
86#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
87#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
88
89/*
90 * ----------------------------------------------------------------------------
91 * Clocks
92 * ----------------------------------------------------------------------------
93 */
94#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
95
96/*
97 * ----------------------------------------------------------------------------
98 * Pin configuration registers
99 * ----------------------------------------------------------------------------
100 */
101#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
102#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
103#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
104#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
105#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
106
107/*
108 * ----------------------------------------------------------------------------
109 * System control registers
110 * ----------------------------------------------------------------------------
111 */
112#define OMAP1610_RESET_CONTROL 0xfffe1140
113
114/*
115 * ---------------------------------------------------------------------------
116 * TIPB bus interface
117 * ---------------------------------------------------------------------------
118 */
119#define TIPB_SWITCH_BASE (0xfffbc800)
120#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
121
122/* UART3 Registers Maping through MPU bus */
123#define UART3_RHR (OMAP_UART3_BASE + 0)
124#define UART3_THR (OMAP_UART3_BASE + 0)
125#define UART3_DLL (OMAP_UART3_BASE + 0)
126#define UART3_IER (OMAP_UART3_BASE + 4)
127#define UART3_DLH (OMAP_UART3_BASE + 4)
128#define UART3_IIR (OMAP_UART3_BASE + 8)
129#define UART3_FCR (OMAP_UART3_BASE + 8)
130#define UART3_EFR (OMAP_UART3_BASE + 8)
131#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
132#define UART3_MCR (OMAP_UART3_BASE + 0x10)
133#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
134#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
135#define UART3_LSR (OMAP_UART3_BASE + 0x14)
136#define UART3_TCR (OMAP_UART3_BASE + 0x18)
137#define UART3_MSR (OMAP_UART3_BASE + 0x18)
138#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
139#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
140#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
141#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
142#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
143#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
144#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
145#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
146#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
147#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
148#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
149#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
150#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
151#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
152#define UART3_BLR (OMAP_UART3_BASE + 0x38)
153#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
154#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
155#define UART3_SCR (OMAP_UART3_BASE + 0x40)
156#define UART3_SSR (OMAP_UART3_BASE + 0x44)
157#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
158#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
159#define UART3_MVR (OMAP_UART3_BASE + 0x50)
160
161/*
162 * ---------------------------------------------------------------------------
163 * Watchdog timer
164 * ---------------------------------------------------------------------------
165 */
166
167/* 32-bit Watchdog timer in OMAP 16XX */
168#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
169#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
170#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
171#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
172#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
173#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
174#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
175#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
176#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
177#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
178
179#define WCLR_PRE_SHIFT 5
180#define WCLR_PTV_SHIFT 2
181
182#define WWPS_W_PEND_WSPR (1 << 4)
183#define WWPS_W_PEND_WTGR (1 << 3)
184#define WWPS_W_PEND_WLDR (1 << 2)
185#define WWPS_W_PEND_WCRR (1 << 1)
186#define WWPS_W_PEND_WCLR (1 << 0)
187
188#define WSPR_ENABLE_0 (0x0000bbbb)
189#define WSPR_ENABLE_1 (0x00004444)
190#define WSPR_DISABLE_0 (0x0000aaaa)
191#define WSPR_DISABLE_1 (0x00005555)
192
193/* Mailbox */
194#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
195
196#endif /* __ASM_ARCH_OMAP16XX_H */
197
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
deleted file mode 100644
index b9fcaae287c8..000000000000
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * include/asm-arm/arch-omap/omap24xx.h
3 *
4 * This file contains the processor specific definitions
5 * of the TI OMAP24XX.
6 *
7 * Copyright (C) 2007 Texas Instruments.
8 * Copyright (C) 2007 Nokia Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP24XX_H
27#define __ASM_ARCH_OMAP24XX_H
28
29/*
30 * Please place only base defines here and put the rest in device
31 * specific headers. Note also that some of these defines are needed
32 * for omap1 to compile without adding ifdefs.
33 */
34
35#define L4_24XX_BASE 0x48000000
36#define L4_WK_243X_BASE 0x49000000
37#define L3_24XX_BASE 0x68000000
38
39/* interrupt controller */
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42#define IRQ_SIR_IRQ 0x0040
43
44#define OMAP2420_CTRL_BASE L4_24XX_BASE
45#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
46#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
47#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
48#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
49#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
50#define OMAP2420_SMS_BASE 0x68008000
51
52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
54#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
55#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
56
57#define OMAP243X_SMS_BASE 0x6C000000
58#define OMAP243X_SDRC_BASE 0x6D000000
59#define OMAP243X_GPMC_BASE 0x6E000000
60#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
61#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
62#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
63
64/* DSP SS */
65#define OMAP2420_DSP_BASE 0x58000000
66#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
67#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
68#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
69
70#define OMAP243X_DSP_BASE 0x5C000000
71#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
72#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
73
74/* Mailbox */
75#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
76
77/* Camera */
78#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
79
80/* Security */
81#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
82#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
83#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
84#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
85#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
86#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
87
88#if defined(CONFIG_ARCH_OMAP2420)
89
90#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE
91#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE
92#define OMAP2_CM_BASE OMAP2420_CM_BASE
93#define OMAP2_PRM_BASE OMAP2420_PRM_BASE
94#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
95
96#elif defined(CONFIG_ARCH_OMAP2430)
97
98#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE
99#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE
100#define OMAP2_CM_BASE OMAP2430_CM_BASE
101#define OMAP2_PRM_BASE OMAP2430_PRM_BASE
102#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
103
104#endif
105
106#endif /* __ASM_ARCH_OMAP24XX_H */
107
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
deleted file mode 100644
index aa30c6d10abd..000000000000
--- a/include/asm-arm/arch-omap/omap34xx.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * include/asm-arm/arch-omap/omap34xx.h
3 *
4 * This file contains the processor specific definitions of the TI OMAP34XX.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 * Copyright (C) 2007 Nokia Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef __ASM_ARCH_OMAP34XX_H
25#define __ASM_ARCH_OMAP34XX_H
26
27/*
28 * Please place only base defines here and put the rest in device
29 * specific headers.
30 */
31
32#define L4_34XX_BASE 0x48000000
33#define L4_WK_34XX_BASE 0x48300000
34#define L4_WK_OMAP_BASE L4_WK_34XX_BASE
35#define L4_PER_34XX_BASE 0x49000000
36#define L4_PER_OMAP_BASE L4_PER_34XX_BASE
37#define L4_EMU_34XX_BASE 0x54000000
38#define L4_EMU_BASE L4_EMU_34XX_BASE
39#define L3_34XX_BASE 0x68000000
40#define L3_OMAP_BASE L3_34XX_BASE
41
42#define OMAP3430_32KSYNCT_BASE 0x48320000
43#define OMAP3430_CM_BASE 0x48004800
44#define OMAP3430_PRM_BASE 0x48306800
45#define OMAP343X_SMS_BASE 0x6C000000
46#define OMAP343X_SDRC_BASE 0x6D000000
47#define OMAP34XX_GPMC_BASE 0x6E000000
48#define OMAP343X_SCM_BASE 0x48002000
49#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
50
51#define OMAP34XX_IC_BASE 0x48200000
52#define OMAP34XX_IVA_INTC_BASE 0x40000000
53#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
54#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
55#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
56
57
58#if defined(CONFIG_ARCH_OMAP3430)
59
60#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE
61#define OMAP2_CM_BASE OMAP3430_CM_BASE
62#define OMAP2_PRM_BASE OMAP3430_PRM_BASE
63#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
64
65#endif
66
67#define OMAP34XX_DSP_BASE 0x58000000
68#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0)
69#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000)
70#define OMAP34XX_DSP_MMU_BASE (OMAP34XX_DSP_BASE + 0x2000000)
71#endif /* __ASM_ARCH_OMAP34XX_H */
72
diff --git a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h
deleted file mode 100644
index 755b64c5e9f0..000000000000
--- a/include/asm-arm/arch-omap/omap730.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/* linux/include/asm-arm/arch-omap/omap730.h
2 *
3 * Hardware definitions for TI OMAP730 processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP730_H
29#define __ASM_ARCH_OMAP730_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP730_DSP_BASE 0xE0000000
40#define OMAP730_DSP_SIZE 0x50000
41#define OMAP730_DSP_START 0xE0000000
42
43#define OMAP730_DSPREG_BASE 0xE1000000
44#define OMAP730_DSPREG_SIZE SZ_128K
45#define OMAP730_DSPREG_START 0xE1000000
46
47/*
48 * ----------------------------------------------------------------------------
49 * OMAP730 specific configuration registers
50 * ----------------------------------------------------------------------------
51 */
52#define OMAP730_CONFIG_BASE 0xfffe1000
53#define OMAP730_IO_CONF_0 0xfffe1070
54#define OMAP730_IO_CONF_1 0xfffe1074
55#define OMAP730_IO_CONF_2 0xfffe1078
56#define OMAP730_IO_CONF_3 0xfffe107c
57#define OMAP730_IO_CONF_4 0xfffe1080
58#define OMAP730_IO_CONF_5 0xfffe1084
59#define OMAP730_IO_CONF_6 0xfffe1088
60#define OMAP730_IO_CONF_7 0xfffe108c
61#define OMAP730_IO_CONF_8 0xfffe1090
62#define OMAP730_IO_CONF_9 0xfffe1094
63#define OMAP730_IO_CONF_10 0xfffe1098
64#define OMAP730_IO_CONF_11 0xfffe109c
65#define OMAP730_IO_CONF_12 0xfffe10a0
66#define OMAP730_IO_CONF_13 0xfffe10a4
67
68#define OMAP730_MODE_1 0xfffe1010
69#define OMAP730_MODE_2 0xfffe1014
70
71/* CSMI specials: in terms of base + offset */
72#define OMAP730_MODE2_OFFSET 0x14
73
74/*
75 * ----------------------------------------------------------------------------
76 * OMAP730 traffic controller configuration registers
77 * ----------------------------------------------------------------------------
78 */
79#define OMAP730_FLASH_CFG_0 0xfffecc10
80#define OMAP730_FLASH_ACFG_0 0xfffecc50
81#define OMAP730_FLASH_CFG_1 0xfffecc14
82#define OMAP730_FLASH_ACFG_1 0xfffecc54
83
84/*
85 * ----------------------------------------------------------------------------
86 * OMAP730 DSP control registers
87 * ----------------------------------------------------------------------------
88 */
89#define OMAP730_ICR_BASE 0xfffbb800
90#define OMAP730_DSP_M_CTL 0xfffbb804
91#define OMAP730_DSP_MMU_BASE 0xfffed200
92
93/*
94 * ----------------------------------------------------------------------------
95 * OMAP730 PCC_UPLD configuration registers
96 * ----------------------------------------------------------------------------
97 */
98#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
99#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
100
101#endif /* __ASM_ARCH_OMAP730_H */
102
diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h
deleted file mode 100644
index 46d7a4f60854..000000000000
--- a/include/asm-arm/arch-omap/omapfb.h
+++ /dev/null
@@ -1,395 +0,0 @@
1/*
2 * File: include/asm-arm/arch-omap/omapfb.h
3 *
4 * Framebuffer driver for TI OMAP boards
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Author: Imre Deak <imre.deak@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef __OMAPFB_H
25#define __OMAPFB_H
26
27#include <asm/ioctl.h>
28#include <asm/types.h>
29
30/* IOCTL commands. */
31
32#define OMAP_IOW(num, dtype) _IOW('O', num, dtype)
33#define OMAP_IOR(num, dtype) _IOR('O', num, dtype)
34#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
35#define OMAP_IO(num) _IO('O', num)
36
37#define OMAPFB_MIRROR OMAP_IOW(31, int)
38#define OMAPFB_SYNC_GFX OMAP_IO(37)
39#define OMAPFB_VSYNC OMAP_IO(38)
40#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int)
41#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps)
42#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int)
43#define OMAPFB_LCD_TEST OMAP_IOW(45, int)
44#define OMAPFB_CTRL_TEST OMAP_IOW(46, int)
45#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
46#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key)
47#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key)
48#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info)
49#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info)
50#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window)
51#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info)
52#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info)
53
54#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
55#define OMAPFB_CAPS_LCDC_MASK 0x00fff000
56#define OMAPFB_CAPS_PANEL_MASK 0xff000000
57
58#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000
59#define OMAPFB_CAPS_TEARSYNC 0x00002000
60#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000
61#define OMAPFB_CAPS_PLANE_SCALE 0x00008000
62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
65#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
66
67/* Values from DSP must map to lower 16-bits */
68#define OMAPFB_FORMAT_MASK 0x00ff
69#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100
70#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200
71#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400
72#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800
73#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000
74
75#define OMAPFB_EVENT_READY 1
76#define OMAPFB_EVENT_DISABLED 2
77
78#define OMAPFB_MEMTYPE_SDRAM 0
79#define OMAPFB_MEMTYPE_SRAM 1
80#define OMAPFB_MEMTYPE_MAX 1
81
82enum omapfb_color_format {
83 OMAPFB_COLOR_RGB565 = 0,
84 OMAPFB_COLOR_YUV422,
85 OMAPFB_COLOR_YUV420,
86 OMAPFB_COLOR_CLUT_8BPP,
87 OMAPFB_COLOR_CLUT_4BPP,
88 OMAPFB_COLOR_CLUT_2BPP,
89 OMAPFB_COLOR_CLUT_1BPP,
90 OMAPFB_COLOR_RGB444,
91 OMAPFB_COLOR_YUY422,
92};
93
94struct omapfb_update_window {
95 __u32 x, y;
96 __u32 width, height;
97 __u32 format;
98 __u32 out_x, out_y;
99 __u32 out_width, out_height;
100 __u32 reserved[8];
101};
102
103struct omapfb_update_window_old {
104 __u32 x, y;
105 __u32 width, height;
106 __u32 format;
107};
108
109enum omapfb_plane {
110 OMAPFB_PLANE_GFX = 0,
111 OMAPFB_PLANE_VID1,
112 OMAPFB_PLANE_VID2,
113};
114
115enum omapfb_channel_out {
116 OMAPFB_CHANNEL_OUT_LCD = 0,
117 OMAPFB_CHANNEL_OUT_DIGIT,
118};
119
120struct omapfb_plane_info {
121 __u32 pos_x;
122 __u32 pos_y;
123 __u8 enabled;
124 __u8 channel_out;
125 __u8 mirror;
126 __u8 reserved1;
127 __u32 out_width;
128 __u32 out_height;
129 __u32 reserved2[12];
130};
131
132struct omapfb_mem_info {
133 __u32 size;
134 __u8 type;
135 __u8 reserved[3];
136};
137
138struct omapfb_caps {
139 __u32 ctrl;
140 __u32 plane_color;
141 __u32 wnd_color;
142};
143
144enum omapfb_color_key_type {
145 OMAPFB_COLOR_KEY_DISABLED = 0,
146 OMAPFB_COLOR_KEY_GFX_DST,
147 OMAPFB_COLOR_KEY_VID_SRC,
148};
149
150struct omapfb_color_key {
151 __u8 channel_out;
152 __u32 background;
153 __u32 trans_key;
154 __u8 key_type;
155};
156
157enum omapfb_update_mode {
158 OMAPFB_UPDATE_DISABLED = 0,
159 OMAPFB_AUTO_UPDATE,
160 OMAPFB_MANUAL_UPDATE
161};
162
163#ifdef __KERNEL__
164
165#include <linux/completion.h>
166#include <linux/interrupt.h>
167#include <linux/fb.h>
168#include <linux/mutex.h>
169
170#include <asm/arch/board.h>
171
172#define OMAP_LCDC_INV_VSYNC 0x0001
173#define OMAP_LCDC_INV_HSYNC 0x0002
174#define OMAP_LCDC_INV_PIX_CLOCK 0x0004
175#define OMAP_LCDC_INV_OUTPUT_EN 0x0008
176#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010
177#define OMAP_LCDC_HSVS_OPPOSITE 0x0020
178
179#define OMAP_LCDC_SIGNAL_MASK 0x003f
180
181#define OMAP_LCDC_PANEL_TFT 0x0100
182
183#define OMAPFB_PLANE_XRES_MIN 8
184#define OMAPFB_PLANE_YRES_MIN 8
185
186#ifdef CONFIG_ARCH_OMAP1
187#define OMAPFB_PLANE_NUM 1
188#else
189#define OMAPFB_PLANE_NUM 3
190#endif
191
192struct omapfb_device;
193
194struct lcd_panel {
195 const char *name;
196 int config; /* TFT/STN, signal inversion */
197 int bpp; /* Pixel format in fb mem */
198 int data_lines; /* Lines on LCD HW interface */
199
200 int x_res, y_res;
201 int pixel_clock; /* In kHz */
202 int hsw; /* Horizontal synchronization
203 pulse width */
204 int hfp; /* Horizontal front porch */
205 int hbp; /* Horizontal back porch */
206 int vsw; /* Vertical synchronization
207 pulse width */
208 int vfp; /* Vertical front porch */
209 int vbp; /* Vertical back porch */
210 int acb; /* ac-bias pin frequency */
211 int pcd; /* pixel clock divider.
212 Obsolete use pixel_clock instead */
213
214 int (*init) (struct lcd_panel *panel,
215 struct omapfb_device *fbdev);
216 void (*cleanup) (struct lcd_panel *panel);
217 int (*enable) (struct lcd_panel *panel);
218 void (*disable) (struct lcd_panel *panel);
219 unsigned long (*get_caps) (struct lcd_panel *panel);
220 int (*set_bklight_level)(struct lcd_panel *panel,
221 unsigned int level);
222 unsigned int (*get_bklight_level)(struct lcd_panel *panel);
223 unsigned int (*get_bklight_max) (struct lcd_panel *panel);
224 int (*run_test) (struct lcd_panel *panel, int test_num);
225};
226
227struct extif_timings {
228 int cs_on_time;
229 int cs_off_time;
230 int we_on_time;
231 int we_off_time;
232 int re_on_time;
233 int re_off_time;
234 int we_cycle_time;
235 int re_cycle_time;
236 int cs_pulse_width;
237 int access_time;
238
239 int clk_div;
240
241 u32 tim[5]; /* set by extif->convert_timings */
242
243 int converted;
244};
245
246struct lcd_ctrl_extif {
247 int (*init) (struct omapfb_device *fbdev);
248 void (*cleanup) (void);
249 void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div);
250 unsigned long (*get_max_tx_rate)(void);
251 int (*convert_timings) (struct extif_timings *timings);
252 void (*set_timings) (const struct extif_timings *timings);
253 void (*set_bits_per_cycle)(int bpc);
254 void (*write_command) (const void *buf, unsigned int len);
255 void (*read_data) (void *buf, unsigned int len);
256 void (*write_data) (const void *buf, unsigned int len);
257 void (*transfer_area) (int width, int height,
258 void (callback)(void * data), void *data);
259 int (*setup_tearsync) (unsigned pin_cnt,
260 unsigned hs_pulse_time, unsigned vs_pulse_time,
261 int hs_pol_inv, int vs_pol_inv, int div);
262 int (*enable_tearsync) (int enable, unsigned line);
263
264 unsigned long max_transmit_size;
265};
266
267struct omapfb_notifier_block {
268 struct notifier_block nb;
269 void *data;
270 int plane_idx;
271};
272
273typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
274 unsigned long event,
275 void *fbi);
276
277struct omapfb_mem_region {
278 dma_addr_t paddr;
279 void *vaddr;
280 unsigned long size;
281 u8 type; /* OMAPFB_PLANE_MEM_* */
282 unsigned alloc:1; /* allocated by the driver */
283 unsigned map:1; /* kernel mapped by the driver */
284};
285
286struct omapfb_mem_desc {
287 int region_cnt;
288 struct omapfb_mem_region region[OMAPFB_PLANE_NUM];
289};
290
291struct lcd_ctrl {
292 const char *name;
293 void *data;
294
295 int (*init) (struct omapfb_device *fbdev,
296 int ext_mode,
297 struct omapfb_mem_desc *req_md);
298 void (*cleanup) (void);
299 void (*bind_client) (struct omapfb_notifier_block *nb);
300 void (*get_caps) (int plane, struct omapfb_caps *caps);
301 int (*set_update_mode)(enum omapfb_update_mode mode);
302 enum omapfb_update_mode (*get_update_mode)(void);
303 int (*setup_plane) (int plane, int channel_out,
304 unsigned long offset,
305 int screen_width,
306 int pos_x, int pos_y, int width,
307 int height, int color_mode);
308 int (*setup_mem) (int plane, size_t size,
309 int mem_type, unsigned long *paddr);
310 int (*mmap) (struct fb_info *info,
311 struct vm_area_struct *vma);
312 int (*set_scale) (int plane,
313 int orig_width, int orig_height,
314 int out_width, int out_height);
315 int (*enable_plane) (int plane, int enable);
316 int (*update_window) (struct fb_info *fbi,
317 struct omapfb_update_window *win,
318 void (*callback)(void *),
319 void *callback_data);
320 void (*sync) (void);
321 void (*suspend) (void);
322 void (*resume) (void);
323 int (*run_test) (int test_num);
324 int (*setcolreg) (u_int regno, u16 red, u16 green,
325 u16 blue, u16 transp,
326 int update_hw_mem);
327 int (*set_color_key) (struct omapfb_color_key *ck);
328 int (*get_color_key) (struct omapfb_color_key *ck);
329};
330
331enum omapfb_state {
332 OMAPFB_DISABLED = 0,
333 OMAPFB_SUSPENDED= 99,
334 OMAPFB_ACTIVE = 100
335};
336
337struct omapfb_plane_struct {
338 int idx;
339 struct omapfb_plane_info info;
340 enum omapfb_color_format color_mode;
341 struct omapfb_device *fbdev;
342};
343
344struct omapfb_device {
345 int state;
346 int ext_lcdc; /* Using external
347 LCD controller */
348 struct mutex rqueue_mutex;
349
350 int palette_size;
351 u32 pseudo_palette[17];
352
353 struct lcd_panel *panel; /* LCD panel */
354 struct lcd_ctrl *ctrl; /* LCD controller */
355 struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
356 struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
357 interface */
358 struct device *dev;
359 struct fb_var_screeninfo new_var; /* for mode changes */
360
361 struct omapfb_mem_desc mem_desc;
362 struct fb_info *fb_info[OMAPFB_PLANE_NUM];
363};
364
365struct omapfb_platform_data {
366 struct omap_lcd_config lcd;
367 struct omapfb_mem_desc mem_desc;
368 void *ctrl_platform_data;
369};
370
371#ifdef CONFIG_ARCH_OMAP1
372extern struct lcd_ctrl omap1_lcd_ctrl;
373#else
374extern struct lcd_ctrl omap2_disp_ctrl;
375#endif
376
377extern void omapfb_register_panel(struct lcd_panel *panel);
378extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
379extern void omapfb_notify_clients(struct omapfb_device *fbdev,
380 unsigned long event);
381extern int omapfb_register_client(struct omapfb_notifier_block *nb,
382 omapfb_notifier_callback_t callback,
383 void *callback_data);
384extern int omapfb_unregister_client(struct omapfb_notifier_block *nb);
385extern int omapfb_update_window_async(struct fb_info *fbi,
386 struct omapfb_update_window *win,
387 void (*callback)(void *),
388 void *callback_data);
389
390/* in arch/arm/plat-omap/fb.c */
391extern void omapfb_set_ctrl_platform_data(void *pdata);
392
393#endif /* __KERNEL__ */
394
395#endif /* __OMAPFB_H */
diff --git a/include/asm-arm/arch-omap/onenand.h b/include/asm-arm/arch-omap/onenand.h
deleted file mode 100644
index 6c959d0ce470..000000000000
--- a/include/asm-arm/arch-omap/onenand.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * include/asm-arm/arch-omap/onenand.h
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Author: Juha Yrjola
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/mtd/partitions.h>
13
14struct omap_onenand_platform_data {
15 int cs;
16 int gpio_irq;
17 struct mtd_partition *parts;
18 int nr_parts;
19 int (*onenand_setup)(void __iomem *);
20 int dma_channel;
21};
diff --git a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h
deleted file mode 100644
index face9ad41e97..000000000000
--- a/include/asm-arm/arch-omap/param.h
+++ /dev/null
@@ -1,8 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/param.h
3 *
4 */
5
6#ifdef CONFIG_OMAP_32K_TIMER_HZ
7#define HZ CONFIG_OMAP_32K_TIMER_HZ
8#endif
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
deleted file mode 100644
index 14588059981f..000000000000
--- a/include/asm-arm/arch-omap/pm.h
+++ /dev/null
@@ -1,356 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/pm.h
3 *
4 * Header file for OMAP Power Management Routines
5 *
6 * Author: MontaVista Software, Inc.
7 * support@mvista.com
8 *
9 * Copyright 2002 MontaVista Software Inc.
10 *
11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#ifndef __ASM_ARCH_OMAP_PM_H
35#define __ASM_ARCH_OMAP_PM_H
36
37/*
38 * ----------------------------------------------------------------------------
39 * Register and offset definitions to be used in PM assembler code
40 * ----------------------------------------------------------------------------
41 */
42#define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08
45
46#define TCMIF_ASM_BASE io_p2v(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49
50/*
51 * ----------------------------------------------------------------------------
52 * Power management bitmasks
53 * ----------------------------------------------------------------------------
54 */
55#define IDLE_WAIT_CYCLES 0x00000fff
56#define PERIPHERAL_ENABLE 0x2
57
58#define SELF_REFRESH_MODE 0x0c000001
59#define IDLE_EMIFS_REQUEST 0xc
60#define MODEM_32K_EN 0x1
61#define PER_EN 0x1
62
63#define CPU_SUSPEND_SIZE 200
64#define ULPD_LOW_PWR_EN 0x0001
65#define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010
66#define ULPD_SETUP_ANALOG_CELL_3_VAL 0
67#define ULPD_POWER_CTRL_REG_VAL 0x0219
68
69#define DSP_IDLE_DELAY 10
70#define DSP_IDLE 0x0040
71#define DSP_RST 0x0004
72#define DSP_ENABLE 0x0002
73#define SUFFICIENT_DSP_RESET_TIME 1000
74#define DEFAULT_MPUI_CONFIG 0x05cf
75#define ENABLE_XORCLK 0x2
76#define DSP_CLOCK_ENABLE 0x2000
77#define DSP_IDLE_MODE 0x2
78#define TC_IDLE_REQUEST (0x0000000c)
79
80#define IRQ_LEVEL2 (1<<0)
81#define IRQ_KEYBOARD (1<<1)
82#define IRQ_UART2 (1<<15)
83
84#define PDE_BIT 0x08
85#define PWD_EN_BIT 0x04
86#define EN_PERCK_BIT 0x04
87
88#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
89#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
90#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
91#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
92
93/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
94#define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7
95#define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7
96#define OMAP1610_IDLECT3_VAL 0x3f
97#define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c
98#define OMAP1610_IDLECT3 0xfffece24
99#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
100
101#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7
102#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7
103#define OMAP730_IDLECT3_VAL 0x3f
104#define OMAP730_IDLECT3 0xfffece24
105#define OMAP730_IDLE_LOOP_REQUEST 0x0C00
106
107#if !defined(CONFIG_ARCH_OMAP730) && \
108 !defined(CONFIG_ARCH_OMAP15XX) && \
109 !defined(CONFIG_ARCH_OMAP16XX) && \
110 !defined(CONFIG_ARCH_OMAP24XX)
111#error "Power management for this processor not implemented yet"
112#endif
113
114#ifndef __ASSEMBLER__
115
116#include <linux/clk.h>
117
118extern void prevent_idle_sleep(void);
119extern void allow_idle_sleep(void);
120
121/**
122 * clk_deny_idle - Prevents the clock from being idled during MPU idle
123 * @clk: clock signal handle
124 */
125void clk_deny_idle(struct clk *clk);
126
127/**
128 * clk_allow_idle - Counters previous clk_deny_idle
129 * @clk: clock signal handle
130 */
131void clk_deny_idle(struct clk *clk);
132
133extern void omap_pm_idle(void);
134extern void omap_pm_suspend(void);
135extern void omap730_cpu_suspend(unsigned short, unsigned short);
136extern void omap1510_cpu_suspend(unsigned short, unsigned short);
137extern void omap1610_cpu_suspend(unsigned short, unsigned short);
138extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision);
139extern void omap730_idle_loop_suspend(void);
140extern void omap1510_idle_loop_suspend(void);
141extern void omap1610_idle_loop_suspend(void);
142extern void omap24xx_idle_loop_suspend(void);
143
144extern unsigned int omap730_cpu_suspend_sz;
145extern unsigned int omap1510_cpu_suspend_sz;
146extern unsigned int omap1610_cpu_suspend_sz;
147extern unsigned int omap24xx_cpu_suspend_sz;
148extern unsigned int omap730_idle_loop_suspend_sz;
149extern unsigned int omap1510_idle_loop_suspend_sz;
150extern unsigned int omap1610_idle_loop_suspend_sz;
151extern unsigned int omap24xx_idle_loop_suspend_sz;
152
153#ifdef CONFIG_OMAP_SERIAL_WAKE
154extern void omap_serial_wake_trigger(int enable);
155#else
156#define omap_serial_wakeup_init() {}
157#define omap_serial_wake_trigger(x) {}
158#endif /* CONFIG_OMAP_SERIAL_WAKE */
159
160#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
161#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
162#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
163
164#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
165#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
166#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
167
168#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
169#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
170#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
171
172#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
173#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
174#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
175
176#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
177#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
178#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
179
180#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
181#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
182#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
183
184#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
185#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
186#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
187
188/*
189 * List of global OMAP registers to preserve.
190 * More ones like CP and general purpose register values are preserved
191 * with the stack pointer in sleep.S.
192 */
193
194enum arm_save_state {
195 ARM_SLEEP_SAVE_START = 0,
196 /*
197 * MPU control registers 32 bits
198 */
199 ARM_SLEEP_SAVE_ARM_CKCTL,
200 ARM_SLEEP_SAVE_ARM_IDLECT1,
201 ARM_SLEEP_SAVE_ARM_IDLECT2,
202 ARM_SLEEP_SAVE_ARM_IDLECT3,
203 ARM_SLEEP_SAVE_ARM_EWUPCT,
204 ARM_SLEEP_SAVE_ARM_RSTCT1,
205 ARM_SLEEP_SAVE_ARM_RSTCT2,
206 ARM_SLEEP_SAVE_ARM_SYSST,
207 ARM_SLEEP_SAVE_SIZE
208};
209
210enum dsp_save_state {
211 DSP_SLEEP_SAVE_START = 0,
212 /*
213 * DSP registers 16 bits
214 */
215 DSP_SLEEP_SAVE_DSP_IDLECT2,
216 DSP_SLEEP_SAVE_SIZE
217};
218
219enum ulpd_save_state {
220 ULPD_SLEEP_SAVE_START = 0,
221 /*
222 * ULPD registers 16 bits
223 */
224 ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
225 ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
226 ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
227 ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
228 ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
229 ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
230 ULPD_SLEEP_SAVE_SIZE
231};
232
233enum mpui1510_save_state {
234 MPUI1510_SLEEP_SAVE_START = 0,
235 /*
236 * MPUI registers 32 bits
237 */
238 MPUI1510_SLEEP_SAVE_MPUI_CTRL,
239 MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
240 MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
241 MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
242 MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
243 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
244 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
245 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
246#if defined(CONFIG_ARCH_OMAP15XX)
247 MPUI1510_SLEEP_SAVE_SIZE
248#else
249 MPUI1510_SLEEP_SAVE_SIZE = 0
250#endif
251};
252
253enum mpui730_save_state {
254 MPUI730_SLEEP_SAVE_START = 0,
255 /*
256 * MPUI registers 32 bits
257 */
258 MPUI730_SLEEP_SAVE_MPUI_CTRL,
259 MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
260 MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
261 MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
262 MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
263 MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
264 MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
265 MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
266 MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
267#if defined(CONFIG_ARCH_OMAP730)
268 MPUI730_SLEEP_SAVE_SIZE
269#else
270 MPUI730_SLEEP_SAVE_SIZE = 0
271#endif
272};
273
274enum mpui1610_save_state {
275 MPUI1610_SLEEP_SAVE_START = 0,
276 /*
277 * MPUI registers 32 bits
278 */
279 MPUI1610_SLEEP_SAVE_MPUI_CTRL,
280 MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
281 MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
282 MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
283 MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
284 MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
285 MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
286 MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
287 MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
288 MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
289 MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
290#if defined(CONFIG_ARCH_OMAP16XX)
291 MPUI1610_SLEEP_SAVE_SIZE
292#else
293 MPUI1610_SLEEP_SAVE_SIZE = 0
294#endif
295};
296
297enum omap24xx_save_state {
298 OMAP24XX_SLEEP_SAVE_START = 0,
299 OMAP24XX_SLEEP_SAVE_INTC_MIR0,
300 OMAP24XX_SLEEP_SAVE_INTC_MIR1,
301 OMAP24XX_SLEEP_SAVE_INTC_MIR2,
302
303 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
304 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
305 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
306 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
307 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
308
309 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
310 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
311 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
312 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
313 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
314
315 OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
316 OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
317 OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
318 OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
319 OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
320 OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
321 OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
322 OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
323 OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
324
325 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
326 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
327 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
328 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
329 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
330 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
331 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
332 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
333
334 OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
335 OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
336 OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
337 OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
338 OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
339 OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
340 OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
341 OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
342 OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
343 OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
344 OMAP24XX_SLEEP_SAVE_GPIO3_OE,
345 OMAP24XX_SLEEP_SAVE_GPIO4_OE,
346 OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
347 OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
348 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
349 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
350 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
351 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
352 OMAP24XX_SLEEP_SAVE_SIZE
353};
354
355#endif /* ASSEMBLER */
356#endif /* __ASM_ARCH_OMAP_PM_H */
diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h
deleted file mode 100644
index 7bcaf94bde9f..000000000000
--- a/include/asm-arm/arch-omap/prcm.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/prcm.h
3 *
4 * Access definations for use in OMAP24XX clock and power management
5 *
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
24#define __ASM_ARM_ARCH_DPM_PRCM_H
25
26u32 omap_prcm_get_reset_sources(void);
27
28#endif
29
30
31
32
33
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
deleted file mode 100644
index 673b3965befc..000000000000
--- a/include/asm-arm/arch-omap/sdrc.h
+++ /dev/null
@@ -1,75 +0,0 @@
1#ifndef ____ASM_ARCH_SDRC_H
2#define ____ASM_ARCH_SDRC_H
3
4/*
5 * OMAP2/3 SDRC/SMS register definitions
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <asm/arch/io.h>
18
19/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
20
21#define SDRC_SYSCONFIG 0x010
22#define SDRC_DLLA_CTRL 0x060
23#define SDRC_DLLA_STATUS 0x064
24#define SDRC_DLLB_CTRL 0x068
25#define SDRC_DLLB_STATUS 0x06C
26#define SDRC_POWER 0x070
27#define SDRC_MR_0 0x084
28#define SDRC_RFR_CTRL_0 0x0a4
29
30/*
31 * These values represent the number of memory clock cycles between
32 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
33 * rows per device, and include a subtraction of a 50 cycle window in the
34 * event that the autorefresh command is delayed due to other SDRC activity.
35 * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
36 * counter reaches 0.
37 *
38 * These represent optimal values for common parts, it won't work for all.
39 * As long as you scale down, most parameters are still work, they just
40 * become sub-optimal. The RFR value goes in the opposite direction. If you
41 * don't adjust it down as your clock period increases the refresh interval
42 * will not be met. Setting all parameters for complete worst case may work,
43 * but may cut memory performance by 2x. Due to errata the DLLs need to be
44 * unlocked and their value needs run time calibration. A dynamic call is
45 * need for that as no single right value exists acorss production samples.
46 *
47 * Only the FULL speed values are given. Current code is such that rate
48 * changes must be made at DPLLoutx2. The actual value adjustment for low
49 * frequency operation will be handled by omap_set_performance()
50 *
51 * By having the boot loader boot up in the fastest L4 speed available likely
52 * will result in something which you can switch between.
53 */
54#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
55#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
56#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
57#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
58#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
59
60
61/*
62 * SMS register access
63 */
64
65
66#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
67#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
68#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
69
70/* SMS register offsets - read/write with sms_{read,write}_reg() */
71
72#define SMS_SYSCONFIG 0x010
73/* REVISIT: fill in other SMS registers here */
74
75#endif
diff --git a/include/asm-arm/arch-omap/serial.h b/include/asm-arm/arch-omap/serial.h
deleted file mode 100644
index 79a5297af9fc..000000000000
--- a/include/asm-arm/arch-omap/serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/serial.h
3 *
4 * This program is distributed in the hope that it will be useful,
5 * but WITHOUT ANY WARRANTY; without even the implied warranty of
6 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7 * GNU General Public License for more details.
8 */
9
10#ifndef __ASM_ARCH_SERIAL_H
11#define __ASM_ARCH_SERIAL_H
12
13#if defined(CONFIG_ARCH_OMAP1)
14/* OMAP1 serial ports */
15#define OMAP_UART1_BASE 0xfffb0000
16#define OMAP_UART2_BASE 0xfffb0800
17#define OMAP_UART3_BASE 0xfffb9800
18#elif defined(CONFIG_ARCH_OMAP2)
19/* OMAP2 serial ports */
20#define OMAP_UART1_BASE 0x4806a000
21#define OMAP_UART2_BASE 0x4806c000
22#define OMAP_UART3_BASE 0x4806e000
23#endif
24
25#define OMAP_MAX_NR_PORTS 3
26#define OMAP1510_BASE_BAUD (12000000/16)
27#define OMAP16XX_BASE_BAUD (48000000/16)
28
29#define is_omap_port(p) ({int __ret = 0; \
30 if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
31 p == IO_ADDRESS(OMAP_UART2_BASE) || \
32 p == IO_ADDRESS(OMAP_UART3_BASE)) \
33 __ret = 1; \
34 __ret; \
35 })
36
37#endif
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
deleted file mode 100644
index be59f4a9828b..000000000000
--- a/include/asm-arm/arch-omap/sram.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/sram.h
3 *
4 * Interface for functions that need to be run in internal SRAM
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H
13
14extern int __init omap_sram_init(void);
15extern void * omap_sram_push(void * start, unsigned long size);
16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
17
18extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
19 u32 base_cs, u32 force_unlock);
20extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21 u32 mem_type);
22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
23
24/* Do not use these */
25extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
26extern unsigned long omap1_sram_reprogram_clock_sz;
27
28extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
29extern unsigned long omap24xx_sram_reprogram_clock_sz;
30
31extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
32 u32 base_cs, u32 force_unlock);
33extern unsigned long omap242x_sram_ddr_init_sz;
34
35extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
36 int bypass);
37extern unsigned long omap242x_sram_set_prcm_sz;
38
39extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
40 u32 mem_type);
41extern unsigned long omap242x_sram_reprogram_sdrc_sz;
42
43
44extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
45 u32 base_cs, u32 force_unlock);
46extern unsigned long omap243x_sram_ddr_init_sz;
47
48extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
49 int bypass);
50extern unsigned long omap243x_sram_set_prcm_sz;
51
52extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
53 u32 mem_type);
54extern unsigned long omap243x_sram_reprogram_sdrc_sz;
55
56#endif
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
deleted file mode 100644
index 176d9d6c258e..000000000000
--- a/include/asm-arm/arch-omap/system.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Copied from linux/include/asm-arm/arch-sa1100/system.h
3 * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
4 */
5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H
7#include <linux/clk.h>
8
9#include <asm/mach-types.h>
10#include <asm/arch/hardware.h>
11
12#ifndef CONFIG_MACH_VOICEBLUE
13#define voiceblue_reset() do {} while (0)
14#endif
15
16extern void omap_prcm_arch_reset(char mode);
17
18static inline void arch_idle(void)
19{
20 cpu_do_idle();
21}
22
23static inline void omap1_arch_reset(char mode)
24{
25 /*
26 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
27 * "Global Software Reset Affects Traffic Controller Frequency".
28 */
29 if (cpu_is_omap5912()) {
30 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
31 DPLL_CTL);
32 omap_writew(0x8, ARM_RSTCT1);
33 }
34
35 if (machine_is_voiceblue())
36 voiceblue_reset();
37 else
38 omap_writew(1, ARM_RSTCT1);
39}
40
41static inline void arch_reset(char mode)
42{
43 if (!cpu_is_omap24xx())
44 omap1_arch_reset(mode);
45 else
46 omap_prcm_arch_reset(mode);
47}
48
49#endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
deleted file mode 100644
index 65a9c82d3bf7..000000000000
--- a/include/asm-arm/arch-omap/tc.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/tc.h
3 *
4 * OMAP Traffic Controller
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Author: Imre Deak <imre.deak@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef __ASM_ARCH_TC_H
25#define __ASM_ARCH_TC_H
26
27#define TCMIF_BASE 0xfffecc00
28#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
29#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
30#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
31#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
32#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
33#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
34#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
35#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
36#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
37#define EMIFF_MRS (TCMIF_BASE + 0x24)
38#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
39#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
40#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
41#define TC_ENDIANISM (TCMIF_BASE + 0x34)
42#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
43#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
44#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
45#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
46#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
47#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
48#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
49
50/* external EMIFS chipselect regions */
51#define OMAP_CS0_PHYS 0x00000000
52#define OMAP_CS0_SIZE SZ_64M
53
54#define OMAP_CS1_PHYS 0x04000000
55#define OMAP_CS1_SIZE SZ_64M
56
57#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
58#define OMAP_CS1A_SIZE SZ_32M
59
60#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
61#define OMAP_CS1B_SIZE SZ_32M
62
63#define OMAP_CS2_PHYS 0x08000000
64#define OMAP_CS2_SIZE SZ_64M
65
66#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
67#define OMAP_CS2A_SIZE SZ_32M
68
69#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
70#define OMAP_CS2B_SIZE SZ_32M
71
72#define OMAP_CS3_PHYS 0x0c000000
73#define OMAP_CS3_SIZE SZ_64M
74
75#ifndef __ASSEMBLER__
76
77/* EMIF Slow Interface Configuration Register */
78#define OMAP_EMIFS_CONFIG_FR (1 << 4)
79#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
80#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
81#define OMAP_EMIFS_CONFIG_BM (1 << 1)
82#define OMAP_EMIFS_CONFIG_WP (1 << 0)
83
84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
86
87/* Almost all documentation for chip and board memory maps assumes
88 * BM is clear. Most devel boards have a switch to control booting
89 * from NOR flash (using external chipselect 3) rather than mask ROM,
90 * which uses BM to interchange the physical CS0 and CS3 addresses.
91 */
92static inline u32 omap_cs0_phys(void)
93{
94 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
95 ? OMAP_CS3_PHYS : 0;
96}
97
98static inline u32 omap_cs3_phys(void)
99{
100 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
101 ? 0 : OMAP_CS3_PHYS;
102}
103
104#endif /* __ASSEMBLER__ */
105
106#endif /* __ASM_ARCH_TC_H */
diff --git a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h
deleted file mode 100644
index 21f2e367185a..000000000000
--- a/include/asm-arm/arch-omap/timex.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/timex.h
3 *
4 * Copyright (C) 2000 RidgeRun, Inc.
5 * Author: Greg Lonnon <glonnon@ridgerun.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
29#define __ASM_ARCH_OMAP_TIMEX_H
30
31/*
32 * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
33 * and that's why the CLOCK_TICK_RATE is not 32768.
34 */
35#ifdef CONFIG_OMAP_32K_TIMER
36#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
37#else
38#define CLOCK_TICK_RATE (HZ * 100000UL)
39#endif
40
41#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
deleted file mode 100644
index aca0adfef1b8..000000000000
--- a/include/asm-arm/arch-omap/uncompress.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/uncompress.h
3 *
4 * Serial port stubs for kernel decompress status messages
5 *
6 * Initially based on:
7 * linux-2.4.15-rmk1-dsplinux1.6/include/asm-arm/arch-omap1510/uncompress.h
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Author: Greg Lonnon <glonnon@ridgerun.com>
10 *
11 * Rewritten by:
12 * Author: <source@mvista.com>
13 * 2004 (c) MontaVista Software, Inc.
14 *
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
18 */
19
20#include <linux/types.h>
21#include <linux/serial_reg.h>
22#include <asm/arch/serial.h>
23
24unsigned int system_rev;
25
26#define UART_OMAP_MDR1 0x08 /* mode definition register */
27#define OMAP_ID_730 0x355F
28#define ID_MASK 0x7fff
29#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
30#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
31
32static void putc(int c)
33{
34 volatile u8 * uart = 0;
35 int shift = 2;
36
37#ifdef CONFIG_MACH_OMAP_PALMTE
38 return;
39#endif
40
41#ifdef CONFIG_ARCH_OMAP
42#ifdef CONFIG_OMAP_LL_DEBUG_UART3
43 uart = (volatile u8 *)(OMAP_UART3_BASE);
44#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
45 uart = (volatile u8 *)(OMAP_UART2_BASE);
46#else
47 uart = (volatile u8 *)(OMAP_UART1_BASE);
48#endif
49
50#ifdef CONFIG_ARCH_OMAP1
51 /* Determine which serial port to use */
52 do {
53 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
54 unsigned int omap_id = omap_get_id();
55
56 if (omap_id == OMAP_ID_730)
57 shift = 0;
58
59 if (check_port(uart, shift))
60 break;
61 /* Silent boot if no serial ports are enabled. */
62 return;
63 } while (0);
64#endif /* CONFIG_ARCH_OMAP1 */
65#endif
66
67 /*
68 * Now, xmit each character
69 */
70 while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
71 barrier();
72 uart[UART_TX << shift] = c;
73}
74
75static inline void flush(void)
76{
77}
78
79/*
80 * nothing to do
81 */
82#define arch_decomp_setup()
83#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
deleted file mode 100644
index ddf1861e6df9..000000000000
--- a/include/asm-arm/arch-omap/usb.h
+++ /dev/null
@@ -1,141 +0,0 @@
1// include/asm-arm/mach-omap/usb.h
2
3#ifndef __ASM_ARCH_OMAP_USB_H
4#define __ASM_ARCH_OMAP_USB_H
5
6#include <asm/arch/board.h>
7
8/*-------------------------------------------------------------------------*/
9
10#define OMAP1_OTG_BASE 0xfffb0400
11#define OMAP1_UDC_BASE 0xfffb4000
12#define OMAP1_OHCI_BASE 0xfffba000
13
14#define OMAP2_OHCI_BASE 0x4805e000
15#define OMAP2_UDC_BASE 0x4805e200
16#define OMAP2_OTG_BASE 0x4805e300
17
18#ifdef CONFIG_ARCH_OMAP1
19
20#define OTG_BASE OMAP1_OTG_BASE
21#define UDC_BASE OMAP1_UDC_BASE
22#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
23
24#else
25
26#define OTG_BASE OMAP2_OTG_BASE
27#define UDC_BASE OMAP2_UDC_BASE
28#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
29
30#endif
31
32/*-------------------------------------------------------------------------*/
33
34/*
35 * OTG and transceiver registers, for OMAPs starting with ARM926
36 */
37#define OTG_REV (OTG_BASE + 0x00)
38#define OTG_SYSCON_1 (OTG_BASE + 0x04)
39# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
40# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
41# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
42# define OTG_IDLE_EN (1 << 15)
43# define HST_IDLE_EN (1 << 14)
44# define DEV_IDLE_EN (1 << 13)
45# define OTG_RESET_DONE (1 << 2)
46# define OTG_SOFT_RESET (1 << 1)
47#define OTG_SYSCON_2 (OTG_BASE + 0x08)
48# define OTG_EN (1 << 31)
49# define USBX_SYNCHRO (1 << 30)
50# define OTG_MST16 (1 << 29)
51# define SRP_GPDATA (1 << 28)
52# define SRP_GPDVBUS (1 << 27)
53# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
54# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
55# define B_ASE_BRST(w) (((w)>>16)&0x07)
56# define SRP_DPW (1 << 14)
57# define SRP_DATA (1 << 13)
58# define SRP_VBUS (1 << 12)
59# define OTG_PADEN (1 << 10)
60# define HMC_PADEN (1 << 9)
61# define UHOST_EN (1 << 8)
62# define HMC_TLLSPEED (1 << 7)
63# define HMC_TLLATTACH (1 << 6)
64# define OTG_HMC(w) (((w)>>0)&0x3f)
65#define OTG_CTRL (OTG_BASE + 0x0c)
66# define OTG_USB2_EN (1 << 29)
67# define OTG_USB2_DP (1 << 28)
68# define OTG_USB2_DM (1 << 27)
69# define OTG_USB1_EN (1 << 26)
70# define OTG_USB1_DP (1 << 25)
71# define OTG_USB1_DM (1 << 24)
72# define OTG_USB0_EN (1 << 23)
73# define OTG_USB0_DP (1 << 22)
74# define OTG_USB0_DM (1 << 21)
75# define OTG_ASESSVLD (1 << 20)
76# define OTG_BSESSEND (1 << 19)
77# define OTG_BSESSVLD (1 << 18)
78# define OTG_VBUSVLD (1 << 17)
79# define OTG_ID (1 << 16)
80# define OTG_DRIVER_SEL (1 << 15)
81# define OTG_A_SETB_HNPEN (1 << 12)
82# define OTG_A_BUSREQ (1 << 11)
83# define OTG_B_HNPEN (1 << 9)
84# define OTG_B_BUSREQ (1 << 8)
85# define OTG_BUSDROP (1 << 7)
86# define OTG_PULLDOWN (1 << 5)
87# define OTG_PULLUP (1 << 4)
88# define OTG_DRV_VBUS (1 << 3)
89# define OTG_PD_VBUS (1 << 2)
90# define OTG_PU_VBUS (1 << 1)
91# define OTG_PU_ID (1 << 0)
92#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
93# define DRIVER_SWITCH (1 << 15)
94# define A_VBUS_ERR (1 << 13)
95# define A_REQ_TMROUT (1 << 12)
96# define A_SRP_DETECT (1 << 11)
97# define B_HNP_FAIL (1 << 10)
98# define B_SRP_TMROUT (1 << 9)
99# define B_SRP_DONE (1 << 8)
100# define B_SRP_STARTED (1 << 7)
101# define OPRT_CHG (1 << 0)
102#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
103 // same bits as in IRQ_EN
104#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
105# define OTGVPD (1 << 14)
106# define OTGVPU (1 << 13)
107# define OTGPUID (1 << 12)
108# define USB2VDR (1 << 10)
109# define USB2PDEN (1 << 9)
110# define USB2PUEN (1 << 8)
111# define USB1VDR (1 << 6)
112# define USB1PDEN (1 << 5)
113# define USB1PUEN (1 << 4)
114# define USB0VDR (1 << 2)
115# define USB0PDEN (1 << 1)
116# define USB0PUEN (1 << 0)
117#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
118#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
119
120/*-------------------------------------------------------------------------*/
121
122/* OMAP1 */
123#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
124# define CONF_USB2_UNI_R (1 << 8)
125# define CONF_USB1_UNI_R (1 << 7)
126# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
127# define CONF_USB0_ISOLATE_R (1 << 3)
128# define CONF_USB_PWRDN_DM_R (1 << 2)
129# define CONF_USB_PWRDN_DP_R (1 << 1)
130
131/* OMAP2 */
132# define USB_UNIDIR 0x0
133# define USB_UNIDIR_TLL 0x1
134# define USB_BIDIR 0x2
135# define USB_BIDIR_TLL 0x3
136# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
137# define USBT2TLL5PI (1 << 17)
138# define USB0PUENACTLOI (1 << 16)
139# define USBSTANDBYCTRL (1 << 15)
140
141#endif /* __ASM_ARCH_OMAP_USB_H */
diff --git a/include/asm-arm/arch-omap/vmalloc.h b/include/asm-arm/arch-omap/vmalloc.h
deleted file mode 100644
index 5b8bd8dae8be..000000000000
--- a/include/asm-arm/arch-omap/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
21
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 11:01:05 -0500