aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm/arch-omap
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm/arch-omap')
-rw-r--r--include/asm-arm/arch-omap/board-fsample.h51
-rw-r--r--include/asm-arm/arch-omap/board.h7
-rw-r--r--include/asm-arm/arch-omap/dma.h15
-rw-r--r--include/asm-arm/arch-omap/dmtimer.h80
-rw-r--r--include/asm-arm/arch-omap/gpmc.h91
-rw-r--r--include/asm-arm/arch-omap/hardware.h4
-rw-r--r--include/asm-arm/arch-omap/irqs.h14
-rw-r--r--include/asm-arm/arch-omap/mux.h26
-rw-r--r--include/asm-arm/arch-omap/pm.h33
9 files changed, 269 insertions, 52 deletions
diff --git a/include/asm-arm/arch-omap/board-fsample.h b/include/asm-arm/arch-omap/board-fsample.h
new file mode 100644
index 000000000000..89a1e529fb6f
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-fsample.h
@@ -0,0 +1,51 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-fsample.h
3 *
4 * Board-specific goodies for TI F-Sample.
5 *
6 * Copyright (C) 2006 Google, Inc.
7 * Author: Brian Swetland <swetland@google.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_OMAP_FSAMPLE_H
15#define __ASM_ARCH_OMAP_FSAMPLE_H
16
17/* fsample is pretty close to p2-sample */
18#include <asm/arch/board-perseus2.h>
19
20#define fsample_cpld_read(reg) __raw_readb(reg)
21#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
22
23#define FSAMPLE_CPLD_BASE 0xE8100000
24#define FSAMPLE_CPLD_SIZE SZ_4K
25#define FSAMPLE_CPLD_START 0x05080000
26
27#define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
28#define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
29#define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
30#define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
31#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
32#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
33
34#define FSAMPLE_CPLD_BIT_BT_RESET 0
35#define FSAMPLE_CPLD_BIT_LCD_RESET 1
36#define FSAMPLE_CPLD_BIT_CAM_PWDN 2
37#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
38#define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
39#define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
40#define FSAMPLE_CPLD_BIT_BACKLIGHT 6
41#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
42#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
43#define FSAMPLE_CPLD_BIT_OTG_RESET 9
44
45#define fsample_cpld_set(bit) \
46 fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
47
48#define fsample_cpld_clear(bit) \
49 fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
50
51#endif
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
index dfdbf06fd646..edf1dc6ad919 100644
--- a/include/asm-arm/arch-omap/board.h
+++ b/include/asm-arm/arch-omap/board.h
@@ -22,6 +22,7 @@
22#define OMAP_TAG_UART 0x4f07 22#define OMAP_TAG_UART 0x4f07
23#define OMAP_TAG_FBMEM 0x4f08 23#define OMAP_TAG_FBMEM 0x4f08
24#define OMAP_TAG_STI_CONSOLE 0x4f09 24#define OMAP_TAG_STI_CONSOLE 0x4f09
25#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
25 26
26#define OMAP_TAG_BOOT_REASON 0x4f80 27#define OMAP_TAG_BOOT_REASON 0x4f80
27#define OMAP_TAG_FLASH_PART 0x4f81 28#define OMAP_TAG_FLASH_PART 0x4f81
@@ -61,6 +62,12 @@ struct omap_sti_console_config {
61 u8 channel; 62 u8 channel;
62}; 63};
63 64
65struct omap_camera_sensor_config {
66 u16 reset_gpio;
67 int (*power_on)(void * data);
68 int (*power_off)(void * data);
69};
70
64struct omap_usb_config { 71struct omap_usb_config {
65 /* Configure drivers according to the connectors on your board: 72 /* Configure drivers according to the connectors on your board:
66 * - "A" connector (rectagular) 73 * - "A" connector (rectagular)
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index ca1202312a45..1b1b02307e77 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -185,8 +185,8 @@
185/* DMA channels for 24xx */ 185/* DMA channels for 24xx */
186#define OMAP24XX_DMA_NO_DEVICE 0 186#define OMAP24XX_DMA_NO_DEVICE 0
187#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ 187#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
188#define OMAP24XX_DMA_EXT_NDMA_REQ0 2 /* S_DMA_1 */ 188#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
189#define OMAP24XX_DMA_EXT_NDMA_REQ1 3 /* S_DMA_2 */ 189#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
190#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ 190#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
191#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ 191#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
192#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ 192#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
@@ -197,7 +197,9 @@
197#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ 197#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
198#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ 198#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
199#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ 199#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
200 200#define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
201#define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
202#define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
201#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ 203#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */
202#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ 204#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */
203#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ 205#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
@@ -244,6 +246,7 @@
244#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ 246#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */
245#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ 247#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */
246#define OMAP24XX_DMA_MS 63 /* SDMA_62 */ 248#define OMAP24XX_DMA_MS 63 /* SDMA_62 */
249#define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
247 250
248/*----------------------------------------------------------------------------*/ 251/*----------------------------------------------------------------------------*/
249 252
@@ -274,7 +277,7 @@
274#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) 277#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
275#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) 278#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
276 279
277#define OMAP_DMA_TOUT_IRQ (1 << 0) /* Only on omap1 */ 280#define OMAP1_DMA_TOUT_IRQ (1 << 0)
278#define OMAP_DMA_DROP_IRQ (1 << 1) 281#define OMAP_DMA_DROP_IRQ (1 << 1)
279#define OMAP_DMA_HALF_IRQ (1 << 2) 282#define OMAP_DMA_HALF_IRQ (1 << 2)
280#define OMAP_DMA_FRAME_IRQ (1 << 3) 283#define OMAP_DMA_FRAME_IRQ (1 << 3)
@@ -315,11 +318,11 @@ enum {
315 OMAP_LCD_DMA_B2_BOTTOM 318 OMAP_LCD_DMA_B2_BOTTOM
316}; 319};
317 320
318/* REVISIT: Check if BURST_4 is really 1 (or 2) */
319enum omap_dma_burst_mode { 321enum omap_dma_burst_mode {
320 OMAP_DMA_DATA_BURST_DIS = 0, 322 OMAP_DMA_DATA_BURST_DIS = 0,
321 OMAP_DMA_DATA_BURST_4, 323 OMAP_DMA_DATA_BURST_4,
322 OMAP_DMA_DATA_BURST_8 324 OMAP_DMA_DATA_BURST_8,
325 OMAP_DMA_DATA_BURST_16,
323}; 326};
324 327
325enum omap_dma_color_mode { 328enum omap_dma_color_mode {
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
index e6522e6a3834..7a289ff07404 100644
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -5,6 +5,7 @@
5 * 5 *
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> 7 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
8 * PWM and clock framwork support by Timo Teras.
8 * 9 *
9 * This program is free software; you can redistribute it and/or modify it 10 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 11 * under the terms of the GNU General Public License as published by the
@@ -25,69 +26,56 @@
25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */ 27 */
27 28
28#ifndef __ASM_ARCH_TIMER_H 29#ifndef __ASM_ARCH_DMTIMER_H
29#define __ASM_ARCH_TIMER_H 30#define __ASM_ARCH_DMTIMER_H
30
31#include <linux/list.h>
32
33#define OMAP_TIMER_SRC_ARMXOR 0x00
34#define OMAP_TIMER_SRC_32_KHZ 0x01
35#define OMAP_TIMER_SRC_EXT_CLK 0x02
36
37/* timer control reg bits */
38#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
39#define OMAP_TIMER_CTRL_PT (1 << 12)
40#define OMAP_TIMER_CTRL_TRG_OVERFLOW (0x1 << 10)
41#define OMAP_TIMER_CTRL_TRG_OFANDMATCH (0x2 << 10)
42#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
43#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
44#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
45#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
46#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
47#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
48#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */
49#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
50#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
51 31
52/* timer interrupt enable bits */ 32/* clock sources */
53#define OMAP_TIMER_INT_CAPTURE (1 << 2) 33#define OMAP_TIMER_SRC_SYS_CLK 0x00
54#define OMAP_TIMER_INT_OVERFLOW (1 << 1) 34#define OMAP_TIMER_SRC_32_KHZ 0x01
55#define OMAP_TIMER_INT_MATCH (1 << 0) 35#define OMAP_TIMER_SRC_EXT_CLK 0x02
56 36
37/* timer interrupt enable bits */
38#define OMAP_TIMER_INT_CAPTURE (1 << 2)
39#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
40#define OMAP_TIMER_INT_MATCH (1 << 0)
57 41
58struct omap_dm_timer { 42/* trigger types */
59 struct list_head timer_list; 43#define OMAP_TIMER_TRIGGER_NONE 0x00
44#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
45#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
60 46
61 u32 base; 47struct omap_dm_timer;
62 unsigned int irq; 48struct clk;
63};
64 49
65u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg); 50int omap_dm_timer_init(void);
66void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value);
67 51
68struct omap_dm_timer * omap_dm_timer_request(void); 52struct omap_dm_timer *omap_dm_timer_request(void);
53struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
69void omap_dm_timer_free(struct omap_dm_timer *timer); 54void omap_dm_timer_free(struct omap_dm_timer *timer);
70void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
71 55
72void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); 56int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
73void omap_dm_timer_set_trigger(struct omap_dm_timer *timer, unsigned int value); 57
74void omap_dm_timer_enable_compare(struct omap_dm_timer *timer); 58u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
75void omap_dm_timer_enable_autoreload(struct omap_dm_timer *timer); 59struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
76 60
77void omap_dm_timer_trigger(struct omap_dm_timer *timer); 61void omap_dm_timer_trigger(struct omap_dm_timer *timer);
78void omap_dm_timer_start(struct omap_dm_timer *timer); 62void omap_dm_timer_start(struct omap_dm_timer *timer);
79void omap_dm_timer_stop(struct omap_dm_timer *timer); 63void omap_dm_timer_stop(struct omap_dm_timer *timer);
80 64
81void omap_dm_timer_set_load(struct omap_dm_timer *timer, unsigned int load); 65void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
82void omap_dm_timer_set_match(struct omap_dm_timer *timer, unsigned int match); 66void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
67void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
68void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
69void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
70
71void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
83 72
84unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); 73unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
85void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); 74void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
86
87unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); 75unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
88void omap_dm_timer_reset_counter(struct omap_dm_timer *timer); 76void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
89 77
90int omap_dm_timers_active(void); 78int omap_dm_timers_active(void);
91u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
92 79
93#endif /* __ASM_ARCH_TIMER_H */ 80
81#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
new file mode 100644
index 000000000000..1a0a5207822d
--- /dev/null
+++ b/include/asm-arm/arch-omap/gpmc.h
@@ -0,0 +1,91 @@
1/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14#define GPMC_CS_CONFIG1 0x00
15#define GPMC_CS_CONFIG2 0x04
16#define GPMC_CS_CONFIG3 0x08
17#define GPMC_CS_CONFIG4 0x0c
18#define GPMC_CS_CONFIG5 0x10
19#define GPMC_CS_CONFIG6 0x14
20#define GPMC_CS_CONFIG7 0x18
21#define GPMC_CS_NAND_COMMAND 0x1c
22#define GPMC_CS_NAND_ADDRESS 0x20
23#define GPMC_CS_NAND_DATA 0x24
24
25#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
26#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 20)
27#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
28#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
29#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
30#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
31#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
32#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
33#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
34#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
35#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
36#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
37#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
38#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
39#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
40#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
41#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1)
42#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
43#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
44#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
45#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
46#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
47#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
48
49/*
50 * Note that all values in this struct are in nanoseconds, while
51 * the register values are in gpmc_fck cycles.
52 */
53struct gpmc_timings {
54 /* Minimum clock period for synchronous mode */
55 u16 sync_clk;
56
57 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u16 cs_on; /* Assertion time */
59 u16 cs_rd_off; /* Read deassertion time */
60 u16 cs_wr_off; /* Write deassertion time */
61
62 /* ADV signal timings corresponding to GPMC_CONFIG3 */
63 u16 adv_on; /* Assertion time */
64 u16 adv_rd_off; /* Read deassertion time */
65 u16 adv_wr_off; /* Write deassertion time */
66
67 /* WE signals timings corresponding to GPMC_CONFIG4 */
68 u16 we_on; /* WE assertion time */
69 u16 we_off; /* WE deassertion time */
70
71 /* OE signals timings corresponding to GPMC_CONFIG4 */
72 u16 oe_on; /* OE assertion time */
73 u16 oe_off; /* OE deassertion time */
74
75 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
76 u16 page_burst_access; /* Multiple access word delay */
77 u16 access; /* Start-cycle to first data valid delay */
78 u16 rd_cycle; /* Total read cycle time */
79 u16 wr_cycle; /* Total write cycle time */
80};
81
82extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
83
84extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
85extern u32 gpmc_cs_read_reg(int cs, int idx);
86extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
87extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
88extern unsigned long gpmc_cs_get_base_addr(int cs);
89
90
91#endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index c7d9e857795d..481048d65214 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -297,6 +297,10 @@
297#include "board-perseus2.h" 297#include "board-perseus2.h"
298#endif 298#endif
299 299
300#ifdef CONFIG_MACH_OMAP_FSAMPLE
301#include "board-fsample.h"
302#endif
303
300#ifdef CONFIG_MACH_OMAP_H3 304#ifdef CONFIG_MACH_OMAP_H3
301#include "board-h3.h" 305#include "board-h3.h"
302#endif 306#endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 42098d99f302..2542495d8a43 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -242,10 +242,24 @@
242#define INT_24XX_GPIO_BANK2 30 242#define INT_24XX_GPIO_BANK2 30
243#define INT_24XX_GPIO_BANK3 31 243#define INT_24XX_GPIO_BANK3 31
244#define INT_24XX_GPIO_BANK4 32 244#define INT_24XX_GPIO_BANK4 32
245#define INT_24XX_GPTIMER1 37
246#define INT_24XX_GPTIMER2 38
247#define INT_24XX_GPTIMER3 39
248#define INT_24XX_GPTIMER4 40
249#define INT_24XX_GPTIMER5 41
250#define INT_24XX_GPTIMER6 42
251#define INT_24XX_GPTIMER7 43
252#define INT_24XX_GPTIMER8 44
253#define INT_24XX_GPTIMER9 45
254#define INT_24XX_GPTIMER10 46
255#define INT_24XX_GPTIMER11 47
256#define INT_24XX_GPTIMER12 48
245#define INT_24XX_MCBSP1_IRQ_TX 59 257#define INT_24XX_MCBSP1_IRQ_TX 59
246#define INT_24XX_MCBSP1_IRQ_RX 60 258#define INT_24XX_MCBSP1_IRQ_RX 60
247#define INT_24XX_MCBSP2_IRQ_TX 62 259#define INT_24XX_MCBSP2_IRQ_TX 62
248#define INT_24XX_MCBSP2_IRQ_RX 63 260#define INT_24XX_MCBSP2_IRQ_RX 63
261#define INT_24XX_UART1_IRQ 72
262#define INT_24XX_UART2_IRQ 73
249#define INT_24XX_UART3_IRQ 74 263#define INT_24XX_UART3_IRQ 74
250 264
251/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and 265/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 0dc24d4ba59c..679869c5e68f 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -410,6 +410,12 @@ enum omap24xx_index {
410 /* 24xx clock */ 410 /* 24xx clock */
411 W14_24XX_SYS_CLKOUT, 411 W14_24XX_SYS_CLKOUT,
412 412
413 /* 24xx GPMC wait pin monitoring */
414 L3_GPMC_WAIT0,
415 N7_GPMC_WAIT1,
416 M1_GPMC_WAIT2,
417 P1_GPMC_WAIT3,
418
413 /* 242X McBSP */ 419 /* 242X McBSP */
414 Y15_24XX_MCBSP2_CLKX, 420 Y15_24XX_MCBSP2_CLKX,
415 R14_24XX_MCBSP2_FSX, 421 R14_24XX_MCBSP2_FSX,
@@ -429,6 +435,26 @@ enum omap24xx_index {
429 M15_24XX_GPIO92, 435 M15_24XX_GPIO92,
430 V14_24XX_GPIO117, 436 V14_24XX_GPIO117,
431 437
438 /* 242x DBG GPIO */
439 V4_242X_GPIO49,
440 W2_242X_GPIO50,
441 U4_242X_GPIO51,
442 V3_242X_GPIO52,
443 V2_242X_GPIO53,
444 V6_242X_GPIO53,
445 T4_242X_GPIO54,
446 Y4_242X_GPIO54,
447 T3_242X_GPIO55,
448 U2_242X_GPIO56,
449
450 /* 24xx external DMA requests */
451 AA10_242X_DMAREQ0,
452 AA6_242X_DMAREQ1,
453 E4_242X_DMAREQ2,
454 G4_242X_DMAREQ3,
455 D3_242X_DMAREQ4,
456 E3_242X_DMAREQ5,
457
432 P20_24XX_TSC_IRQ, 458 P20_24XX_TSC_IRQ,
433 459
434 /* UART3 */ 460 /* UART3 */
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
index 05b003f3a94c..e46623c61a72 100644
--- a/include/asm-arm/arch-omap/pm.h
+++ b/include/asm-arm/arch-omap/pm.h
@@ -299,10 +299,43 @@ enum omap24xx_save_state {
299 OMAP24XX_SLEEP_SAVE_INTC_MIR0, 299 OMAP24XX_SLEEP_SAVE_INTC_MIR0,
300 OMAP24XX_SLEEP_SAVE_INTC_MIR1, 300 OMAP24XX_SLEEP_SAVE_INTC_MIR1,
301 OMAP24XX_SLEEP_SAVE_INTC_MIR2, 301 OMAP24XX_SLEEP_SAVE_INTC_MIR2,
302
303 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
304 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
305 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
306 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
307 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
308
309 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
310 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
311 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
312 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
313 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
314
315 OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
316 OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
317 OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
318 OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
319 OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
320 OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
321 OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
322 OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
323 OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
324
325 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
326 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
327 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
328 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
329 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
330 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
331 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
332 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
333
302 OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE, 334 OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
303 OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE, 335 OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
304 OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE, 336 OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
305 OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE, 337 OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
338 OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
306 OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE, 339 OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
307 OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1, 340 OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
308 OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1, 341 OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 20:41:17 -0500