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-rw-r--r--include/asm-arm/arch-omap/board-osk.h11
-rw-r--r--include/asm-arm/arch-omap/clock.h75
-rw-r--r--include/asm-arm/arch-omap/control.h191
-rw-r--r--include/asm-arm/arch-omap/entry-macro.S2
-rw-r--r--include/asm-arm/arch-omap/gpio.h57
-rw-r--r--include/asm-arm/arch-omap/io.h70
-rw-r--r--include/asm-arm/arch-omap/mux.h66
-rw-r--r--include/asm-arm/arch-omap/omap24xx.h96
-rw-r--r--include/asm-arm/arch-omap/sdrc.h75
-rw-r--r--include/asm-arm/arch-omap/usb.h5
10 files changed, 556 insertions, 92 deletions
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
index 2b1a8a4fe44e..94926090e475 100644
--- a/include/asm-arm/arch-omap/board-osk.h
+++ b/include/asm-arm/arch-omap/board-osk.h
@@ -32,5 +32,16 @@
32/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ 32/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
33#define OMAP_OSK_ETHR_START 0x04800300 33#define OMAP_OSK_ETHR_START 0x04800300
34 34
35/* TPS65010 has four GPIOs. nPG and LED2 can be treated like GPIOs with
36 * alternate pin configurations for hardware-controlled blinking.
37 */
38#define OSK_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
39# define OSK_TPS_GPIO_USB_PWR_EN (OSK_TPS_GPIO_BASE + 0)
40# define OSK_TPS_GPIO_LED_D3 (OSK_TPS_GPIO_BASE + 1)
41# define OSK_TPS_GPIO_LAN_RESET (OSK_TPS_GPIO_BASE + 2)
42# define OSK_TPS_GPIO_DSP_PWR_EN (OSK_TPS_GPIO_BASE + 3)
43# define OSK_TPS_GPIO_LED_D9 (OSK_TPS_GPIO_BASE + 4)
44# define OSK_TPS_GPIO_LED_D2 (OSK_TPS_GPIO_BASE + 5)
45
35#endif /* __ASM_ARCH_OMAP_OSK_H */ 46#endif /* __ASM_ARCH_OMAP_OSK_H */
36 47
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index fa6881049903..57523bdb642b 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -14,6 +14,35 @@
14#define __ARCH_ARM_OMAP_CLOCK_H 14#define __ARCH_ARM_OMAP_CLOCK_H
15 15
16struct module; 16struct module;
17struct clk;
18
19#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
20
21struct clksel_rate {
22 u8 div;
23 u32 val;
24 u8 flags;
25};
26
27struct clksel {
28 struct clk *parent;
29 const struct clksel_rate *rates;
30};
31
32struct dpll_data {
33 void __iomem *mult_div1_reg;
34 u32 mult_mask;
35 u32 div1_mask;
36# if defined(CONFIG_ARCH_OMAP3)
37 void __iomem *control_reg;
38 u32 enable_mask;
39 u8 auto_recal_bit;
40 u8 recal_en_bit;
41 u8 recal_st_bit;
42# endif
43};
44
45#endif
17 46
18struct clk { 47struct clk {
19 struct list_head node; 48 struct list_head node;
@@ -25,8 +54,6 @@ struct clk {
25 __u32 flags; 54 __u32 flags;
26 void __iomem *enable_reg; 55 void __iomem *enable_reg;
27 __u8 enable_bit; 56 __u8 enable_bit;
28 __u8 rate_offset;
29 __u8 src_offset;
30 __s8 usecount; 57 __s8 usecount;
31 void (*recalc)(struct clk *); 58 void (*recalc)(struct clk *);
32 int (*set_rate)(struct clk *, unsigned long); 59 int (*set_rate)(struct clk *, unsigned long);
@@ -34,6 +61,16 @@ struct clk {
34 void (*init)(struct clk *); 61 void (*init)(struct clk *);
35 int (*enable)(struct clk *); 62 int (*enable)(struct clk *);
36 void (*disable)(struct clk *); 63 void (*disable)(struct clk *);
64#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
65 u8 fixed_div;
66 void __iomem *clksel_reg;
67 u32 clksel_mask;
68 const struct clksel *clksel;
69 const struct dpll_data *dpll_data;
70#else
71 __u8 rate_offset;
72 __u8 src_offset;
73#endif
37}; 74};
38 75
39struct clk_functions { 76struct clk_functions {
@@ -54,10 +91,12 @@ extern int clk_init(struct clk_functions * custom_clocks);
54extern int clk_register(struct clk *clk); 91extern int clk_register(struct clk *clk);
55extern void clk_unregister(struct clk *clk); 92extern void clk_unregister(struct clk *clk);
56extern void propagate_rate(struct clk *clk); 93extern void propagate_rate(struct clk *clk);
94extern void recalculate_root_clocks(void);
57extern void followparent_recalc(struct clk * clk); 95extern void followparent_recalc(struct clk * clk);
58extern void clk_allow_idle(struct clk *clk); 96extern void clk_allow_idle(struct clk *clk);
59extern void clk_deny_idle(struct clk *clk); 97extern void clk_deny_idle(struct clk *clk);
60extern int clk_get_usecount(struct clk *clk); 98extern int clk_get_usecount(struct clk *clk);
99extern void clk_enable_init_clocks(void);
61 100
62/* Clock flags */ 101/* Clock flags */
63#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ 102#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
@@ -71,21 +110,33 @@ extern int clk_get_usecount(struct clk *clk);
71#define CLOCK_NO_IDLE_PARENT (1 << 8) 110#define CLOCK_NO_IDLE_PARENT (1 << 8)
72#define DELAYED_APP (1 << 9) /* Delay application of clock */ 111#define DELAYED_APP (1 << 9) /* Delay application of clock */
73#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ 112#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
74#define CM_MPU_SEL1 (1 << 11) /* Domain divider/source */ 113#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
75#define CM_DSP_SEL1 (1 << 12) 114#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
76#define CM_GFX_SEL1 (1 << 13) 115/* bits 13-20 are currently free */
77#define CM_MODEM_SEL1 (1 << 14)
78#define CM_CORE_SEL1 (1 << 15) /* Sets divider for many */
79#define CM_CORE_SEL2 (1 << 16) /* sets parent for GPT */
80#define CM_WKUP_SEL1 (1 << 17)
81#define CM_PLL_SEL1 (1 << 18)
82#define CM_PLL_SEL2 (1 << 19)
83#define CM_SYSCLKOUT_SEL1 (1 << 20)
84#define CLOCK_IN_OMAP310 (1 << 21) 116#define CLOCK_IN_OMAP310 (1 << 21)
85#define CLOCK_IN_OMAP730 (1 << 22) 117#define CLOCK_IN_OMAP730 (1 << 22)
86#define CLOCK_IN_OMAP1510 (1 << 23) 118#define CLOCK_IN_OMAP1510 (1 << 23)
87#define CLOCK_IN_OMAP16XX (1 << 24) 119#define CLOCK_IN_OMAP16XX (1 << 24)
88#define CLOCK_IN_OMAP242X (1 << 25) 120#define CLOCK_IN_OMAP242X (1 << 25)
89#define CLOCK_IN_OMAP243X (1 << 26) 121#define CLOCK_IN_OMAP243X (1 << 26)
122#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
123#define PARENT_CONTROLS_CLOCK (1 << 28)
124#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
125#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
126
127/* Clksel_rate flags */
128#define DEFAULT_RATE (1 << 0)
129#define RATE_IN_242X (1 << 1)
130#define RATE_IN_243X (1 << 2)
131#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
132#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
133
134#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
135
136
137/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
138#define CORE_CLK_SRC_32K 0
139#define CORE_CLK_SRC_DPLL 1
140#define CORE_CLK_SRC_DPLL_X2 2
90 141
91#endif 142#endif
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
new file mode 100644
index 000000000000..9944bb5d5330
--- /dev/null
+++ b/include/asm-arm/arch-omap/control.h
@@ -0,0 +1,191 @@
1#ifndef __ASM_ARCH_CONTROL_H
2#define __ASM_ARCH_CONTROL_H
3
4/*
5 * include/asm-arm/arch-omap/control.h
6 *
7 * OMAP2/3 System Control Module definitions
8 *
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Copyright (C) 2007 Nokia Corporation
11 *
12 * Written by Paul Walmsley
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation.
17 */
18
19#include <asm/arch/io.h>
20
21#define OMAP242X_CTRL_REGADDR(reg) \
22 (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
23#define OMAP243X_CTRL_REGADDR(reg) \
24 (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
25#define OMAP343X_CTRL_REGADDR(reg) \
26 (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
27
28/*
29 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
30 * OMAP24XX and OMAP34XX.
31 */
32
33/* Control submodule offsets */
34
35#define OMAP2_CONTROL_INTERFACE 0x000
36#define OMAP2_CONTROL_PADCONFS 0x030
37#define OMAP2_CONTROL_GENERAL 0x270
38#define OMAP343X_CONTROL_MEM_WKUP 0x600
39#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
40#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
41
42/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
43
44#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
45
46/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
47#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
48#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
49#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
50#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
51#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
52#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
53#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
54#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
55#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
56#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
57#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
58#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
59
60/* 242x-only CONTROL_GENERAL register offsets */
61#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
62#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
63
64/* 243x-only CONTROL_GENERAL register offsets */
65/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
66#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
67#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
68#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
69#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
70#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
71
72/* 24xx-only CONTROL_GENERAL register offsets */
73#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
74#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
75#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
76#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
77#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
78#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
79#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
80#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
81#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
82#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
83#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074
84#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
85#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
86#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
87#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
88#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
89#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
90#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
91#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
92#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
93#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
94#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
95#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
96#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
97#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
98#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
99#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
100#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
101#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
102#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
103#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
104
105/* 34xx-only CONTROL_GENERAL register offsets */
106#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
107#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
108#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
109#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
110#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
111#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
112#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
113#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
114#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
115#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
116#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
117#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
118#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
119#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
120#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
121#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
122#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
123#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
124#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
125#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
126#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
127#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
128#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
129#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
130#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
131#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
132#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
133#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
134#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
135#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
136#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
137
138/*
139 * REVISIT: This list of registers is not comprehensive - there are more
140 * that should be added.
141 */
142
143/*
144 * Control module register bit defines - these should eventually go into
145 * their own regbits file. Some of these will be complicated, depending
146 * on the device type (general-purpose, emulator, test, secure, bad, other)
147 * and the security mode (secure, non-secure, don't care)
148 */
149/* CONTROL_DEVCONF0 bits */
150#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
151#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
152#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
153
154/* CONTROL_DEVCONF1 bits */
155#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
156#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
157#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
158
159/* CONTROL_STATUS bits */
160#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
161#define OMAP2_SYSBOOT_5_MASK (1 << 5)
162#define OMAP2_SYSBOOT_4_MASK (1 << 4)
163#define OMAP2_SYSBOOT_3_MASK (1 << 3)
164#define OMAP2_SYSBOOT_2_MASK (1 << 2)
165#define OMAP2_SYSBOOT_1_MASK (1 << 1)
166#define OMAP2_SYSBOOT_0_MASK (1 << 0)
167
168#ifndef __ASSEMBLY__
169#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
170extern void omap_ctrl_base_set(u32 base);
171extern u32 omap_ctrl_base_get(void);
172extern u8 omap_ctrl_readb(u16 offset);
173extern u16 omap_ctrl_readw(u16 offset);
174extern u32 omap_ctrl_readl(u16 offset);
175extern void omap_ctrl_writeb(u8 val, u16 offset);
176extern void omap_ctrl_writew(u16 val, u16 offset);
177extern void omap_ctrl_writel(u32 val, u16 offset);
178#else
179#define omap_ctrl_base_set(x) WARN_ON(1)
180#define omap_ctrl_base_get() 0
181#define omap_ctrl_readb(x) 0
182#define omap_ctrl_readw(x) 0
183#define omap_ctrl_readl(x) 0
184#define omap_ctrl_writeb(x, y) WARN_ON(1)
185#define omap_ctrl_writew(x, y) WARN_ON(1)
186#define omap_ctrl_writel(x, y) WARN_ON(1)
187#endif
188#endif /* __ASSEMBLY__ */
189
190#endif /* __ASM_ARCH_CONTROL_H */
191
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
index f6967c8df323..74cd57221c8e 100644
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -68,7 +68,7 @@
68 .endm 68 .endm
69 69
70 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 70 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
71 ldr \base, =VA_IC_BASE 71 ldr \base, =OMAP2_VA_IC_BASE
72 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ 72 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
73 cmp \irqnr, #0x0 73 cmp \irqnr, #0x0
74 bne 2222f 74 bne 2222f
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
index 164da09be095..86621a04cd8f 100644
--- a/include/asm-arm/arch-omap/gpio.h
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -82,62 +82,35 @@ extern void omap_set_gpio_debounce_time(int gpio, int enable);
82 82
83/*-------------------------------------------------------------------------*/ 83/*-------------------------------------------------------------------------*/
84 84
85/* wrappers for "new style" GPIO calls. the old OMAP-specfic ones should 85/* Wrappers for "new style" GPIO calls, using the new infrastructure
86 * eventually be removed (along with this errno.h inclusion), and maybe 86 * which lets us plug in FPGA, I2C, and other implementations.
87 * gpios should put MPUIOs last too. 87 * *
88 * The original OMAP-specfic calls should eventually be removed.
88 */ 89 */
89 90
90#include <asm/errno.h> 91#include <linux/errno.h>
91 92#include <asm-generic/gpio.h>
92static inline int gpio_request(unsigned gpio, const char *label)
93{
94 return omap_request_gpio(gpio);
95}
96
97static inline void gpio_free(unsigned gpio)
98{
99 omap_free_gpio(gpio);
100}
101
102static inline int __gpio_set_direction(unsigned gpio, int is_input)
103{
104 if (cpu_class_is_omap2()) {
105 if (gpio > OMAP_MAX_GPIO_LINES)
106 return -EINVAL;
107 } else {
108 if (gpio > (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */))
109 return -EINVAL;
110 }
111 omap_set_gpio_direction(gpio, is_input);
112 return 0;
113}
114
115static inline int gpio_direction_input(unsigned gpio)
116{
117 return __gpio_set_direction(gpio, 1);
118}
119
120static inline int gpio_direction_output(unsigned gpio, int value)
121{
122 omap_set_gpio_dataout(gpio, value);
123 return __gpio_set_direction(gpio, 0);
124}
125 93
126static inline int gpio_get_value(unsigned gpio) 94static inline int gpio_get_value(unsigned gpio)
127{ 95{
128 return omap_get_gpio_datain(gpio); 96 return __gpio_get_value(gpio);
129} 97}
130 98
131static inline void gpio_set_value(unsigned gpio, int value) 99static inline void gpio_set_value(unsigned gpio, int value)
132{ 100{
133 omap_set_gpio_dataout(gpio, value); 101 __gpio_set_value(gpio, value);
134} 102}
135 103
136#include <asm-generic/gpio.h> /* cansleep wrappers */ 104static inline int gpio_cansleep(unsigned gpio)
105{
106 return __gpio_cansleep(gpio);
107}
137 108
138static inline int gpio_to_irq(unsigned gpio) 109static inline int gpio_to_irq(unsigned gpio)
139{ 110{
140 return OMAP_GPIO_IRQ(gpio); 111 if (gpio < (OMAP_MAX_GPIO_LINES + 16))
112 return OMAP_GPIO_IRQ(gpio);
113 return -EINVAL;
141} 114}
142 115
143static inline int irq_to_gpio(unsigned irq) 116static inline int irq_to_gpio(unsigned irq)
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 289082d07f14..160578e1f557 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -80,6 +80,13 @@
80#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ 80#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
81#define OMAP243X_GPMC_VIRT 0xFE000000 81#define OMAP243X_GPMC_VIRT 0xFE000000
82#define OMAP243X_GPMC_SIZE SZ_1M 82#define OMAP243X_GPMC_SIZE SZ_1M
83#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
84#define OMAP243X_SDRC_VIRT 0xFD000000
85#define OMAP243X_SDRC_SIZE SZ_1M
86#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
87#define OMAP243X_SMS_VIRT 0xFC000000
88#define OMAP243X_SMS_SIZE SZ_1M
89
83#endif 90#endif
84 91
85#define IO_OFFSET 0x90000000 92#define IO_OFFSET 0x90000000
@@ -88,16 +95,73 @@
88#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ 95#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
89 96
90/* DSP */ 97/* DSP */
91#define DSP_MEM_24XX_PHYS OMAP24XX_DSP_MEM_BASE /* 0x58000000 */ 98#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
92#define DSP_MEM_24XX_VIRT 0xe0000000 99#define DSP_MEM_24XX_VIRT 0xe0000000
93#define DSP_MEM_24XX_SIZE 0x28000 100#define DSP_MEM_24XX_SIZE 0x28000
94#define DSP_IPI_24XX_PHYS OMAP24XX_DSP_IPI_BASE /* 0x59000000 */ 101#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
95#define DSP_IPI_24XX_VIRT 0xe1000000 102#define DSP_IPI_24XX_VIRT 0xe1000000
96#define DSP_IPI_24XX_SIZE SZ_4K 103#define DSP_IPI_24XX_SIZE SZ_4K
97#define DSP_MMU_24XX_PHYS OMAP24XX_DSP_MMU_BASE /* 0x5a000000 */ 104#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
98#define DSP_MMU_24XX_VIRT 0xe2000000 105#define DSP_MMU_24XX_VIRT 0xe2000000
99#define DSP_MMU_24XX_SIZE SZ_4K 106#define DSP_MMU_24XX_SIZE SZ_4K
100 107
108#elif defined(CONFIG_ARCH_OMAP3)
109
110/* We map both L3 and L4 on OMAP3 */
111#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
112#define L3_34XX_VIRT 0xf8000000
113#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
114
115#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */
116#define L4_34XX_VIRT 0xd8000000
117#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
118
119/*
120 * Need to look at the Size 4M for L4.
121 * VPOM3430 was not working for Int controller
122 */
123
124#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */
125#define L4_WK_34XX_VIRT 0xd8300000
126#define L4_WK_34XX_SIZE SZ_1M
127
128#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */
129#define L4_PER_34XX_VIRT 0xd9000000
130#define L4_PER_34XX_SIZE SZ_1M
131
132#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */
133#define L4_EMU_34XX_VIRT 0xe4000000
134#define L4_EMU_34XX_SIZE SZ_64M
135
136#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */
137#define OMAP34XX_GPMC_VIRT 0xFE000000
138#define OMAP34XX_GPMC_SIZE SZ_1M
139
140#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
141#define OMAP343X_SMS_VIRT 0xFC000000
142#define OMAP343X_SMS_SIZE SZ_1M
143
144#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
145#define OMAP343X_SDRC_VIRT 0xFD000000
146#define OMAP343X_SDRC_SIZE SZ_1M
147
148
149#define IO_OFFSET 0x90000000
150#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
151#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
152#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
153
154/* DSP */
155#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
156#define DSP_MEM_34XX_VIRT 0xe0000000
157#define DSP_MEM_34XX_SIZE 0x28000
158#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
159#define DSP_IPI_34XX_VIRT 0xe1000000
160#define DSP_IPI_34XX_SIZE SZ_4K
161#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
162#define DSP_MMU_34XX_VIRT 0xe2000000
163#define DSP_MMU_34XX_SIZE SZ_4K
164
101#endif 165#endif
102 166
103#ifndef __ASSEMBLER__ 167#ifndef __ASSEMBLER__
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index b8fff50e6a87..ff9a5b5575fd 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -4,9 +4,10 @@
4 * Table of the Omap register configurations for the FUNC_MUX and 4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations. 5 * PULL_DWN combinations.
6 * 6 *
7 * Copyright (C) 2003 - 2005 Nokia Corporation 7 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
8 * Copyright (C) 2003 - 2008 Nokia Corporation
8 * 9 *
9 * Written by Tony Lindgren <tony.lindgren@nokia.com> 10 * Written by Tony Lindgren
10 * 11 *
11 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 13 * it under the terms of the GNU General Public License as published by
@@ -27,14 +28,6 @@
27 * - W8 = ball 28 * - W8 = ball
28 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 29 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
29 * - MMC2_DAT0 = function 30 * - MMC2_DAT0 = function
30 *
31 * Change log:
32 * Added entry for the I2C interface. (02Feb 2004)
33 * Copyright (C) 2004 Texas Instruments
34 *
35 * Added entry for the keypad and uwire CS1. (09Mar 2004)
36 * Copyright (C) 2004 Texas Instruments
37 *
38 */ 31 */
39 32
40#ifndef __ASM_ARCH_MUX_H 33#ifndef __ASM_ARCH_MUX_H
@@ -469,7 +462,12 @@ enum omap24xx_index {
469 AA8_242X_GPIO58, 462 AA8_242X_GPIO58,
470 Y20_24XX_GPIO60, 463 Y20_24XX_GPIO60,
471 W4__24XX_GPIO74, 464 W4__24XX_GPIO74,
465 N15_24XX_GPIO85,
472 M15_24XX_GPIO92, 466 M15_24XX_GPIO92,
467 P20_24XX_GPIO93,
468 P18_24XX_GPIO95,
469 M18_24XX_GPIO96,
470 L14_24XX_GPIO97,
473 J15_24XX_GPIO99, 471 J15_24XX_GPIO99,
474 V14_24XX_GPIO117, 472 V14_24XX_GPIO117,
475 P14_24XX_GPIO125, 473 P14_24XX_GPIO125,
@@ -494,8 +492,6 @@ enum omap24xx_index {
494 D3_242X_DMAREQ4, 492 D3_242X_DMAREQ4,
495 E3_242X_DMAREQ5, 493 E3_242X_DMAREQ5,
496 494
497 P20_24XX_TSC_IRQ,
498
499 /* UART3 */ 495 /* UART3 */
500 K15_24XX_UART3_TX, 496 K15_24XX_UART3_TX,
501 K14_24XX_UART3_RX, 497 K14_24XX_UART3_RX,
@@ -557,13 +553,57 @@ enum omap24xx_index {
557 B3__24XX_KBR5, 553 B3__24XX_KBR5,
558 AA4_24XX_KBC2, 554 AA4_24XX_KBC2,
559 B13_24XX_KBC6, 555 B13_24XX_KBC6,
556
557 /* 2430 USB */
558 AD9_2430_USB0_PUEN,
559 Y11_2430_USB0_VP,
560 AD7_2430_USB0_VM,
561 AE7_2430_USB0_RCV,
562 AD4_2430_USB0_TXEN,
563 AF9_2430_USB0_SE0,
564 AE6_2430_USB0_DAT,
565 AD24_2430_USB1_SE0,
566 AB24_2430_USB1_RCV,
567 Y25_2430_USB1_TXEN,
568 AA26_2430_USB1_DAT,
569
570 /* 2430 HS-USB */
571 AD9_2430_USB0HS_DATA3,
572 Y11_2430_USB0HS_DATA4,
573 AD7_2430_USB0HS_DATA5,
574 AE7_2430_USB0HS_DATA6,
575 AD4_2430_USB0HS_DATA2,
576 AF9_2430_USB0HS_DATA0,
577 AE6_2430_USB0HS_DATA1,
578 AE8_2430_USB0HS_CLK,
579 AD8_2430_USB0HS_DIR,
580 AE5_2430_USB0HS_STP,
581 AE9_2430_USB0HS_NXT,
582 AC7_2430_USB0HS_DATA7,
583
584 /* 2430 McBSP */
585 AC10_2430_MCBSP2_FSX,
586 AD16_2430_MCBSP2_CLX,
587 AE13_2430_MCBSP2_DX,
588 AD13_2430_MCBSP2_DR,
589 AC10_2430_MCBSP2_FSX_OFF,
590 AD16_2430_MCBSP2_CLX_OFF,
591 AE13_2430_MCBSP2_DX_OFF,
592 AD13_2430_MCBSP2_DR_OFF,
593
594};
595
596struct omap_mux_cfg {
597 struct pin_config *pins;
598 unsigned long size;
599 int (*cfg_reg)(const struct pin_config *cfg);
560}; 600};
561 601
562#ifdef CONFIG_OMAP_MUX 602#ifdef CONFIG_OMAP_MUX
563/* setup pin muxing in Linux */ 603/* setup pin muxing in Linux */
564extern int omap1_mux_init(void); 604extern int omap1_mux_init(void);
565extern int omap2_mux_init(void); 605extern int omap2_mux_init(void);
566extern int omap_mux_register(struct pin_config * pins, unsigned long size); 606extern int omap_mux_register(struct omap_mux_cfg *);
567extern int omap_cfg_reg(unsigned long reg_cfg); 607extern int omap_cfg_reg(unsigned long reg_cfg);
568#else 608#else
569/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ 609/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index 14c0f9496579..b9fcaae287c8 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -1,3 +1,28 @@
1/*
2 * include/asm-arm/arch-omap/omap24xx.h
3 *
4 * This file contains the processor specific definitions
5 * of the TI OMAP24XX.
6 *
7 * Copyright (C) 2007 Texas Instruments.
8 * Copyright (C) 2007 Nokia Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
1#ifndef __ASM_ARCH_OMAP24XX_H 26#ifndef __ASM_ARCH_OMAP24XX_H
2#define __ASM_ARCH_OMAP24XX_H 27#define __ASM_ARCH_OMAP24XX_H
3 28
@@ -13,33 +38,70 @@
13 38
14/* interrupt controller */ 39/* interrupt controller */
15#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
16#define VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
17#define OMAP24XX_IVA_INTC_BASE 0x40000000 41#define OMAP24XX_IVA_INTC_BASE 0x40000000
18#define IRQ_SIR_IRQ 0x0040 42#define IRQ_SIR_IRQ 0x0040
19 43
20#ifdef CONFIG_ARCH_OMAP2420 44#define OMAP2420_CTRL_BASE L4_24XX_BASE
21#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 45#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
22#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000) 46#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
23#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000) 47#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
24#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) 48#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
25#endif 49#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
50#define OMAP2420_SMS_BASE 0x68008000
26 51
27#ifdef CONFIG_ARCH_OMAP2430 52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
28#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) 53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
29#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000) 54#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
30#define OMAP24XX_SDRC_BASE (0x6D000000) 55#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
31#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) 56
57#define OMAP243X_SMS_BASE 0x6C000000
58#define OMAP243X_SDRC_BASE 0x6D000000
32#define OMAP243X_GPMC_BASE 0x6E000000 59#define OMAP243X_GPMC_BASE 0x6E000000
33#endif 60#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
61#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
62#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
34 63
35/* DSP SS */ 64/* DSP SS */
36#define OMAP24XX_DSP_BASE 0x58000000 65#define OMAP2420_DSP_BASE 0x58000000
37#define OMAP24XX_DSP_MEM_BASE (OMAP24XX_DSP_BASE + 0x0) 66#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
38#define OMAP24XX_DSP_IPI_BASE (OMAP24XX_DSP_BASE + 0x1000000) 67#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
39#define OMAP24XX_DSP_MMU_BASE (OMAP24XX_DSP_BASE + 0x2000000) 68#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
69
70#define OMAP243X_DSP_BASE 0x5C000000
71#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
72#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
40 73
41/* Mailbox */ 74/* Mailbox */
42#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000) 75#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
43 76
77/* Camera */
78#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
79
80/* Security */
81#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
82#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
83#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
84#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
85#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
86#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
87
88#if defined(CONFIG_ARCH_OMAP2420)
89
90#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE
91#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE
92#define OMAP2_CM_BASE OMAP2420_CM_BASE
93#define OMAP2_PRM_BASE OMAP2420_PRM_BASE
94#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
95
96#elif defined(CONFIG_ARCH_OMAP2430)
97
98#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE
99#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE
100#define OMAP2_CM_BASE OMAP2430_CM_BASE
101#define OMAP2_PRM_BASE OMAP2430_PRM_BASE
102#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
103
104#endif
105
44#endif /* __ASM_ARCH_OMAP24XX_H */ 106#endif /* __ASM_ARCH_OMAP24XX_H */
45 107
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
new file mode 100644
index 000000000000..673b3965befc
--- /dev/null
+++ b/include/asm-arm/arch-omap/sdrc.h
@@ -0,0 +1,75 @@
1#ifndef ____ASM_ARCH_SDRC_H
2#define ____ASM_ARCH_SDRC_H
3
4/*
5 * OMAP2/3 SDRC/SMS register definitions
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <asm/arch/io.h>
18
19/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
20
21#define SDRC_SYSCONFIG 0x010
22#define SDRC_DLLA_CTRL 0x060
23#define SDRC_DLLA_STATUS 0x064
24#define SDRC_DLLB_CTRL 0x068
25#define SDRC_DLLB_STATUS 0x06C
26#define SDRC_POWER 0x070
27#define SDRC_MR_0 0x084
28#define SDRC_RFR_CTRL_0 0x0a4
29
30/*
31 * These values represent the number of memory clock cycles between
32 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
33 * rows per device, and include a subtraction of a 50 cycle window in the
34 * event that the autorefresh command is delayed due to other SDRC activity.
35 * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
36 * counter reaches 0.
37 *
38 * These represent optimal values for common parts, it won't work for all.
39 * As long as you scale down, most parameters are still work, they just
40 * become sub-optimal. The RFR value goes in the opposite direction. If you
41 * don't adjust it down as your clock period increases the refresh interval
42 * will not be met. Setting all parameters for complete worst case may work,
43 * but may cut memory performance by 2x. Due to errata the DLLs need to be
44 * unlocked and their value needs run time calibration. A dynamic call is
45 * need for that as no single right value exists acorss production samples.
46 *
47 * Only the FULL speed values are given. Current code is such that rate
48 * changes must be made at DPLLoutx2. The actual value adjustment for low
49 * frequency operation will be handled by omap_set_performance()
50 *
51 * By having the boot loader boot up in the fastest L4 speed available likely
52 * will result in something which you can switch between.
53 */
54#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
55#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
56#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
57#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
58#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
59
60
61/*
62 * SMS register access
63 */
64
65
66#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
67#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
68#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
69
70/* SMS register offsets - read/write with sms_{read,write}_reg() */
71
72#define SMS_SYSCONFIG 0x010
73/* REVISIT: fill in other SMS registers here */
74
75#endif
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 99ae9eabaf71..2147d18aaeae 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -132,14 +132,11 @@
132# define CONF_USB_PWRDN_DP_R (1 << 1) 132# define CONF_USB_PWRDN_DP_R (1 << 1)
133 133
134/* OMAP2 */ 134/* OMAP2 */
135#define CONTROL_DEVCONF_REG __REG32(L4_24XX_BASE + 0x0274)
136# define USB_UNIDIR 0x0 135# define USB_UNIDIR 0x0
137# define USB_UNIDIR_TLL 0x1 136# define USB_UNIDIR_TLL 0x1
138# define USB_BIDIR 0x2 137# define USB_BIDIR 0x2
139# define USB_BIDIR_TLL 0x3 138# define USB_BIDIR_TLL 0x3
140# define USBT0WRMODEI(x) ((x) << 22) 139# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
141# define USBT1WRMODEI(x) ((x) << 20)
142# define USBT2WRMODEI(x) ((x) << 18)
143# define USBT2TLL5PI (1 << 17) 140# define USBT2TLL5PI (1 << 17)
144# define USB0PUENACTLOI (1 << 16) 141# define USB0PUENACTLOI (1 << 16)
145# define USBSTANDBYCTRL (1 << 15) 142# define USBSTANDBYCTRL (1 << 15)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 21:03:54 -0500