1 files changed, 4 insertions, 400 deletions
diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h
index 7b48a5cbb15f..7bcaf94bde9f 100644
--- a/include/asm-arm/arch-omap/prcm.h
+++ b/include/asm-arm/arch-omap/prcm.h
@@ -1,5 +1,7 @@
 /*
- * prcm.h - Access definations for use in OMAP24XX clock and power management
+ * linux/include/asm-arm/arch-omap/prcm.h
+ *
+ * Access definations for use in OMAP24XX clock and power management
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 *
@@ -21,405 +23,7 @@
 #ifndef __ASM_ARM_ARCH_DPM_PRCM_H
 #define __ASM_ARM_ARCH_DPM_PRCM_H
-/* SET_PERFORMANCE_LEVEL PARAMETERS */
+u32 omap_prcm_get_reset_sources(void);
-#define PRCM_HALF_SPEED 1
-#define PRCM_FULL_SPEED 2
-#ifndef __ASSEMBLER__
-#define PRCM_REG32(offset)      __REG32(OMAP24XX_PRCM_BASE + (offset))
-#define PRCM_REVISION           PRCM_REG32(0x000)
-#define PRCM_SYSCONFIG          PRCM_REG32(0x010)
-#define PRCM_IRQSTATUS_MPU      PRCM_REG32(0x018)
-#define PRCM_IRQENABLE_MPU      PRCM_REG32(0x01C)
-#define PRCM_VOLTCTRL           PRCM_REG32(0x050)
-#define PRCM_VOLTST             PRCM_REG32(0x054)
-#define PRCM_CLKSRC_CTRL        PRCM_REG32(0x060)
-#define PRCM_CLKOUT_CTRL        PRCM_REG32(0x070)
-#define PRCM_CLKEMUL_CTRL       PRCM_REG32(0x078)
-#define PRCM_CLKCFG_CTRL        PRCM_REG32(0x080)
-#define PRCM_CLKCFG_STATUS      PRCM_REG32(0x084)
-#define PRCM_VOLTSETUP          PRCM_REG32(0x090)
-#define PRCM_CLKSSETUP          PRCM_REG32(0x094)
-#define PRCM_POLCTRL            PRCM_REG32(0x098)
-/* GENERAL PURPOSE */
-#define GENERAL_PURPOSE1        PRCM_REG32(0x0B0)
-#define GENERAL_PURPOSE2        PRCM_REG32(0x0B4)
-#define GENERAL_PURPOSE3        PRCM_REG32(0x0B8)
-#define GENERAL_PURPOSE4        PRCM_REG32(0x0BC)
-#define GENERAL_PURPOSE5        PRCM_REG32(0x0C0)
-#define GENERAL_PURPOSE6        PRCM_REG32(0x0C4)
-#define GENERAL_PURPOSE7        PRCM_REG32(0x0C8)
-#define GENERAL_PURPOSE8        PRCM_REG32(0x0CC)
-#define GENERAL_PURPOSE9        PRCM_REG32(0x0D0)
-#define GENERAL_PURPOSE10       PRCM_REG32(0x0D4)
-#define GENERAL_PURPOSE11       PRCM_REG32(0x0D8)
-#define GENERAL_PURPOSE12       PRCM_REG32(0x0DC)
-#define GENERAL_PURPOSE13       PRCM_REG32(0x0E0)
-#define GENERAL_PURPOSE14       PRCM_REG32(0x0E4)
-#define GENERAL_PURPOSE15       PRCM_REG32(0x0E8)
-#define GENERAL_PURPOSE16       PRCM_REG32(0x0EC)
-#define GENERAL_PURPOSE17       PRCM_REG32(0x0F0)
-#define GENERAL_PURPOSE18       PRCM_REG32(0x0F4)
-#define GENERAL_PURPOSE19       PRCM_REG32(0x0F8)
-#define GENERAL_PURPOSE20       PRCM_REG32(0x0FC)
-/* MPU */
-#define CM_CLKSEL_MPU           PRCM_REG32(0x140)
-#define CM_CLKSTCTRL_MPU        PRCM_REG32(0x148)
-#define RM_RSTST_MPU            PRCM_REG32(0x158)
-#define PM_WKDEP_MPU            PRCM_REG32(0x1C8)
-#define PM_EVGENCTRL_MPU        PRCM_REG32(0x1D4)
-#define PM_EVEGENONTIM_MPU      PRCM_REG32(0x1D8)
-#define PM_EVEGENOFFTIM_MPU     PRCM_REG32(0x1DC)
-#define PM_PWSTCTRL_MPU         PRCM_REG32(0x1E0)
-#define PM_PWSTST_MPU           PRCM_REG32(0x1E4)
-/* CORE */
-#define CM_FCLKEN1_CORE         PRCM_REG32(0x200)
-#define CM_FCLKEN2_CORE         PRCM_REG32(0x204)
-#define CM_FCLKEN3_CORE         PRCM_REG32(0x208)
-#define CM_ICLKEN1_CORE         PRCM_REG32(0x210)
-#define CM_ICLKEN2_CORE         PRCM_REG32(0x214)
-#define CM_ICLKEN3_CORE         PRCM_REG32(0x218)
-#define CM_ICLKEN4_CORE         PRCM_REG32(0x21C)
-#define CM_IDLEST1_CORE         PRCM_REG32(0x220)
-#define CM_IDLEST2_CORE         PRCM_REG32(0x224)
-#define CM_IDLEST3_CORE         PRCM_REG32(0x228)
-#define CM_IDLEST4_CORE         PRCM_REG32(0x22C)
-#define CM_AUTOIDLE1_CORE       PRCM_REG32(0x230)
-#define CM_AUTOIDLE2_CORE       PRCM_REG32(0x234)
-#define CM_AUTOIDLE3_CORE       PRCM_REG32(0x238)
-#define CM_AUTOIDLE4_CORE       PRCM_REG32(0x23C)
-#define CM_CLKSEL1_CORE         PRCM_REG32(0x240)
-#define CM_CLKSEL2_CORE         PRCM_REG32(0x244)
-#define CM_CLKSTCTRL_CORE       PRCM_REG32(0x248)
-#define PM_WKEN1_CORE           PRCM_REG32(0x2A0)
-#define PM_WKEN2_CORE           PRCM_REG32(0x2A4)
-#define PM_WKST1_CORE           PRCM_REG32(0x2B0)
-#define PM_WKST2_CORE           PRCM_REG32(0x2B4)
-#define PM_WKDEP_CORE           PRCM_REG32(0x2C8)
-#define PM_PWSTCTRL_CORE        PRCM_REG32(0x2E0)
-#define PM_PWSTST_CORE          PRCM_REG32(0x2E4)
-/* GFX */
-#define CM_FCLKEN_GFX           PRCM_REG32(0x300)
-#define CM_ICLKEN_GFX           PRCM_REG32(0x310)
-#define CM_IDLEST_GFX           PRCM_REG32(0x320)
-#define CM_CLKSEL_GFX           PRCM_REG32(0x340)
-#define CM_CLKSTCTRL_GFX        PRCM_REG32(0x348)
-#define RM_RSTCTRL_GFX          PRCM_REG32(0x350)
-#define RM_RSTST_GFX            PRCM_REG32(0x358)
-#define PM_WKDEP_GFX            PRCM_REG32(0x3C8)
-#define PM_PWSTCTRL_GFX         PRCM_REG32(0x3E0)
-#define PM_PWSTST_GFX           PRCM_REG32(0x3E4)
-/* WAKE-UP */
-#define CM_FCLKEN_WKUP          PRCM_REG32(0x400)
-#define CM_ICLKEN_WKUP          PRCM_REG32(0x410)
-#define CM_IDLEST_WKUP          PRCM_REG32(0x420)
-#define CM_AUTOIDLE_WKUP        PRCM_REG32(0x430)
-#define CM_CLKSEL_WKUP          PRCM_REG32(0x440)
-#define RM_RSTCTRL_WKUP         PRCM_REG32(0x450)
-#define RM_RSTTIME_WKUP         PRCM_REG32(0x454)
-#define RM_RSTST_WKUP           PRCM_REG32(0x458)
-#define PM_WKEN_WKUP            PRCM_REG32(0x4A0)
-#define PM_WKST_WKUP            PRCM_REG32(0x4B0)
-/* CLOCKS */
-#define CM_CLKEN_PLL            PRCM_REG32(0x500)
-#define CM_IDLEST_CKGEN         PRCM_REG32(0x520)
-#define CM_AUTOIDLE_PLL         PRCM_REG32(0x530)
-#define CM_CLKSEL1_PLL          PRCM_REG32(0x540)
-#define CM_CLKSEL2_PLL          PRCM_REG32(0x544)
-/* DSP */
-#define CM_FCLKEN_DSP           PRCM_REG32(0x800)
-#define CM_ICLKEN_DSP           PRCM_REG32(0x810)
-#define CM_IDLEST_DSP           PRCM_REG32(0x820)
-#define CM_AUTOIDLE_DSP         PRCM_REG32(0x830)
-#define CM_CLKSEL_DSP           PRCM_REG32(0x840)
-#define CM_CLKSTCTRL_DSP        PRCM_REG32(0x848)
-#define RM_RSTCTRL_DSP          PRCM_REG32(0x850)
-#define RM_RSTST_DSP            PRCM_REG32(0x858)
-#define PM_WKEN_DSP             PRCM_REG32(0x8A0)
-#define PM_WKDEP_DSP            PRCM_REG32(0x8C8)
-#define PM_PWSTCTRL_DSP         PRCM_REG32(0x8E0)
-#define PM_PWSTST_DSP           PRCM_REG32(0x8E4)
-#define PRCM_IRQSTATUS_DSP      PRCM_REG32(0x8F0)
-#define PRCM_IRQENABLE_DSP      PRCM_REG32(0x8F4)
-/* IVA */
-#define PRCM_IRQSTATUS_IVA      PRCM_REG32(0x8F8)
-#define PRCM_IRQENABLE_IVA      PRCM_REG32(0x8FC)
-/* Modem on 2430 */
-#define CM_FCLKEN_MDM           PRCM_REG32(0xC00)
-#define CM_ICLKEN_MDM           PRCM_REG32(0xC10)
-#define CM_IDLEST_MDM           PRCM_REG32(0xC20)
-#define CM_CLKSEL_MDM           PRCM_REG32(0xC40)
-/* FIXME: Move to header for 2430 */
-#define DISP_BASE               (OMAP24XX_L4_IO_BASE+0x50000)
-#define DISP_REG32(offset)      __REG32(DISP_BASE + (offset))
-#define OMAP24XX_GPMC_BASE      (L3_24XX_BASE + 0xa000)
-#define GPMC_BASE               (OMAP24XX_GPMC_BASE)
-#define GPMC_REG32(offset)      __REG32(GPMC_BASE + (offset))
-#define GPT1_BASE               (OMAP24XX_GPT1)
-#define GPT1_REG32(offset)      __REG32(GPT1_BASE + (offset))
-/* Misc sysconfig */
-#define DISPC_SYSCONFIG         DISP_REG32(0x410)
-#define SPI_BASE                (OMAP24XX_L4_IO_BASE+0x98000)
-#define MCSPI1_SYSCONFIG        __REG32(SPI_BASE + 0x10)
-#define MCSPI2_SYSCONFIG        __REG32(SPI_BASE+0x2000 + 0x10)
-//#define DSP_MMU_SYSCONFIG     0x5A000010
-#define CAMERA_MMU_SYSCONFIG    __REG32(DISP_BASE+0x2C10)
-//#define IVA_MMU_SYSCONFIG     0x5D000010
-//#define DSP_DMA_SYSCONFIG     0x00FCC02C
-#define CAMERA_DMA_SYSCONFIG    __REG32(DISP_BASE+0x282C)
-#define SYSTEM_DMA_SYSCONFIG    __REG32(DISP_BASE+0x602C)
-#define GPMC_SYSCONFIG          GPMC_REG32(0x010)
-#define MAILBOXES_SYSCONFIG     __REG32(OMAP24XX_L4_IO_BASE+0x94010)
-#define UART1_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE+0x6A054)
-#define UART2_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE+0x6C054)
-#define UART3_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE+0x6E054)
-//#define IVA_SYSCONFIG         0x5C060010
-#define SDRC_SYSCONFIG          __REG32(OMAP24XX_SDRC_BASE+0x10)
-#define SMS_SYSCONFIG           __REG32(OMAP24XX_SMS_BASE+0x10)
-#define SSI_SYSCONFIG           __REG32(DISP_BASE+0x8010)
-//#define VLYNQ_SYSCONFIG       0x67FFFE10
-/* rkw - good cannidates for PM_ to start what nm was trying */
-#define OMAP24XX_GPT2           (OMAP24XX_L4_IO_BASE+0x2A000)
-#define OMAP24XX_GPT3           (OMAP24XX_L4_IO_BASE+0x78000)
-#define OMAP24XX_GPT4           (OMAP24XX_L4_IO_BASE+0x7A000)
-#define OMAP24XX_GPT5           (OMAP24XX_L4_IO_BASE+0x7C000)
-#define OMAP24XX_GPT6           (OMAP24XX_L4_IO_BASE+0x7E000)
-#define OMAP24XX_GPT7           (OMAP24XX_L4_IO_BASE+0x80000)
-#define OMAP24XX_GPT8           (OMAP24XX_L4_IO_BASE+0x82000)
-#define OMAP24XX_GPT9           (OMAP24XX_L4_IO_BASE+0x84000)
-#define OMAP24XX_GPT10          (OMAP24XX_L4_IO_BASE+0x86000)
-#define OMAP24XX_GPT11          (OMAP24XX_L4_IO_BASE+0x88000)
-#define OMAP24XX_GPT12          (OMAP24XX_L4_IO_BASE+0x8A000)
-#define GPTIMER1_SYSCONFIG      GPT1_REG32(0x010)
-#define GPTIMER2_SYSCONFIG      __REG32(OMAP24XX_GPT2 + 0x10)
-#define GPTIMER3_SYSCONFIG      __REG32(OMAP24XX_GPT3 + 0x10)
-#define GPTIMER4_SYSCONFIG      __REG32(OMAP24XX_GPT4 + 0x10)
-#define GPTIMER5_SYSCONFIG      __REG32(OMAP24XX_GPT5 + 0x10)
-#define GPTIMER6_SYSCONFIG      __REG32(OMAP24XX_GPT6 + 0x10)
-#define GPTIMER7_SYSCONFIG      __REG32(OMAP24XX_GPT7 + 0x10)
-#define GPTIMER8_SYSCONFIG      __REG32(OMAP24XX_GPT8 + 0x10)
-#define GPTIMER9_SYSCONFIG      __REG32(OMAP24XX_GPT9 + 0x10)
-#define GPTIMER10_SYSCONFIG     __REG32(OMAP24XX_GPT10 + 0x10)
-#define GPTIMER11_SYSCONFIG     __REG32(OMAP24XX_GPT11 + 0x10)
-#define GPTIMER12_SYSCONFIG     __REG32(OMAP24XX_GPT12 + 0x10)
-#define GPIOX_BASE(X)           (OMAP24XX_GPIO_BASE+(0x2000*((X)-1)))
-#define GPIO1_SYSCONFIG         __REG32((GPIOX_BASE(1)+0x10))
-#define GPIO2_SYSCONFIG         __REG32((GPIOX_BASE(2)+0x10))
-#define GPIO3_SYSCONFIG         __REG32((GPIOX_BASE(3)+0x10))
-#define GPIO4_SYSCONFIG         __REG32((GPIOX_BASE(4)+0x10))
-/* GP TIMER 1 */
-#define GPTIMER1_TISTAT         GPT1_REG32(0x014)
-#define GPTIMER1_TISR           GPT1_REG32(0x018)
-#define GPTIMER1_TIER           GPT1_REG32(0x01C)
-#define GPTIMER1_TWER           GPT1_REG32(0x020)
-#define GPTIMER1_TCLR           GPT1_REG32(0x024)
-#define GPTIMER1_TCRR           GPT1_REG32(0x028)
-#define GPTIMER1_TLDR           GPT1_REG32(0x02C)
-#define GPTIMER1_TTGR           GPT1_REG32(0x030)
-#define GPTIMER1_TWPS           GPT1_REG32(0x034)
-#define GPTIMER1_TMAR           GPT1_REG32(0x038)
-#define GPTIMER1_TCAR1          GPT1_REG32(0x03C)
-#define GPTIMER1_TSICR          GPT1_REG32(0x040)
-#define GPTIMER1_TCAR2          GPT1_REG32(0x044)
-/* rkw -- base fix up please... */
-#define GPTIMER3_TISR           __REG32(OMAP24XX_L4_IO_BASE+0x78018)
-/* SDRC */
-#define SDRC_DLLA_CTRL          __REG32(OMAP24XX_SDRC_BASE+0x060)
-#define SDRC_DLLA_STATUS        __REG32(OMAP24XX_SDRC_BASE+0x064)
-#define SDRC_DLLB_CTRL          __REG32(OMAP24XX_SDRC_BASE+0x068)
-#define SDRC_DLLB_STATUS        __REG32(OMAP24XX_SDRC_BASE+0x06C)
-#define SDRC_POWER              __REG32(OMAP24XX_SDRC_BASE+0x070)
-#define SDRC_MR_0               __REG32(OMAP24XX_SDRC_BASE+0x084)
-/* GPIO 1 */
-#define GPIO1_BASE              GPIOX_BASE(1)
-#define GPIO1_REG32(offset)     __REG32(GPIO1_BASE + (offset))
-#define GPIO1_IRQENABLE1        GPIO1_REG32(0x01C)
-#define GPIO1_IRQSTATUS1        GPIO1_REG32(0x018)
-#define GPIO1_IRQENABLE2        GPIO1_REG32(0x02C)
-#define GPIO1_IRQSTATUS2        GPIO1_REG32(0x028)
-#define GPIO1_WAKEUPENABLE      GPIO1_REG32(0x020)
-#define GPIO1_RISINGDETECT      GPIO1_REG32(0x048)
-#define GPIO1_DATAIN            GPIO1_REG32(0x038)
-#define GPIO1_OE                GPIO1_REG32(0x034)
-#define GPIO1_DATAOUT           GPIO1_REG32(0x03C)
-/* GPIO2 */
-#define GPIO2_BASE              GPIOX_BASE(2)
-#define GPIO2_REG32(offset)     __REG32(GPIO2_BASE + (offset))
-#define GPIO2_IRQENABLE1        GPIO2_REG32(0x01C)
-#define GPIO2_IRQSTATUS1        GPIO2_REG32(0x018)
-#define GPIO2_IRQENABLE2        GPIO2_REG32(0x02C)
-#define GPIO2_IRQSTATUS2        GPIO2_REG32(0x028)
-#define GPIO2_WAKEUPENABLE      GPIO2_REG32(0x020)
-#define GPIO2_RISINGDETECT      GPIO2_REG32(0x048)
-#define GPIO2_DATAIN            GPIO2_REG32(0x038)
-#define GPIO2_OE                GPIO2_REG32(0x034)
-#define GPIO2_DATAOUT           GPIO2_REG32(0x03C)
-/* GPIO 3 */
-#define GPIO3_BASE              GPIOX_BASE(3)
-#define GPIO3_REG32(offset)     __REG32(GPIO3_BASE + (offset))
-#define GPIO3_IRQENABLE1        GPIO3_REG32(0x01C)
-#define GPIO3_IRQSTATUS1        GPIO3_REG32(0x018)
-#define GPIO3_IRQENABLE2        GPIO3_REG32(0x02C)
-#define GPIO3_IRQSTATUS2        GPIO3_REG32(0x028)
-#define GPIO3_WAKEUPENABLE      GPIO3_REG32(0x020)
-#define GPIO3_RISINGDETECT      GPIO3_REG32(0x048)
-#define GPIO3_FALLINGDETECT     GPIO3_REG32(0x04C)
-#define GPIO3_DATAIN            GPIO3_REG32(0x038)
-#define GPIO3_OE                GPIO3_REG32(0x034)
-#define GPIO3_DATAOUT           GPIO3_REG32(0x03C)
-#define GPIO3_DEBOUNCENABLE     GPIO3_REG32(0x050)
-#define GPIO3_DEBOUNCINGTIME    GPIO3_REG32(0x054)
-/* GPIO 4 */
-#define GPIO4_BASE              GPIOX_BASE(4)
-#define GPIO4_REG32(offset)     __REG32(GPIO4_BASE + (offset))
-#define GPIO4_IRQENABLE1        GPIO4_REG32(0x01C)
-#define GPIO4_IRQSTATUS1        GPIO4_REG32(0x018)
-#define GPIO4_IRQENABLE2        GPIO4_REG32(0x02C)
-#define GPIO4_IRQSTATUS2        GPIO4_REG32(0x028)
-#define GPIO4_WAKEUPENABLE      GPIO4_REG32(0x020)
-#define GPIO4_RISINGDETECT      GPIO4_REG32(0x048)
-#define GPIO4_FALLINGDETECT     GPIO4_REG32(0x04C)
-#define GPIO4_DATAIN            GPIO4_REG32(0x038)
-#define GPIO4_OE                GPIO4_REG32(0x034)
-#define GPIO4_DATAOUT           GPIO4_REG32(0x03C)
-#define GPIO4_DEBOUNCENABLE     GPIO4_REG32(0x050)
-#define GPIO4_DEBOUNCINGTIME    GPIO4_REG32(0x054)
-/* IO CONFIG */
-#define CONTROL_BASE            (OMAP24XX_CTRL_BASE)
-#define CONTROL_REG32(offset)   __REG32(CONTROL_BASE + (offset))
-#define CONTROL_PADCONF_SPI1_NCS2       CONTROL_REG32(0x104)
-#define CONTROL_PADCONF_SYS_XTALOUT     CONTROL_REG32(0x134)
-#define CONTROL_PADCONF_UART1_RX        CONTROL_REG32(0x0C8)
-#define CONTROL_PADCONF_MCBSP1_DX       CONTROL_REG32(0x10C)
-#define CONTROL_PADCONF_GPMC_NCS4       CONTROL_REG32(0x090)
-#define CONTROL_PADCONF_DSS_D5          CONTROL_REG32(0x0B8)
-#define CONTROL_PADCONF_DSS_D9          CONTROL_REG32(0x0BC)
-#define CONTROL_PADCONF_DSS_D13         CONTROL_REG32(0x0C0)
-#define CONTROL_PADCONF_DSS_VSYNC       CONTROL_REG32(0x0CC)
-/* CONTROL */
-#define CONTROL_DEVCONF         CONTROL_REG32(0x274)
-/* INTERRUPT CONTROLLER */
-#define INTC_BASE               (OMAP24XX_L4_IO_BASE+0xfe000)
-#define INTC_REG32(offset)      __REG32(INTC_BASE + (offset))
-#define INTC1_U_BASE            INTC_REG32(0x000)
-#define INTC_MIR0               INTC_REG32(0x084)
-#define INTC_MIR_SET0           INTC_REG32(0x08C)
-#define INTC_MIR_CLEAR0         INTC_REG32(0x088)
-#define INTC_ISR_CLEAR0         INTC_REG32(0x094)
-#define INTC_MIR1               INTC_REG32(0x0A4)
-#define INTC_MIR_SET1           INTC_REG32(0x0AC)
-#define INTC_MIR_CLEAR1         INTC_REG32(0x0A8)
-#define INTC_ISR_CLEAR1         INTC_REG32(0x0B4)
-#define INTC_MIR2               INTC_REG32(0x0C4)
-#define INTC_MIR_SET2           INTC_REG32(0x0CC)
-#define INTC_MIR_CLEAR2         INTC_REG32(0x0C8)
-#define INTC_ISR_CLEAR2         INTC_REG32(0x0D4)
-#define INTC_SIR_IRQ            INTC_REG32(0x040)
-#define INTC_CONTROL            INTC_REG32(0x048)
-#define INTC_ILR11              INTC_REG32(0x12C)
-#define INTC_ILR32              INTC_REG32(0x180)
-#define INTC_ILR37              INTC_REG32(0x194)
-#define INTC_SYSCONFIG          INTC_REG32(0x010)
-/* RAM FIREWALL */
-#define RAMFW_BASE              (0x68005000)
-#define RAMFW_REG32(offset)     __REG32(RAMFW_BASE + (offset))
-#define RAMFW_REQINFOPERM0      RAMFW_REG32(0x048)
-#define RAMFW_READPERM0         RAMFW_REG32(0x050)
-#define RAMFW_WRITEPERM0        RAMFW_REG32(0x058)
-/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
-//#define DEBUG_BOARD_LED_REGISTER 0x04000014
-/* GPMC CS0 */
-#define GPMC_CONFIG1_0          GPMC_REG32(0x060)
-#define GPMC_CONFIG2_0          GPMC_REG32(0x064)
-#define GPMC_CONFIG3_0          GPMC_REG32(0x068)
-#define GPMC_CONFIG4_0          GPMC_REG32(0x06C)
-#define GPMC_CONFIG5_0          GPMC_REG32(0x070)
-#define GPMC_CONFIG6_0          GPMC_REG32(0x074)
-#define GPMC_CONFIG7_0          GPMC_REG32(0x078)
-/* GPMC CS1 */
-#define GPMC_CONFIG1_1          GPMC_REG32(0x090)
-#define GPMC_CONFIG2_1          GPMC_REG32(0x094)
-#define GPMC_CONFIG3_1          GPMC_REG32(0x098)
-#define GPMC_CONFIG4_1          GPMC_REG32(0x09C)
-#define GPMC_CONFIG5_1          GPMC_REG32(0x0a0)
-#define GPMC_CONFIG6_1          GPMC_REG32(0x0a4)
-#define GPMC_CONFIG7_1          GPMC_REG32(0x0a8)
-/* DSS */
-#define DSS_CONTROL             DISP_REG32(0x040)
-#define DISPC_CONTROL           DISP_REG32(0x440)
-#define DISPC_SYSSTATUS         DISP_REG32(0x414)
-#define DISPC_IRQSTATUS         DISP_REG32(0x418)
-#define DISPC_IRQENABLE         DISP_REG32(0x41C)
-#define DISPC_CONFIG            DISP_REG32(0x444)
-#define DISPC_DEFAULT_COLOR0    DISP_REG32(0x44C)
-#define DISPC_DEFAULT_COLOR1    DISP_REG32(0x450)
-#define DISPC_TRANS_COLOR0      DISP_REG32(0x454)
-#define DISPC_TRANS_COLOR1      DISP_REG32(0x458)
-#define DISPC_LINE_NUMBER       DISP_REG32(0x460)
-#define DISPC_TIMING_H          DISP_REG32(0x464)
-#define DISPC_TIMING_V          DISP_REG32(0x468)
-#define DISPC_POL_FREQ          DISP_REG32(0x46C)
-#define DISPC_DIVISOR           DISP_REG32(0x470)
-#define DISPC_SIZE_DIG          DISP_REG32(0x478)
-#define DISPC_SIZE_LCD          DISP_REG32(0x47C)
-#define DISPC_GFX_BA0           DISP_REG32(0x480)
-#define DISPC_GFX_BA1           DISP_REG32(0x484)
-#define DISPC_GFX_POSITION      DISP_REG32(0x488)
-#define DISPC_GFX_SIZE          DISP_REG32(0x48C)
-#define DISPC_GFX_ATTRIBUTES    DISP_REG32(0x4A0)
-#define DISPC_GFX_FIFO_THRESHOLD        DISP_REG32(0x4A4)
-#define DISPC_GFX_ROW_INC       DISP_REG32(0x4AC)
-#define DISPC_GFX_PIXEL_INC     DISP_REG32(0x4B0)
-#define DISPC_GFX_WINDOW_SKIP   DISP_REG32(0x4B4)
-#define DISPC_GFX_TABLE_BA      DISP_REG32(0x4B8)
-#define DISPC_DATA_CYCLE1       DISP_REG32(0x5D4)
-#define DISPC_DATA_CYCLE2       DISP_REG32(0x5D8)
-#define DISPC_DATA_CYCLE3       DISP_REG32(0x5DC)
-/* Wake up define for board */
-#define GPIO97                  (1 << 1)
-#define GPIO88                  (1 << 24)
-#endif /* __ASSEMBLER__ */
 #endif

diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h index 7b48a5cbb15f..7bcaf94bde9f 100644 --- a/include/asm-arm/arch-omap/prcm.h +++ b/include/asm-arm/arch-omap/prcm.h
@@ -1,5 +1,7 @@
1	/*	1	/*
2	* prcm.h - Access definations for use in OMAP24XX clock and power management	2	* linux/include/asm-arm/arch-omap/prcm.h
		3	*
		4	* Access definations for use in OMAP24XX clock and power management
3	*	5	*
4	* Copyright (C) 2005 Texas Instruments, Inc.	6	* Copyright (C) 2005 Texas Instruments, Inc.
5	*	7	*
@@ -21,405 +23,7 @@
21	#ifndef __ASM_ARM_ARCH_DPM_PRCM_H	23	#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
22	#define __ASM_ARM_ARCH_DPM_PRCM_H	24	#define __ASM_ARM_ARCH_DPM_PRCM_H
23		25
24	/* SET_PERFORMANCE_LEVEL PARAMETERS */	26	u32 omap_prcm_get_reset_sources(void);
25	#define PRCM_HALF_SPEED 1
26	#define PRCM_FULL_SPEED 2
27
28	#ifndef __ASSEMBLER__
29
30	#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
31
32	#define PRCM_REVISION PRCM_REG32(0x000)
33	#define PRCM_SYSCONFIG PRCM_REG32(0x010)
34	#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
35	#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
36	#define PRCM_VOLTCTRL PRCM_REG32(0x050)
37	#define PRCM_VOLTST PRCM_REG32(0x054)
38	#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
39	#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
40	#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
41	#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
42	#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
43	#define PRCM_VOLTSETUP PRCM_REG32(0x090)
44	#define PRCM_CLKSSETUP PRCM_REG32(0x094)
45	#define PRCM_POLCTRL PRCM_REG32(0x098)
46
47	/* GENERAL PURPOSE */
48	#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
49	#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
50	#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
51	#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
52	#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
53	#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
54	#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
55	#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
56	#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
57	#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
58	#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
59	#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
60	#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
61	#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
62	#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
63	#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
64	#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
65	#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
66	#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
67	#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
68
69	/* MPU */
70	#define CM_CLKSEL_MPU PRCM_REG32(0x140)
71	#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
72	#define RM_RSTST_MPU PRCM_REG32(0x158)
73	#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
74	#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
75	#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
76	#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
77	#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
78	#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
79
80	/* CORE */
81	#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
82	#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
83	#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
84	#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
85	#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
86	#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
87	#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
88	#define CM_IDLEST1_CORE PRCM_REG32(0x220)
89	#define CM_IDLEST2_CORE PRCM_REG32(0x224)
90	#define CM_IDLEST3_CORE PRCM_REG32(0x228)
91	#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
92	#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
93	#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
94	#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
95	#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
96	#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
97	#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
98	#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
99	#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
100	#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
101	#define PM_WKST1_CORE PRCM_REG32(0x2B0)
102	#define PM_WKST2_CORE PRCM_REG32(0x2B4)
103	#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
104	#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
105	#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
106
107	/* GFX */
108	#define CM_FCLKEN_GFX PRCM_REG32(0x300)
109	#define CM_ICLKEN_GFX PRCM_REG32(0x310)
110	#define CM_IDLEST_GFX PRCM_REG32(0x320)
111	#define CM_CLKSEL_GFX PRCM_REG32(0x340)
112	#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
113	#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
114	#define RM_RSTST_GFX PRCM_REG32(0x358)
115	#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
116	#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
117	#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
118
119	/* WAKE-UP */
120	#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
121	#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
122	#define CM_IDLEST_WKUP PRCM_REG32(0x420)
123	#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
124	#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
125	#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
126	#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
127	#define RM_RSTST_WKUP PRCM_REG32(0x458)
128	#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
129	#define PM_WKST_WKUP PRCM_REG32(0x4B0)
130
131	/* CLOCKS */
132	#define CM_CLKEN_PLL PRCM_REG32(0x500)
133	#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
134	#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
135	#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
136	#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
137
138	/* DSP */
139	#define CM_FCLKEN_DSP PRCM_REG32(0x800)
140	#define CM_ICLKEN_DSP PRCM_REG32(0x810)
141	#define CM_IDLEST_DSP PRCM_REG32(0x820)
142	#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
143	#define CM_CLKSEL_DSP PRCM_REG32(0x840)
144	#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
145	#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
146	#define RM_RSTST_DSP PRCM_REG32(0x858)
147	#define PM_WKEN_DSP PRCM_REG32(0x8A0)
148	#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
149	#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
150	#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
151	#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
152	#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
153
154	/* IVA */
155	#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
156	#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
157
158	/* Modem on 2430 */
159	#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
160	#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
161	#define CM_IDLEST_MDM PRCM_REG32(0xC20)
162	#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
163
164	/* FIXME: Move to header for 2430 */
165	#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000)
166	#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
167
168	#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
169	#define GPMC_BASE (OMAP24XX_GPMC_BASE)
170	#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset))
171
172	#define GPT1_BASE (OMAP24XX_GPT1)
173	#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
174
175	/* Misc sysconfig */
176	#define DISPC_SYSCONFIG DISP_REG32(0x410)
177	#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000)
178	#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
179	#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10)
180
181	//#define DSP_MMU_SYSCONFIG 0x5A000010
182	#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10)
183	//#define IVA_MMU_SYSCONFIG 0x5D000010
184	//#define DSP_DMA_SYSCONFIG 0x00FCC02C
185	#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C)
186	#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C)
187	#define GPMC_SYSCONFIG GPMC_REG32(0x010)
188	#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010)
189	#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054)
190	#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054)
191	#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054)
192	//#define IVA_SYSCONFIG 0x5C060010
193	#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10)
194	#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10)
195	#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010)
196	//#define VLYNQ_SYSCONFIG 0x67FFFE10
197
198	/* rkw - good cannidates for PM_ to start what nm was trying */
199	#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)
200	#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)
201	#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)
202	#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)
203	#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)
204	#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)
205	#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)
206	#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)
207	#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)
208	#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)
209	#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000)
210
211	#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
212	#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
213	#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
214	#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)
215	#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)
216	#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10)
217	#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10)
218	#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10)
219	#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10)
220	#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10)
221	#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
222	#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
223
224	#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1)))
225
226	#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10))
227	#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10))
228	#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10))
229	#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10))
230
231	/* GP TIMER 1 */
232	#define GPTIMER1_TISTAT GPT1_REG32(0x014)
233	#define GPTIMER1_TISR GPT1_REG32(0x018)
234	#define GPTIMER1_TIER GPT1_REG32(0x01C)
235	#define GPTIMER1_TWER GPT1_REG32(0x020)
236	#define GPTIMER1_TCLR GPT1_REG32(0x024)
237	#define GPTIMER1_TCRR GPT1_REG32(0x028)
238	#define GPTIMER1_TLDR GPT1_REG32(0x02C)
239	#define GPTIMER1_TTGR GPT1_REG32(0x030)
240	#define GPTIMER1_TWPS GPT1_REG32(0x034)
241	#define GPTIMER1_TMAR GPT1_REG32(0x038)
242	#define GPTIMER1_TCAR1 GPT1_REG32(0x03C)
243	#define GPTIMER1_TSICR GPT1_REG32(0x040)
244	#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
245
246	/* rkw -- base fix up please... */
247	#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018)
248
249	/* SDRC */
250	#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060)
251	#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064)
252	#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068)
253	#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C)
254	#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070)
255	#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084)
256
257	/* GPIO 1 */
258	#define GPIO1_BASE GPIOX_BASE(1)
259	#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
260	#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C)
261	#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018)
262	#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C)
263	#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028)
264	#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020)
265	#define GPIO1_RISINGDETECT GPIO1_REG32(0x048)
266	#define GPIO1_DATAIN GPIO1_REG32(0x038)
267	#define GPIO1_OE GPIO1_REG32(0x034)
268	#define GPIO1_DATAOUT GPIO1_REG32(0x03C)
269
270	/* GPIO2 */
271	#define GPIO2_BASE GPIOX_BASE(2)
272	#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset))
273	#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C)
274	#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018)
275	#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C)
276	#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028)
277	#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020)
278	#define GPIO2_RISINGDETECT GPIO2_REG32(0x048)
279	#define GPIO2_DATAIN GPIO2_REG32(0x038)
280	#define GPIO2_OE GPIO2_REG32(0x034)
281	#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
282
283	/* GPIO 3 */
284	#define GPIO3_BASE GPIOX_BASE(3)
285	#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset))
286	#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C)
287	#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018)
288	#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C)
289	#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028)
290	#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020)
291	#define GPIO3_RISINGDETECT GPIO3_REG32(0x048)
292	#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C)
293	#define GPIO3_DATAIN GPIO3_REG32(0x038)
294	#define GPIO3_OE GPIO3_REG32(0x034)
295	#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
296	#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
297	#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
298
299	/* GPIO 4 */
300	#define GPIO4_BASE GPIOX_BASE(4)
301	#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset))
302	#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C)
303	#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018)
304	#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C)
305	#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028)
306	#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020)
307	#define GPIO4_RISINGDETECT GPIO4_REG32(0x048)
308	#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C)
309	#define GPIO4_DATAIN GPIO4_REG32(0x038)
310	#define GPIO4_OE GPIO4_REG32(0x034)
311	#define GPIO4_DATAOUT GPIO4_REG32(0x03C)
312	#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
313	#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
314
315
316	/* IO CONFIG */
317	#define CONTROL_BASE (OMAP24XX_CTRL_BASE)
318	#define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset))
319
320	#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
321	#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
322	#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8)
323	#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
324	#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
325	#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
326	#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC)
327	#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
328	#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
329
330	/* CONTROL */
331	#define CONTROL_DEVCONF CONTROL_REG32(0x274)
332
333	/* INTERRUPT CONTROLLER */
334	#define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000)
335	#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
336
337	#define INTC1_U_BASE INTC_REG32(0x000)
338	#define INTC_MIR0 INTC_REG32(0x084)
339	#define INTC_MIR_SET0 INTC_REG32(0x08C)
340	#define INTC_MIR_CLEAR0 INTC_REG32(0x088)
341	#define INTC_ISR_CLEAR0 INTC_REG32(0x094)
342	#define INTC_MIR1 INTC_REG32(0x0A4)
343	#define INTC_MIR_SET1 INTC_REG32(0x0AC)
344	#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8)
345	#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4)
346	#define INTC_MIR2 INTC_REG32(0x0C4)
347	#define INTC_MIR_SET2 INTC_REG32(0x0CC)
348	#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8)
349	#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
350	#define INTC_SIR_IRQ INTC_REG32(0x040)
351	#define INTC_CONTROL INTC_REG32(0x048)
352	#define INTC_ILR11 INTC_REG32(0x12C)
353	#define INTC_ILR32 INTC_REG32(0x180)
354	#define INTC_ILR37 INTC_REG32(0x194)
355	#define INTC_SYSCONFIG INTC_REG32(0x010)
356
357	/* RAM FIREWALL */
358	#define RAMFW_BASE (0x68005000)
359	#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset))
360
361	#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048)
362	#define RAMFW_READPERM0 RAMFW_REG32(0x050)
363	#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058)
364
365	/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
366	//#define DEBUG_BOARD_LED_REGISTER 0x04000014
367
368	/* GPMC CS0 */
369	#define GPMC_CONFIG1_0 GPMC_REG32(0x060)
370	#define GPMC_CONFIG2_0 GPMC_REG32(0x064)
371	#define GPMC_CONFIG3_0 GPMC_REG32(0x068)
372	#define GPMC_CONFIG4_0 GPMC_REG32(0x06C)
373	#define GPMC_CONFIG5_0 GPMC_REG32(0x070)
374	#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
375	#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
376
377	/* GPMC CS1 */
378	#define GPMC_CONFIG1_1 GPMC_REG32(0x090)
379	#define GPMC_CONFIG2_1 GPMC_REG32(0x094)
380	#define GPMC_CONFIG3_1 GPMC_REG32(0x098)
381	#define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
382	#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
383	#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
384	#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
385
386	/* DSS */
387	#define DSS_CONTROL DISP_REG32(0x040)
388	#define DISPC_CONTROL DISP_REG32(0x440)
389	#define DISPC_SYSSTATUS DISP_REG32(0x414)
390	#define DISPC_IRQSTATUS DISP_REG32(0x418)
391	#define DISPC_IRQENABLE DISP_REG32(0x41C)
392	#define DISPC_CONFIG DISP_REG32(0x444)
393	#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C)
394	#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450)
395	#define DISPC_TRANS_COLOR0 DISP_REG32(0x454)
396	#define DISPC_TRANS_COLOR1 DISP_REG32(0x458)
397	#define DISPC_LINE_NUMBER DISP_REG32(0x460)
398	#define DISPC_TIMING_H DISP_REG32(0x464)
399	#define DISPC_TIMING_V DISP_REG32(0x468)
400	#define DISPC_POL_FREQ DISP_REG32(0x46C)
401	#define DISPC_DIVISOR DISP_REG32(0x470)
402	#define DISPC_SIZE_DIG DISP_REG32(0x478)
403	#define DISPC_SIZE_LCD DISP_REG32(0x47C)
404	#define DISPC_GFX_BA0 DISP_REG32(0x480)
405	#define DISPC_GFX_BA1 DISP_REG32(0x484)
406	#define DISPC_GFX_POSITION DISP_REG32(0x488)
407	#define DISPC_GFX_SIZE DISP_REG32(0x48C)
408	#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0)
409	#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4)
410	#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC)
411	#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0)
412	#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4)
413	#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8)
414	#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4)
415	#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
416	#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
417
418	/* Wake up define for board */
419	#define GPIO97 (1 << 1)
420	#define GPIO88 (1 << 24)
421
422	#endif /* __ASSEMBLER__ */
423		27
424	#endif	28	#endif
425		29