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-rw-r--r--include/asm-arm/arch-omap/mux.h327
1 files changed, 88 insertions, 239 deletions
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 1b1ad4105349..13415a9aab06 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -4,7 +4,7 @@
4 * Table of the Omap register configurations for the FUNC_MUX and 4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations. 5 * PULL_DWN combinations.
6 * 6 *
7 * Copyright (C) 2003 Nokia Corporation 7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 * 8 *
9 * Written by Tony Lindgren <tony.lindgren@nokia.com> 9 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 * 10 *
@@ -58,6 +58,16 @@
58 .pu_pd_reg = PU_PD_SEL_##reg, \ 58 .pu_pd_reg = PU_PD_SEL_##reg, \
59 .pu_pd_val = status, 59 .pu_pd_val = status,
60 60
61#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
62 .mux_reg = OMAP730_IO_CONF_##reg, \
63 .mask_offset = mode_offset, \
64 .mask = mode,
65
66#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
67 .pull_reg = OMAP730_IO_CONF_##reg, \
68 .pull_bit = bit, \
69 .pull_val = status,
70
61#else 71#else
62 72
63#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ 73#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
@@ -71,6 +81,15 @@
71#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ 81#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
72 .pu_pd_val = status, 82 .pu_pd_val = status,
73 83
84#define MUX_REG_730(reg, mode_offset, mode) \
85 .mux_reg = OMAP730_IO_CONF_##reg, \
86 .mask_offset = mode_offset, \
87 .mask = mode,
88
89#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
90 .pull_bit = bit, \
91 .pull_val = status,
92
74#endif /* CONFIG_OMAP_MUX_DEBUG */ 93#endif /* CONFIG_OMAP_MUX_DEBUG */
75 94
76#define MUX_CFG(desc, mux_reg, mode_offset, mode, \ 95#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
@@ -84,13 +103,44 @@
84 PU_PD_REG(pu_pd_reg, pu_pd_status) \ 103 PU_PD_REG(pu_pd_reg, pu_pd_status) \
85}, 104},
86 105
106
107/*
108 * OMAP730 has a slightly different config for the pin mux.
109 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
110 * not the FUNC_MUX_CTRL_x regs from hardware.h
111 * - for pull-up/down, only has one enable bit which is is in the same register
112 * as mux config
113 */
114#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
115 pull_reg, pull_bit, pull_status, \
116 pu_pd_reg, pu_pd_status, debug_status)\
117{ \
118 .name = desc, \
119 .debug = debug_status, \
120 MUX_REG_730(mux_reg, mode_offset, mode) \
121 PULL_REG_730(mux_reg, pull_bit, pull_status) \
122 PU_PD_REG(pu_pd_reg, pu_pd_status) \
123},
124
125#define MUX_CFG_24XX(desc, reg_offset, mode, \
126 pull_en, pull_mode, dbg) \
127{ \
128 .name = desc, \
129 .debug = dbg, \
130 .mux_reg = reg_offset, \
131 .mask = mode, \
132 .pull_val = pull_en, \
133 .pu_pd_val = pull_mode, \
134},
135
136
87#define PULL_DISABLED 0 137#define PULL_DISABLED 0
88#define PULL_ENABLED 1 138#define PULL_ENABLED 1
89 139
90#define PULL_DOWN 0 140#define PULL_DOWN 0
91#define PULL_UP 1 141#define PULL_UP 1
92 142
93typedef struct { 143struct pin_config {
94 char *name; 144 char *name;
95 unsigned char busy; 145 unsigned char busy;
96 unsigned char debug; 146 unsigned char debug;
@@ -108,13 +158,23 @@ typedef struct {
108 const char *pu_pd_name; 158 const char *pu_pd_name;
109 const unsigned int pu_pd_reg; 159 const unsigned int pu_pd_reg;
110 const unsigned char pu_pd_val; 160 const unsigned char pu_pd_val;
111} reg_cfg_set; 161};
112 162
113/* 163enum omap730_index {
114 * Lookup table for FUNC_MUX and PULL_DWN register combinations for each 164 /* OMAP 730 keyboard */
115 * device. See also reg_cfg_table below for the register values. 165 E2_730_KBR0,
116 */ 166 J7_730_KBR1,
117typedef enum { 167 E1_730_KBR2,
168 F3_730_KBR3,
169 D2_730_KBR4,
170 C2_730_KBC0,
171 D3_730_KBC1,
172 E4_730_KBC2,
173 F4_730_KBC3,
174 E3_730_KBC4,
175};
176
177enum omap1xxx_index {
118 /* UART1 (BT_UART_GATING)*/ 178 /* UART1 (BT_UART_GATING)*/
119 UART1_TX = 0, 179 UART1_TX = 0,
120 UART1_RTS, 180 UART1_RTS,
@@ -331,245 +391,34 @@ typedef enum {
331 V10_1610_CF_IREQ, 391 V10_1610_CF_IREQ,
332 W10_1610_CF_RESET, 392 W10_1610_CF_RESET,
333 W11_1610_CF_CD1, 393 W11_1610_CF_CD1,
334} reg_cfg_t; 394};
335 395
336#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX) 396enum omap24xx_index {
397 /* 24xx I2C */
398 M19_24XX_I2C1_SCL,
399 L15_24XX_I2C1_SDA,
400 J15_24XX_I2C2_SCL,
401 H19_24XX_I2C2_SDA,
337 402
338/* 403 /* 24xx Menelaus interrupt */
339 * Table of various FUNC_MUX and PULL_DWN combinations for each device. 404 W19_24XX_SYS_NIRQ,
340 * See also reg_cfg_t above for the lookup table.
341 */
342static const reg_cfg_set __initdata_or_module
343reg_cfg_table[] = {
344/*
345 * description mux mode mux pull pull pull pu_pd pu dbg
346 * reg offset mode reg bit ena reg
347 */
348MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
349MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
350
351/* UART2 (COM_UART_GATING), conflicts with USB2 */
352MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
353MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
354MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
355MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
356
357/* UART3 (GIGA_UART_GATING) */
358MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
359MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
360MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
361MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
362MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
363MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
364MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
365
366/* PWT & PWL, conflicts with UART3 */
367MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
368MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
369
370/* USB internal master generic */
371MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
372MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
373/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
374MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
375MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
376MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
377MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
378
379/* USB1 master */
380MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
381MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
382MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
383MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
384MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
385MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
386MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
387MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
388MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
389MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
390MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
391
392/* USB2 master */
393MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
394MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
395MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
396MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
397MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
398MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
399MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
400
401/* OMAP-1510 GPIO */
402MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
403MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
404MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
405
406/* OMAP1610 GPIO */
407MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
408MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
409
410/* OMAP-1710 GPIO */
411MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
412MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
413MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
414MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
415
416/* MPUIO */
417MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
418MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
419MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
420MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
421
422MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
423MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
424MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
425MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
426MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
427MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
428MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
429MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
430MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
431
432/* MCBSP2 */
433MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
434MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
435MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
436MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
437MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
438MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
439
440/* MCBSP3 NOTE: Mode must 1 for clock */
441MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
442
443/* Misc ballouts */
444MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
445MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
446
447/* OMAP-1610 MMC2 */
448MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
449MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
450MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
451MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
452MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
453MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
454MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
455MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
456MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
457MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
458
459/* OMAP-1610 External Trace Interface */
460MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
461MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
462MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
463MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
464MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
465MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
466
467/* OMAP16XX GPIO */
468MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
469MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
470MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
471MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
472MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
473MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
474MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
475MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
476MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
477MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
478MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
479MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
480MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
481
482/* OMAP-1610 uWire */
483MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
484MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
485MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
486MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
487MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
488MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
489
490/* OMAP-1610 Flash */
491MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
492MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
493
494/* First MMC interface, same on 1510, 1610 and 1710 */
495MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
496MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
497MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
498MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
499MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
500MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
501MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
502MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
503MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
504
505/* OMAP-1610 USB0 alternate configuration */
506MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
507MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
508MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
509MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
510MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
511MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
512MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
513MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
514
515/* USB2 interface */
516MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
517MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
518MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
519MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
520MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
521MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
522
523/* 16XX UART */
524MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
525MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
526MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
527MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
528MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
529MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
530
531/* I2C interface */
532MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
533MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
534
535/* Keypad */
536MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
537MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
538MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
539MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
540MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
541MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
542MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
543MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
544MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
545MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
546MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
547
548/* Power management */
549MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
550
551/* MCLK Settings */
552MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
553MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
554MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
555MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
556
557/* CompactFlash controller, conflicts with MMC1 */
558MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
559MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
560MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
561MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
562MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
563};
564 405
565#endif /* __MUX_C__ */ 406 /* 24xx GPIO */
407 Y20_24XX_GPIO60,
408 M15_24XX_GPIO92,
409};
566 410
567#ifdef CONFIG_OMAP_MUX 411#ifdef CONFIG_OMAP_MUX
568/* setup pin muxing in Linux */ 412/* setup pin muxing in Linux */
569extern int omap_cfg_reg(reg_cfg_t reg_cfg); 413extern int omap1_mux_init(void);
414extern int omap2_mux_init(void);
415extern int omap_mux_register(struct pin_config * pins, unsigned long size);
416extern int omap_cfg_reg(unsigned long reg_cfg);
570#else 417#else
571/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ 418/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
572static inline int omap_cfg_reg(reg_cfg_t reg_cfg) { return 0; } 419static inline int omap1_mux_init(void) { return 0; }
420static inline int omap2_mux_init(void) { return 0; }
421static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
573#endif 422#endif
574 423
575#endif 424#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 09:25:03 -0500