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diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
deleted file mode 100644
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1/*
2 * linux/include/asm-arm/arch-omap/mcbsp.h
3 *
4 * Defines for Multi-Channel Buffered Serial Port
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H
26
27#include <linux/completion.h>
28#include <linux/spinlock.h>
29
30#include <asm/hardware.h>
31#include <asm/arch/clock.h>
32
33#define OMAP730_MCBSP1_BASE 0xfffb1000
34#define OMAP730_MCBSP2_BASE 0xfffb1800
35
36#define OMAP1510_MCBSP1_BASE 0xe1011800
37#define OMAP1510_MCBSP2_BASE 0xfffb1000
38#define OMAP1510_MCBSP3_BASE 0xe1017000
39
40#define OMAP1610_MCBSP1_BASE 0xe1011800
41#define OMAP1610_MCBSP2_BASE 0xfffb1000
42#define OMAP1610_MCBSP3_BASE 0xe1017000
43
44#define OMAP24XX_MCBSP1_BASE 0x48074000
45#define OMAP24XX_MCBSP2_BASE 0x48076000
46
47#define OMAP34XX_MCBSP1_BASE 0x48074000
48#define OMAP34XX_MCBSP2_BASE 0x49022000
49
50#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
51
52#define OMAP_MCBSP_REG_DRR2 0x00
53#define OMAP_MCBSP_REG_DRR1 0x02
54#define OMAP_MCBSP_REG_DXR2 0x04
55#define OMAP_MCBSP_REG_DXR1 0x06
56#define OMAP_MCBSP_REG_SPCR2 0x08
57#define OMAP_MCBSP_REG_SPCR1 0x0a
58#define OMAP_MCBSP_REG_RCR2 0x0c
59#define OMAP_MCBSP_REG_RCR1 0x0e
60#define OMAP_MCBSP_REG_XCR2 0x10
61#define OMAP_MCBSP_REG_XCR1 0x12
62#define OMAP_MCBSP_REG_SRGR2 0x14
63#define OMAP_MCBSP_REG_SRGR1 0x16
64#define OMAP_MCBSP_REG_MCR2 0x18
65#define OMAP_MCBSP_REG_MCR1 0x1a
66#define OMAP_MCBSP_REG_RCERA 0x1c
67#define OMAP_MCBSP_REG_RCERB 0x1e
68#define OMAP_MCBSP_REG_XCERA 0x20
69#define OMAP_MCBSP_REG_XCERB 0x22
70#define OMAP_MCBSP_REG_PCR0 0x24
71#define OMAP_MCBSP_REG_RCERC 0x26
72#define OMAP_MCBSP_REG_RCERD 0x28
73#define OMAP_MCBSP_REG_XCERC 0x2A
74#define OMAP_MCBSP_REG_XCERD 0x2C
75#define OMAP_MCBSP_REG_RCERE 0x2E
76#define OMAP_MCBSP_REG_RCERF 0x30
77#define OMAP_MCBSP_REG_XCERE 0x32
78#define OMAP_MCBSP_REG_XCERF 0x34
79#define OMAP_MCBSP_REG_RCERG 0x36
80#define OMAP_MCBSP_REG_RCERH 0x38
81#define OMAP_MCBSP_REG_XCERG 0x3A
82#define OMAP_MCBSP_REG_XCERH 0x3C
83
84#define OMAP_MAX_MCBSP_COUNT 3
85#define MAX_MCBSP_CLOCKS 3
86
87#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
88#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
89
90#define AUDIO_MCBSP OMAP_MCBSP1
91#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
92#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
93
94#elif defined(CONFIG_ARCH_OMAP24XX)
95
96#define OMAP_MCBSP_REG_DRR2 0x00
97#define OMAP_MCBSP_REG_DRR1 0x04
98#define OMAP_MCBSP_REG_DXR2 0x08
99#define OMAP_MCBSP_REG_DXR1 0x0C
100#define OMAP_MCBSP_REG_SPCR2 0x10
101#define OMAP_MCBSP_REG_SPCR1 0x14
102#define OMAP_MCBSP_REG_RCR2 0x18
103#define OMAP_MCBSP_REG_RCR1 0x1C
104#define OMAP_MCBSP_REG_XCR2 0x20
105#define OMAP_MCBSP_REG_XCR1 0x24
106#define OMAP_MCBSP_REG_SRGR2 0x28
107#define OMAP_MCBSP_REG_SRGR1 0x2C
108#define OMAP_MCBSP_REG_MCR2 0x30
109#define OMAP_MCBSP_REG_MCR1 0x34
110#define OMAP_MCBSP_REG_RCERA 0x38
111#define OMAP_MCBSP_REG_RCERB 0x3C
112#define OMAP_MCBSP_REG_XCERA 0x40
113#define OMAP_MCBSP_REG_XCERB 0x44
114#define OMAP_MCBSP_REG_PCR0 0x48
115#define OMAP_MCBSP_REG_RCERC 0x4C
116#define OMAP_MCBSP_REG_RCERD 0x50
117#define OMAP_MCBSP_REG_XCERC 0x54
118#define OMAP_MCBSP_REG_XCERD 0x58
119#define OMAP_MCBSP_REG_RCERE 0x5C
120#define OMAP_MCBSP_REG_RCERF 0x60
121#define OMAP_MCBSP_REG_XCERE 0x64
122#define OMAP_MCBSP_REG_XCERF 0x68
123#define OMAP_MCBSP_REG_RCERG 0x6C
124#define OMAP_MCBSP_REG_RCERH 0x70
125#define OMAP_MCBSP_REG_XCERG 0x74
126#define OMAP_MCBSP_REG_XCERH 0x78
127
128#define OMAP_MAX_MCBSP_COUNT 2
129#define MAX_MCBSP_CLOCKS 2
130
131#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
132#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
133
134#define AUDIO_MCBSP OMAP_MCBSP2
135#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
136#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
137
138#endif
139
140#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
141#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
142
143
144/************************** McBSP SPCR1 bit definitions ***********************/
145#define RRST 0x0001
146#define RRDY 0x0002
147#define RFULL 0x0004
148#define RSYNC_ERR 0x0008
149#define RINTM(value) ((value)<<4) /* bits 4:5 */
150#define ABIS 0x0040
151#define DXENA 0x0080
152#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
153#define RJUST(value) ((value)<<13) /* bits 13:14 */
154#define DLB 0x8000
155
156/************************** McBSP SPCR2 bit definitions ***********************/
157#define XRST 0x0001
158#define XRDY 0x0002
159#define XEMPTY 0x0004
160#define XSYNC_ERR 0x0008
161#define XINTM(value) ((value)<<4) /* bits 4:5 */
162#define GRST 0x0040
163#define FRST 0x0080
164#define SOFT 0x0100
165#define FREE 0x0200
166
167/************************** McBSP PCR bit definitions *************************/
168#define CLKRP 0x0001
169#define CLKXP 0x0002
170#define FSRP 0x0004
171#define FSXP 0x0008
172#define DR_STAT 0x0010
173#define DX_STAT 0x0020
174#define CLKS_STAT 0x0040
175#define SCLKME 0x0080
176#define CLKRM 0x0100
177#define CLKXM 0x0200
178#define FSRM 0x0400
179#define FSXM 0x0800
180#define RIOEN 0x1000
181#define XIOEN 0x2000
182#define IDLE_EN 0x4000
183
184/************************** McBSP RCR1 bit definitions ************************/
185#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
186#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
187
188/************************** McBSP XCR1 bit definitions ************************/
189#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
190#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
191
192/*************************** McBSP RCR2 bit definitions ***********************/
193#define RDATDLY(value) (value) /* Bits 0:1 */
194#define RFIG 0x0004
195#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
196#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
197#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
198#define RPHASE 0x8000
199
200/*************************** McBSP XCR2 bit definitions ***********************/
201#define XDATDLY(value) (value) /* Bits 0:1 */
202#define XFIG 0x0004
203#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
204#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
205#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
206#define XPHASE 0x8000
207
208/************************* McBSP SRGR1 bit definitions ************************/
209#define CLKGDV(value) (value) /* Bits 0:7 */
210#define FWID(value) ((value)<<8) /* Bits 8:15 */
211
212/************************* McBSP SRGR2 bit definitions ************************/
213#define FPER(value) (value) /* Bits 0:11 */
214#define FSGM 0x1000
215#define CLKSM 0x2000
216#define CLKSP 0x4000
217#define GSYNC 0x8000
218
219/************************* McBSP MCR1 bit definitions *************************/
220#define RMCM 0x0001
221#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
222#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
223#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
224
225/************************* McBSP MCR2 bit definitions *************************/
226#define XMCM(value) (value) /* Bits 0:1 */
227#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
228#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
229#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
230
231
232/* we don't do multichannel for now */
233struct omap_mcbsp_reg_cfg {
234 u16 spcr2;
235 u16 spcr1;
236 u16 rcr2;
237 u16 rcr1;
238 u16 xcr2;
239 u16 xcr1;
240 u16 srgr2;
241 u16 srgr1;
242 u16 mcr2;
243 u16 mcr1;
244 u16 pcr0;
245 u16 rcerc;
246 u16 rcerd;
247 u16 xcerc;
248 u16 xcerd;
249 u16 rcere;
250 u16 rcerf;
251 u16 xcere;
252 u16 xcerf;
253 u16 rcerg;
254 u16 rcerh;
255 u16 xcerg;
256 u16 xcerh;
257};
258
259typedef enum {
260 OMAP_MCBSP1 = 0,
261 OMAP_MCBSP2,
262 OMAP_MCBSP3,
263} omap_mcbsp_id;
264
265typedef int __bitwise omap_mcbsp_io_type_t;
266#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
267#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
268
269typedef enum {
270 OMAP_MCBSP_WORD_8 = 0,
271 OMAP_MCBSP_WORD_12,
272 OMAP_MCBSP_WORD_16,
273 OMAP_MCBSP_WORD_20,
274 OMAP_MCBSP_WORD_24,
275 OMAP_MCBSP_WORD_32,
276} omap_mcbsp_word_length;
277
278typedef enum {
279 OMAP_MCBSP_CLK_RISING = 0,
280 OMAP_MCBSP_CLK_FALLING,
281} omap_mcbsp_clk_polarity;
282
283typedef enum {
284 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
285 OMAP_MCBSP_FS_ACTIVE_LOW,
286} omap_mcbsp_fs_polarity;
287
288typedef enum {
289 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
290 OMAP_MCBSP_CLK_STP_MODE_DELAY,
291} omap_mcbsp_clk_stp_mode;
292
293
294/******* SPI specific mode **********/
295typedef enum {
296 OMAP_MCBSP_SPI_MASTER = 0,
297 OMAP_MCBSP_SPI_SLAVE,
298} omap_mcbsp_spi_mode;
299
300struct omap_mcbsp_spi_cfg {
301 omap_mcbsp_spi_mode spi_mode;
302 omap_mcbsp_clk_polarity rx_clock_polarity;
303 omap_mcbsp_clk_polarity tx_clock_polarity;
304 omap_mcbsp_fs_polarity fsx_polarity;
305 u8 clk_div;
306 omap_mcbsp_clk_stp_mode clk_stp_mode;
307 omap_mcbsp_word_length word_length;
308};
309
310/* Platform specific configuration */
311struct omap_mcbsp_ops {
312 void (*request)(unsigned int);
313 void (*free)(unsigned int);
314 int (*check)(unsigned int);
315};
316
317struct omap_mcbsp_platform_data {
318 u32 virt_base;
319 u8 dma_rx_sync, dma_tx_sync;
320 u16 rx_irq, tx_irq;
321 struct omap_mcbsp_ops *ops;
322 char const *clk_name;
323};
324
325struct omap_mcbsp {
326 struct device *dev;
327 u32 io_base;
328 u8 id;
329 u8 free;
330 omap_mcbsp_word_length rx_word_length;
331 omap_mcbsp_word_length tx_word_length;
332
333 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
334 /* IRQ based TX/RX */
335 int rx_irq;
336 int tx_irq;
337
338 /* DMA stuff */
339 u8 dma_rx_sync;
340 short dma_rx_lch;
341 u8 dma_tx_sync;
342 short dma_tx_lch;
343
344 /* Completion queues */
345 struct completion tx_irq_completion;
346 struct completion rx_irq_completion;
347 struct completion tx_dma_completion;
348 struct completion rx_dma_completion;
349
350 /* Protect the field .free, while checking if the mcbsp is in use */
351 spinlock_t lock;
352 struct omap_mcbsp_platform_data *pdata;
353 struct clk *clk;
354};
355
356int omap_mcbsp_init(void);
357void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
358 int size);
359void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
360int omap_mcbsp_request(unsigned int id);
361void omap_mcbsp_free(unsigned int id);
362void omap_mcbsp_start(unsigned int id);
363void omap_mcbsp_stop(unsigned int id);
364void omap_mcbsp_xmit_word(unsigned int id, u32 word);
365u32 omap_mcbsp_recv_word(unsigned int id);
366
367int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
368int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
369int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
370int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
371
372
373/* SPI specific API */
374void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
375
376/* Polled read/write functions */
377int omap_mcbsp_pollread(unsigned int id, u16 * buf);
378int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
379
380#endif
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