diff options
Diffstat (limited to 'include/asm-arm/arch-omap/irqs.h')
| -rw-r--r-- | include/asm-arm/arch-omap/irqs.h | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index c5bb05a69b81..3ede58b51db2 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h | |||
| @@ -37,8 +37,6 @@ | |||
| 37 | #define INT_DSP_MMU_ABORT 7 | 37 | #define INT_DSP_MMU_ABORT 7 |
| 38 | #define INT_HOST 8 | 38 | #define INT_HOST 8 |
| 39 | #define INT_ABORT 9 | 39 | #define INT_ABORT 9 |
| 40 | #define INT_DSP_MAILBOX1 10 | ||
| 41 | #define INT_DSP_MAILBOX2 11 | ||
| 42 | #define INT_BRIDGE_PRIV 13 | 40 | #define INT_BRIDGE_PRIV 13 |
| 43 | #define INT_GPIO_BANK1 14 | 41 | #define INT_GPIO_BANK1 14 |
| 44 | #define INT_UART3 15 | 42 | #define INT_UART3 15 |
| @@ -63,6 +61,8 @@ | |||
| 63 | #define INT_1510_RES2 2 | 61 | #define INT_1510_RES2 2 |
| 64 | #define INT_1510_SPI_TX 4 | 62 | #define INT_1510_SPI_TX 4 |
| 65 | #define INT_1510_SPI_RX 5 | 63 | #define INT_1510_SPI_RX 5 |
| 64 | #define INT_1510_DSP_MAILBOX1 10 | ||
| 65 | #define INT_1510_DSP_MAILBOX2 11 | ||
| 66 | #define INT_1510_RES12 12 | 66 | #define INT_1510_RES12 12 |
| 67 | #define INT_1510_LB_MMU 17 | 67 | #define INT_1510_LB_MMU 17 |
| 68 | #define INT_1510_RES18 18 | 68 | #define INT_1510_RES18 18 |
| @@ -75,6 +75,8 @@ | |||
| 75 | #define INT_1610_IH2_FIQ 2 | 75 | #define INT_1610_IH2_FIQ 2 |
| 76 | #define INT_1610_McBSP2_TX 4 | 76 | #define INT_1610_McBSP2_TX 4 |
| 77 | #define INT_1610_McBSP2_RX 5 | 77 | #define INT_1610_McBSP2_RX 5 |
| 78 | #define INT_1610_DSP_MAILBOX1 10 | ||
| 79 | #define INT_1610_DSP_MAILBOX2 11 | ||
| 78 | #define INT_1610_LCD_LINE 12 | 80 | #define INT_1610_LCD_LINE 12 |
| 79 | #define INT_1610_GPTIMER1 17 | 81 | #define INT_1610_GPTIMER1 17 |
| 80 | #define INT_1610_GPTIMER2 18 | 82 | #define INT_1610_GPTIMER2 18 |
| @@ -131,11 +133,11 @@ | |||
| 131 | #define INT_RTC_TIMER (25 + IH2_BASE) | 133 | #define INT_RTC_TIMER (25 + IH2_BASE) |
| 132 | #define INT_RTC_ALARM (26 + IH2_BASE) | 134 | #define INT_RTC_ALARM (26 + IH2_BASE) |
| 133 | #define INT_MEM_STICK (27 + IH2_BASE) | 135 | #define INT_MEM_STICK (27 + IH2_BASE) |
| 134 | #define INT_DSP_MMU (28 + IH2_BASE) | ||
| 135 | 136 | ||
| 136 | /* | 137 | /* |
| 137 | * OMAP-1510 specific IRQ numbers for interrupt handler 2 | 138 | * OMAP-1510 specific IRQ numbers for interrupt handler 2 |
| 138 | */ | 139 | */ |
| 140 | #define INT_1510_DSP_MMU (28 + IH2_BASE) | ||
| 139 | #define INT_1510_COM_SPI_RO (31 + IH2_BASE) | 141 | #define INT_1510_COM_SPI_RO (31 + IH2_BASE) |
| 140 | 142 | ||
| 141 | /* | 143 | /* |
| @@ -146,6 +148,7 @@ | |||
| 146 | #define INT_1610_USB_OTG (8 + IH2_BASE) | 148 | #define INT_1610_USB_OTG (8 + IH2_BASE) |
| 147 | #define INT_1610_SoSSI (9 + IH2_BASE) | 149 | #define INT_1610_SoSSI (9 + IH2_BASE) |
| 148 | #define INT_1610_SoSSI_MATCH (19 + IH2_BASE) | 150 | #define INT_1610_SoSSI_MATCH (19 + IH2_BASE) |
| 151 | #define INT_1610_DSP_MMU (28 + IH2_BASE) | ||
| 149 | #define INT_1610_McBSP2RX_OF (31 + IH2_BASE) | 152 | #define INT_1610_McBSP2RX_OF (31 + IH2_BASE) |
| 150 | #define INT_1610_STI (32 + IH2_BASE) | 153 | #define INT_1610_STI (32 + IH2_BASE) |
| 151 | #define INT_1610_STI_WAKEUP (33 + IH2_BASE) | 154 | #define INT_1610_STI_WAKEUP (33 + IH2_BASE) |
| @@ -239,10 +242,15 @@ | |||
| 239 | #define INT_24XX_SDMA_IRQ3 15 | 242 | #define INT_24XX_SDMA_IRQ3 15 |
| 240 | #define INT_24XX_CAM_IRQ 24 | 243 | #define INT_24XX_CAM_IRQ 24 |
| 241 | #define INT_24XX_DSS_IRQ 25 | 244 | #define INT_24XX_DSS_IRQ 25 |
| 245 | #define INT_24XX_MAIL_U0_MPU 26 | ||
| 246 | #define INT_24XX_DSP_UMA 27 | ||
| 247 | #define INT_24XX_DSP_MMU 28 | ||
| 242 | #define INT_24XX_GPIO_BANK1 29 | 248 | #define INT_24XX_GPIO_BANK1 29 |
| 243 | #define INT_24XX_GPIO_BANK2 30 | 249 | #define INT_24XX_GPIO_BANK2 30 |
| 244 | #define INT_24XX_GPIO_BANK3 31 | 250 | #define INT_24XX_GPIO_BANK3 31 |
| 245 | #define INT_24XX_GPIO_BANK4 32 | 251 | #define INT_24XX_GPIO_BANK4 32 |
| 252 | #define INT_24XX_GPIO_BANK5 33 | ||
| 253 | #define INT_24XX_MAIL_U3_MPU 34 | ||
| 246 | #define INT_24XX_GPTIMER1 37 | 254 | #define INT_24XX_GPTIMER1 37 |
| 247 | #define INT_24XX_GPTIMER2 38 | 255 | #define INT_24XX_GPTIMER2 38 |
| 248 | #define INT_24XX_GPTIMER3 39 | 256 | #define INT_24XX_GPTIMER3 39 |
| @@ -262,6 +270,12 @@ | |||
| 262 | #define INT_24XX_UART1_IRQ 72 | 270 | #define INT_24XX_UART1_IRQ 72 |
| 263 | #define INT_24XX_UART2_IRQ 73 | 271 | #define INT_24XX_UART2_IRQ 73 |
| 264 | #define INT_24XX_UART3_IRQ 74 | 272 | #define INT_24XX_UART3_IRQ 74 |
| 273 | #define INT_24XX_USB_IRQ_GEN 75 | ||
| 274 | #define INT_24XX_USB_IRQ_NISO 76 | ||
| 275 | #define INT_24XX_USB_IRQ_ISO 77 | ||
| 276 | #define INT_24XX_USB_IRQ_HGEN 78 | ||
| 277 | #define INT_24XX_USB_IRQ_HSOF 79 | ||
| 278 | #define INT_24XX_USB_IRQ_OTG 80 | ||
| 265 | #define INT_24XX_MMC_IRQ 83 | 279 | #define INT_24XX_MMC_IRQ 83 |
| 266 | 280 | ||
| 267 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and | 281 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and |